BONDED STRUCTURE AND METHOD FOR MANUFACTURING A BONDED STRUCTURE

Abstract

A bonded structure comprises a substrate component having a plurality of first pads arranged on or within a surface of the substrate component, and an integrated circuit component having a plurality of second pads arranged on or within a surface of the integrated circuit component. The bonded structure further comprises a plurality of connection elements physically connecting the first pads to the second pads. The surface of the integrated circuit component is tilted obliquely to the surface of the substrate component at a tilt angle that results from nominal variations of surface sizes of the first and second pads.

Claims

1. A bonded structure comprising a substrate component having a plurality of first pads arranged on or within a surface of the substrate component; an integrated circuit component having a plurality of second pads arranged on or within a surface of the integrated circuit component; and a plurality of connection elements physically connecting the first pads to the second pads, wherein the surface of the integrated circuit component is tilted obliquely to the surface of the substrate component at a tilt angle; the tilt angle results from nominal variations of surface sizes of the first and second pads.

2. The bonded structure according to claim 1, wherein each of the plurality of connection elements is distributed across the entire surface of a respective one of the plurality of first pads and a respective one of the plurality of second pads.

3. The bonded structure according to claim 1, wherein a diameter of the plurality of connection elements varies by less than 5%.

4. The bonded structure according to claim 1, wherein a vertical extent, measured from the surface of the substrate component in a perpendicular direction, of a respective one of the plurality of connection elements depends on the surface sizes of the first pad and the second pad connected to each other by said connection element.

5. The bonded structure according to claim 1, wherein the nominal variations of surface sizes of the first and second pads result from an increased or decreased nominal size of at least one of the first and second pads with respect to the remaining first and second pads.

6. The bonded structure according to claim 1, wherein the connection elements are solder elements, such as solder balls or solder disks.

7. The bonded structure according to claim 1, wherein a portion of the plurality of the connection elements also electrically connects the first pads to the second pads.

8. The bonded structure according to claim 1, wherein the substrate component comprises an optical waveguide and a coupling region for coupling in and/or out an optical radiation into and/or out of the optical waveguide.

9. The bonded structure according to claim 8, wherein the tilt angle corresponds to a coupling angle of the coupling region.

10. The bonded structure according to claim 8, wherein the coupling region comprises a grating coupler and/or a mirror.

11. The bonded structure according to claim 1, wherein the integrated circuit component comprises an optoelectronic component such as a light source and/or a photodetector.

12. The bonded structure according to claim 1, wherein the first pads and the second pads have circular pad surfaces.

13. The bonded structure according to claim 1, wherein the first pads and/or the second pads are arranged in recesses formed on the respective surface.

14. A sensing device comprising a bonded structure according to claim 1, wherein the sensing device is configured as a gas sensor, a particle sensor, a biosensor and/or a pressure sensor.

15. A method for manufacturing a bonded structure, the method comprising providing a substrate component having a plurality of first pads arranged on or within a surface of the substrate component; depositing a connection element on each of the plurality of first pads; arranging, by method of flip-chip assembly, an integrated circuit component having a plurality of second pads arranged on or within a surface of the integrated circuit component such that each of the plurality of second pads is located above a connection element; and connecting the integrated circuit component to the substrate component by means of a reflow; wherein the surface of the integrated circuit component is tilted obliquely to the surface of the substrate component at a tilt angle; and the tilt angle results from nominal variations of surface sizes of the first and second pads.

16. The method according to claim 15, wherein the method comprises performing a first step of reflow for connecting the connection elements with the first pads; and performing a second step of reflow for connecting the connection elements with the second pads.

17. The bonded structure according to claim 11, wherein the integrated circuit component comprises the optoelectronic component, which is a surface emitter such as a VCSEL.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG. 1 shows a cross-sectional schematic view of a substrate component and an integrated circuit component according to the improved concept before bonding;

[0042] FIGS. 2 to 4 show cross sections of intermediate steps of an exemplary embodiment of a bonded structure according to the improved concept; and

[0043] FIGS. 5 to 7 show exemplary embodiments of a finalized bonded structure according to the improved concept.

DETAILED DESCRIPTION

[0044] FIG. 1 shows a cross-sectional schematic view of an exemplary embodiment of a substrate component 20 and an integrated circuit component 10 according to the improved concept before bonding.

[0045] The substrate component 20 for example comprises a substrate portion 20a, which may be a semiconductor substrate such as silicon, and an integrated circuit portion 20b. The latter may be a processed part of the substrate component comprising active circuitry of an application-specific integrated circuit and/or components of a photonic integrated circuit such as waveguide structures and a coupling element. The substrate component 20 in the integrated circuit portion 20b further comprises the first pads 21, which are bonding pads arranged on or within the surface 22 of the substrate component 20 that faces away from the substrate portion 20a. In this embodiment the first pads 21 are arranged in recesses that are formed within the integrated circuit portion 20b. Before bonding, the first pads 21 are exposed to an environment of the substrate component 20.

[0046] In this specific embodiment, the integrated circuit portion 10b comprises a coupling region 23, e.g. a grating coupler, that is arranged in between the first pads 21. In general, different positions of the grating coupler 23 may be realized with respect to a vertical distance from the surface 22. Vertical in this context refers to the direction that is perpendicular to the surface 22. For example, the grating coupler 23 may be arranged closer to or further from the surface 22 compared to the first pads 21. In other words, the grating coupler 23 may be arranged in a level above the first pad level. This is the case, when wave guides and/or grating couplers are fabricated in a post processing flow, e.g. PE-CVD SiN deposition after passivation of the chip. Alternatively, the grating coupler 23 is positioned below the metal layer, i.e. below the first pad level. This is a typical situation for Si-based waveguides fabricated from SOI substrates.

[0047] The FIG. 1 further shows an exemplary integrated circuit component 10. The integrated circuit component analogously to the substrate component 20 comprises second pads 11 that are likewise bonding pads arranged on or within a surface 12 of the integrated circuit component 10 that may be referred to as the processed or top surface. The integrated circuit component 10 may likewise comprise active circuitry of an application-specific integrated circuit and/or components of a photonic integrated circuit. In particular, the integrated circuit component 10 may comprise a surface emitting light source such as a VCSEL that is configured to emit light through the surface 12 in a direction towards the substrate component 20 in this arrangement. Typically, a VCSEL is configured to emit light in a perpendicular manner relative to the main plane of extension of the die it is comprised by, which in this case corresponds to a vertical direction with respect to the surface 12.

[0048] Regarding the first and second pads 11, 21, a nominal variation of the surface sizes is realized by designing and fabricating at least one of the bonding pads with a substantially different surface. In this exemplary embodiment, one of the first pads 21 is realized with a substantially larger surface compared to the remaining first and second pads 11, 21.

[0049] FIG. 2 shows a cross section of an intermediate step of an exemplary embodiment of a bonded structure according to the improved concept. In this step, the connection elements 31 are placed onto the substrate component 20. The connection elements 31 are for example tin solder balls that are placed onto the bonding pads 21 by means of a ball drop stencil. The connection elements 31 are of a single type with respect to material, shape and size within tolerances of less than 5%, in particular less than 2%. This way, on a wafer scale a large number of connection elements 31 may be placed simultaneously via established mass production processes.

[0050] In order to maintain as low as possible tolerances, using pre-formed solder balls is preferred over solder paste screen print. Furthermore, in order to establish a sufficient physical and/or electrical contact after a reflow phase, flux 32 may be arranged on the first pads 21 prior to the placement of the connection elements 31. The flux may be applied either via spin-on or via a screen print process. The flux further aids in improving a self-aligning effect when the connection element 31 is in a liquid state during the reflow process as the flux removes potentially present oxide layers and it is promoting sufficient wetting between the connection element and the under bump metallization, UMB, which refers to a solderable layer on the first pads 21.

[0051] FIG. 3 shows a cross section of a further intermediate step of an exemplary embodiment of a bonded structure according to the improved concept. Following the placement of the connection element described and illustrated in FIG. 2, in this step a first reflow process as applied. The substrate component 20, or a wafer comprising a number of substrate components 20, and the connection elements 31 are heated up to a temperature of around 260° C. At this temperature, the flux 32 vaporizes while the connection elements 31 melt and fill the available pad size completely. In other words, the connection elements distribute across the entire surface of the first pads 21. After the reflow process, i.e. after cooling down such that the connection elements 31 re-solidify, the shape of the connection elements 31 is merely a function of their diameter and the surface sizes of the first pads 21. As gravity is negligible in this scale—the connection elements are typically of a diameter less than 500 μm—the surface tension of the material of the connection elements 31 causes a perfect ball shape.

[0052] The vertical extent of the connection elements 31 after the first reflow process is defined by the surface sizes of the first pads 21, i.e. the UBM surface, and by the diameter and/or volume of the connection elements 31. As it is clearly illustrated, the vertical extents of the connection elements 31 differ substantially due to the different surface sizes of the first pads 21.

[0053] FIG. 4 shows a cross section of a further intermediate step of an exemplary embodiment of a bonded structure according to the improved concept. Following the first reflow process, the integrated circuit component 10 is in this step arranged in a flip-chip manner, i.e. face down with its surface 12 facing the surface 22 of the substrate component 20. Likewise, the second pads 11 are aligned with the connection elements 31. Analogous to the first pads 21 prior to the placement of the connection elements 31, flux 32 may be also applied onto the second pads 11 prior to the placement of the integrated circuit component 10 onto the connection elements 31 for the same reasons as stated above and to improve an adhesion of the integrated circuit component 10 prior to a second reflow process. The integrated circuit component 10 is placed via a mass production capable pick-and-place process, which typically exhibits an alignment accuracy of around 25 μm. Likewise, a number of integrated circuit components 10 may be arranged on a wafer such that this step can be performed to place multiple integrated circuit components 10 over a corresponding number of substrate components 20.

[0054] FIG. 5 shows a cross section of a finalized exemplary embodiment of a bonded structure according to the improved concept. For finalizing the bonding, a second reflow process analogous to the first reflow process is applied causing the connection elements 31 to again melt and distribute also across the surfaces of the first second pads 11. After the reflow, i.e. after re-solidifying the connection elements 31, the bonded structure 1 with a tilt angle between the substrate component 20 and the integrated circuit component 10 is finalized.

[0055] During this second reflow step, the lateral position of the integrated circuit component 10, which may be a VCSEL die, is adjusted in a way that the surface energy of the connection elements 31 is minimized. Thus, the alignment of the first pads 21 to the second pads 11 is self-adjusted. As the position of the laser beam exit is aligned to the pads by means of lithography, a high degree of alignment accuracy of the laser beam to the grating element 23 is achieved.

[0056] FIG. 6 illustrates the geometrical aspects that define the tilt angle α. Due to employing a single type of connection elements 31 and nominally varying the surface sizes of the first and second pads 11, 21, the tilt angle α results from the distribution of the connection elements 31 across the respective ones of the first and second pads 11, 21. In particular, the tilt angle α is a function of the diameter and/or volume of the connection elements 31, the surfaces of the first and second pads 11, 21 and the pitch between the pads that is likewise used as open space for the light beam.

[0057] For example, as illustrated in FIG. 6, choosing circular pad surfaces for solder ball a to have a diameter of 75 μm and circular pad surfaces for solder ball b to have a diameter of 53 μm diameter in conjunction with a pitch of 166 μm and the solder balls being of a 80 μm diameter, which is a typical size, leads to a tilt angle of around 5° which corresponds to the coupling angle of common grating couplers. This tilt angle may be fine-tuned by further varying the pad surfaces, either individually or pairwise.

[0058] FIG. 7 illustrates an embodiment of a bonded structure that comprises a further integrated circuit component 10a. While the first integrated circuit component 10 comprises a light source, e.g. a VCESL, the further integrated circuit component 10a may comprise a photodetector for analyzing light received from said light source. The substrate component in this embodiment comprises a further coupling region 23a and a waveguide structure 24 for guiding the light towards the detector.

[0059] The tilt angle of the further integrated circuit component 10a with respect to the substrate component 20 may correspond to that of the integrated circuit component 10, e.g. in case the two grating elements 23, 23a have an equal coupling angle, or it may be different which may be achieved via different nominal variations of the surface sizes of the respective first and second pads 11, 21.

[0060] The connection elements 31 in various embodiments establish both a physical and electrical connection. Regarding the embodiment of FIG. 7, the light source and the photodetector may both be electrically connected to an ASIC that is either stacked to or is part of the substrate component 20. In the latter case, the photonic part may be realized via post processing on top of an ASIC.

[0061] The embodiments of the bonded structure 1 illustrated and described above may be conveniently employed in applications of optical sensing with wave guides. Applications include optical sensors based on ring resonators, Mach-Zehnder interferometers or Fabry-Perot interferometers. Si-based photonics is the technology making use of the advanced processing techniques established in semiconductor electronic devices. With respect to the light source Silicon, however, is an indirect semiconductor and therefore not suitable for light generation. Light sources like VCSELs and photodetectors operated at wavelengths larger than 1050 nm may be manufactured based on other types of semiconductors that have a direct band-gap such as III/V substrates that are in a final step bonded to a PIC.