LED and method of manufacture

Abstract

A light emitting diode (LED) comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and the p-doped portion. The light emitting region comprises: a light-emitting layer which emits light at a peak wavelength between 400 and 599 nm under electrical bias thereacross; a III-nitride layer located on the light-emitting layer; and a III-nitride barrier layer located on the III-nitride layer. The light emitting diode comprises a porous region of III-nitride material. An LED array and a method of manufacturing an LED with a peak emission wavelength between 400 nm and 599 nm under electrical bias are also provided.

Claims

1. A light emitting diode (LED), comprising: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion, the light emitting region comprising: a light-emitting layer which emits light at a peak wavelength between 400 and 599 nm under electrical bias thereacross; a III-nitride layer located on the light-emitting layer; and a III-nitride barrier layer located on the III-nitride layer, wherein the light emitting diode comprises a porous region of III-nitride material, and the LED further comprises a connecting layer of III-nitride material positioned between the n-doped portion and the porous region, and a non-porous intermediate layer of III-nitride material positioned between the porous region and the connecting layer, and the LED is configured to emit light with a FWHM of 50 nm or less.

2. An LED according to claim 1, wherein the light emitting diode comprises at least one feature selected from: (a) the light emitting region comprises at least one quantum well; or (b) the III-nitride layer comprises an aluminium gallium nitride layer which has a composition Al.sub.yGa.sub.(I-y)N, where y is in a range from 0.1 to 1.0; or (c) a UV or blue emitting InGaN/GaN or InGaN/InGaN superlattice or InGaN layer is located between the n-doped portion and the light emitting region.

3. A LED according to claim 1, in which the LED is an orange LED, and the light emitting region emits light at a peak wavelength between 590 and 599 nm, or between 592 and 597 nm under electrical bias.

4. A LED according to claim 1, in which the LED is a yellow LED, and the light emitting region emits light at a peak wavelength between 570 and 589 nm, or between 580 and 585 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.25x0.35.

5. An LED according to claim 1, in which the LED is a green LED, and the light emitting region emits light at a peak wavelength between 500 and 569 nm, or between 510 and 555 nm under electrical bias, or between 520 and 540 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.22x0.30.

6. An LED according to claim 1, in which the LED is a blue LED, and the light emitting region emits light at a peak wavelength between 450 and 499 nm, or between 460 and 490 nm under electrical bias, or between 470 and 480 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.12x0.22.

7. An LED according to claim 1, in which the LED is a violet LED, and the light emitting region emits light at a peak wavelength between 400 and 449 nm, or between 400 and 445, or between 410 and 440 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.05x0.17.

8. An LED according to claim 1, in which the LED emits light with a FWHM of 40 nm or less, or 30 nm or less, or 20 nm or less.

9. An LED according to claim 1, in which the thickness of the connecting layer is at least 100 nm.

10. An LED according to claim 1, in which the n-doped portion comprises an n-doped III-nitride layer, in which the n-doped portion comprises n-GaN, or n-InGaN, or a stack of alternating layers of n-GaN/n-InGaN, or a stack of alternating layers of n-InGaN/n-InGaN containing different concentrations of indium.

11. An LED according to claim 1, in which the n-doped portion comprises a single-crystalline n-doped III-nitride portion, in which the n-doped portion comprises a single-crystalline n-doped III-nitride layer having a planar top surface; and in which the porous region and each layer between the porous region and the single-crystalline n-doped III-nitride layer are planar layers having a respective top surface and a respective bottom surface that are parallel to the planar top surface of the single-crystalline n-doped III-nitride layer.

12. An LED according to claim 1, in which the light-emitting layer comprises one or more quantum wells, in which the light-emitting layer is a light-emitting indium gallium nitride layer, and the light-emitting indium gallium nitride layer and/or the quantum wells have the composition In.sub.xGa.sub.1-xN, in which 0.15x<0.35.

13. An LED according to claim 1, in which the LED comprises a cap layer of III-nitride material between the light-emitting layer and the p-doped portion; in which the p-doped portion comprises a p-doped III-nitride layer and a p-doped aluminium gallium nitride layer positioned between the p-doped III-nitride layer and the light emitting region; and/or in which the p-doped aluminium nitride layer is an electron-blocking-layer (EBL) between the cap layer and the p-type layer, in which the electron-blocking-layer contains 5-25 at % aluminium.

14. An LED array, comprising a plurality of LEDs according to claim 1.

15. A method of manufacturing an LED with a peak emission wavelength between 400 nm and 599 nm under electrical bias, comprising the step of overgrowing, over a porous region of III-nitride material, an LED structure comprising: an n-doped portion; a p-doped portion; and a light emitting region comprising a light-emitting layer which emits light at a peak wavelength between 400 and 599 nm under electrical bias thereacross, with a FWHM of 50 nm or less, and comprising forming the porous region of III-nitride material by electrochemical porosification through a non-porous region of III-nitride material, such that the non-porous region of III-nitride material forms a non-porous intermediate layer, and depositing one or more connecting lavers of III-nitride material on the surface of the intermediate layer of III-nitride material prior to overgrowing the n-doped region, the LED light emitting region and the p-doped region.

16. A method according to claim 15, in which the LED is an orange LED with a peak emission wavelength between 590 and 599 nm under electrical bias, or between 595 and 599 nm under electrical bias.

17. A method according to claim 15, in which the LED is a yellow LED with a peak emission wavelength between 570 and 589 nm under electrical bias, or between 575 and 585 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.25<x0.35.

18. A method according to claim 15, in which the LED is a green LED with a peak emission wavelength between 500 and 569 nm under electrical bias, or between 510 and 555 nm under electrical bias, or between 520 and 540 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.22x0.30.

19. A method according to claim 15, in which the LED is a blue LED, and the light emitting region emits light at a peak emission wavelength between 450 and 499 nm under electrical bias, or between 455 and 495 nm under electrical bias, or between 460 and 480 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.18x0.25.

20. A method according to claim 15, in which the LED is a violet LED, and the light emitting region emits light at a peak wavelength between 400 and 449 nm under electrical bias, or between 410 and 435 nm under electrical bias; and/or in which the light-emitting layer has the composition In.sub.xGa.sub.1-xN, in which 0.15x0.22.

21. A method according to claim 15, in which the light emitting layer is an indium gallium nitride layer with the composition In.sub.xGa.sub.1-xN, in which 0.15x0.40.

22. A method according to claim 15, comprising overgrowing the light emitting region in a temperature range of 600 C.-800 C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will now be described with reference to the figures, in which:

(2) FIG. 1 illustrates a porous template suitable for an LED according to the present invention;

(3) FIGS. 2illustrate the steps of manufacturing an LED according to a preferred embodiment of the present invention;

(4) FIG. 19 is a graph of normalised electroluminescence (EL) intensity vs wavelength, for an InGaN LED over a porous region;

(5) FIG. 20 is a graph of normalised electroluminescence (EL) intensity vs wavelength at different current injections, for an InGaN LED on a non-porous substrate;

(6) FIG. 21 is a graph of normalised electroluminescence (EL) intensity vs wavelength at different current injections, for the same InGaN LED as FIG. 15 grown over a porous region;

(7) FIG. 22 is an I-V curve measured for InGaN micro-LEDs of different pixel sizes on a non-porous substrate, with the inset image showing yellow emission;

(8) FIG. 23 is an I-V curve measured for InGaN micro-LEDs of different pixel sizes on a porous substrate, with the inset image showing red emission;

(9) FIG. 24A is a graph of intensity vs EL wavelength comparing three types of LED grown on different templates;

(10) FIG. 24B is a graph of intensity vs EL wavelength comparing three types of LED grown on different templates;

(11) FIG. 24C is a graph of intensity vs EL wavelength comparing two types of LED grown on different templates.

(12) FIG. 1 illustrates a porous template suitable for a LED according to the present invention.

(13) The porous template comprises a porous region of III-nitride material on a substrate, with a non-porous layer of III-nitride material arranged over the top surface of the porous region. Optionally there may be further layers of III-nitride material between the substrate and the porous region.

(14) As described in more detail below, the porous region may be provided by epitaxially growing an n-doped region of III-nitride material and then an undoped layer of III-nitride material, and porosifying the n-doped region using the porosification process as set out in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728).

(15) As described above, this porosification leads to strain relaxation in the crystal lattice, which means that subsequent overgrowth of further semiconductor layers benefit from reduced compressive strain in their lattices.

(16) The porous region may comprise one or more layers one or more III-nitride materials, and may have a range of thicknesses, all while still providing the strain relaxation benefit that shifts the wavelength of InGaN light emitting layers overgrown above the porous region. In preferred embodiments, the porous region may for example comprise GaN and/or InGaN.

(17) A variety of LED structures may be overgrown over the template illustrated in FIG. 1.

(18) In particular, LED structures containing InGaN light emitting layers, which are known in the art for the manufacture of yellow or green LEDs, may be overgrown on the porous template using standard LED manufacturing steps. When grown on the porous template, however, a LED structure which normally emits at a first wavelength, will emit at a red-shifted longer wavelength.

(19) In this way, the use of a porous region of III-nitride material as a template or pseudo-substrate for overgrowth of known InGaN LED structures allows longer-wavelength LEDs to be manufactured in a straightforward manner.

(20) In a preferred embodiment, a LED according to the present invention comprises the following layers, and may be manufactured using the step by step process described below.

(21) The following description of the LED structure relates to a Top emission architecture being described from the bottom up, but the invention is equally applicable to a bottom emission architecture.

(22) FIG. 2Substrate & III-Nitride Layer for Porosification

(23) A compatible substrate is used as a starting surface for epitaxy growth. The substrate may be Silicon, Sapphire, SiC, -Ga2O3, GaN, glass or metal. The crystal orientation of the substrates can be polar, semi-polar or non-polar orientation. The substrate size may vary from 1 cm.sup.2, 2 inch, 4 inch, 6 inch, 8 inch, 12 inch, 16 inch diameters and beyond, and the substrate may have a thickness of greater than 1 m, for example between 1 m and 15000 m.

(24) A layer or stack of layers of III-nitride material is epitaxially grown on the substrate. The III-nitride layer may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layer).

(25) The thickness T of the III-nitride stack is preferably at least 10 nm, or at least 50 nm, or at least 100 nm, for example between 10-10000 nm.

(26) The III-nitride layer comprises a doped region having an n-type doping concentration between 110.sup.17 cm.sup.3-510.sup.20 cm.sup.3. The III-nitride layer may also comprise an undoped cap layer of III-nitride material over the doped region.

(27) The doped region may terminate at the exposed upper surface of the III-nitride layer, in which case the surface of the layer will be porosified during electrochemical etching.

(28) Alternatively, the doped region of the III-nitride material may be covered by an undoped cap layer of III-nitride material, so that the doped region is sub-surface in the semiconductor structure. The sub-surface starting depth (d) of the doped region may be between 1-2000 nm for example.

(29) FIG. 3Porosification to Porous Region

(30) After it is deposited on the substrate, the III-nitride layer (or stack of layers) is porosified with a wafer scale porosification process as set out in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728). During this process, the doped region of the III-nitride material becomes porous, while any undoped region of III-nitride material does not become porous.

(31) Following the porosification step, the structure therefore contains a porous region which remains where there was previously n-doped III-nitride material, and optionally a non-porous intermediate layer overlying the porous region.

(32) The degree of porosity of the porous region is controlled by the electrochemical etching process and may be between 1%-99% porosity, preferably between 20% to 90% porosity or between 30%-80%, though lesser or greater porosities could also be employed.

(33) The thickness of the porous region following porosification is preferably greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm. However, the thickness of material required to obtain the strain relaxation benefit provided by the porous region may vary depending on the type of III-nitride material from which the porous region is made.

(34) The porous region created by the porosification process may be a bulk layer of a III-nitride material having a uniform composition and a uniform porosity throughout the layer. Alternatively the porous region may comprise multiple layers of porous material of different compositions and/or porosities, forming a porous stack of III-nitride material. For example the porous region may be a continuous layer of porous GaN, or a continuous layer of porous InGaN, or a stack comprising one or more layers of porous GaN and/or one or more layers of porous InGaN. The inventors have found that the strain relaxation benefit of the porous region for overgrowth is obtainable across a wide range of porous regions having different thicknesses, compositions, and layered stacks.

(35) In the embodiment illustrated in the Figures, the porous region is a single porous layer.

(36) Where there is an undoped cap layer of III-nitride material over the doped region, the undoped region remains non-porous following through-surface porosification of the doped region below. The thickness D of this non-porous cap layer may preferably be at least 2 nm, or at least 5 nm, or at least 10 nm, preferably 5-3000 nm. Providing an undoped cap layer over the doped region advantageously leads to a non-porous layer of III-nitride material covering the porous region following porosification. This non-porous cap layer may advantageously allow better overgrowth of further material above the porous region.

(37) As the porosification method of PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728) can be carried out on entire semiconductor wafers, no processing/patterning/treatment is needed to prepare the template for porosification.

(38) FIG. 4Connecting Layer

(39) After formation of the porous layer, a III-nitride LED epitaxy structure can be grown onto the porous template/pseudo-substrate provided by the porous layer and the non-porous cap layer.

(40) The first layer for growth of the LED structure onto the template may be termed a connecting layer 1.

(41) Although it is possible for an LED epitaxial structure to be grown directly onto the non-porous cap layer, it is preferable that a connecting layer 1 is provided over the cap layer before overgrowth of the LED structure. The inventors have found that the use of a III-nitride connecting layer 1 between the porous region and the LED epitaxy structure may advantageously ensure a good epitaxial relationship between the LED and the porous template/substrate. The growth of this layer makes sure that subsequent overgrowth on top of the connecting layer is smooth and epitaxial and suitably high quality.

(42) The connecting layer 1 is formed of III-nitride material and may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layer).

(43) The connecting layer can be a doped or un-doped layer. The connecting layer can optionally be doped with suitable n-type dopant materials, e.g Si, Ge, C, O. The III-nitride layer may have a doping concentration between 110.sup.17 cm.sup.3-510.sup.20 cm.sup.3.

(44) The thickness of this connecting layer is preferably at least 100 nm, and can be for example between 100-10000 nm.

(45) FIG. 5N-Doped Region

(46) After the growth of the connecting layer, a bulk n-doped III-nitride region 2 is grown.

(47) The n-doped region 2 may comprise or consist of a III-nitride layer containing Indium, or a stack of thin III-nitride layers with or without indium, or a bulk layer or stack of III-nitride layers with a variation in atomic percentage of indium across the layer or stack is grown. For example, the n-doped region may be a layer of n-GaN, or a layer of n-InGaN, or alternatively the n-doped region may be a stack of n-GaN/n-InGaN alternating layers, or a stack of n-InGaN/n-InGaN alternating layers having different quantities of indium in alternating layers.

(48) Preferably the n-doped region 2 comprises indium, so that the crystalline lattice of the n-doped region has similar lattice parameters to the lattice of the InGaN light emitting layer in the LED. The Indium atomic percentage in the n-doped region may vary between 0.1-25% for example.

(49) In preferred embodiments, the indium content of the n-doped region is within 20 at %, or within 15 at %, or within 10 at %, or within 5 at % of the indium content of the InGaN light emitting layer. This may advantageously ensure that the lattice parameters of the n-doped region are sufficiently similar to those of the InGaN light emitting layer to avoid excessive strain between these layers.

(50) The total thickness of the n-doped region may be at least 2 nm, or at least 5 nm, or at least 10 nm, or at least 20 nm. The thickness of the n-doped region may vary between 2 nm-5000 nm, or even thicker, for example. If the n-doped region comprises a stack of layers, the thickness of each individual layer in the stack is preferably between 1-40 nm.

(51) The n-doped region preferably has an n-type doping concentration between 110.sup.17 cm.sup.3-510.sup.20 cm.sup.3, preferably between 110.sup.18 cm.sup.3-510.sup.20 cm.sup.3, particularly preferably greater than 110.sup.18 cm.sup.3.

(52) FIG. 6Light Emitting Region

(53) After growth of the n-doped region 2, an underlay or pre-layer or pre-well (not labelled in FIG. 6) may be grown, in order to release the strain in the light emitting layer(s). The underlay can be a single layer or stack/multi-layers of GaN, InGaN, or GaN/InGaN, or InGaN/InGaN. Alternatively, the underlay may have a structure similar to InGaN QW/GaN quantum barrier but with a lower proportion of indium. For example, before depositing the light emitting layer having a relatively high proportion of indium, an underlay consisting of a layer of bulk InGaN having a lower proportion of indium than the light emitting layer may be grown. Alternatively, the underlay may take the form of an InGaN dummy QW with a lower proportion of indium than the light emitting layer, and one or more GaN quantum barriers.

(54) After growth of the n-doped region 2 and optionally the underlay, a light emitting region 3 containing an InGaN light emitting layer is grown.

(55) The light emitting region 3 may contain at least one InGaN light emitting layer. Each InGaN light emitting layer may be an InGaN quantum well (QW). Preferably the light emitting region may comprise between 1-7 quantum wells. Adjacent quantum wells are separated by barrier layers of III-nitride material having a different composition to the quantum wells.

(56) The light emitting layer(s) may be referred to as quantum wells throughout the present document, but may take a variety of forms. For example, the light emitting layers may be continuous layers of InGaN, or the layers may be continuous, fragmented, broken layers, contain gaps, or nanostructured so that the quantum well effectively contains a plurality of 3D nanostructures behaving as quantum dots.

(57) The quantum wells and barriers are grown in a temperature range of 600-800 C.

(58) Each quantum wells consists of an InGaN layer with atomic indium percentage between 15-40%. Preferably the light-emitting indium gallium nitride layer(s) and/or the quantum wells have the composition In.sub.xGa.sub.1-xN, in which 0.05x0.35, preferably 0.12x0.30 or 0.22x0.30, particularly preferably 0.22x0.27.

(59) The thickness of each quantum well layer may be between 1.5-8 nm, preferably between 1.5 nm and 6 nm, or between 1.5 nm and 4 nm. The quantum wells may be capped with a thin (0.5-3 nm) III-nitride QW capping layer, which may contain one or a combination of these elements: Al, Ga, In (ternary of quaternary layer)

(60) The QW capping layer, which is the layer added immediately after QW growth, can be AlN, AlGaN of any Al % 0.01-99.9%, GaN, InGaN of any In % 0.01-30%.

(61) The III-nitride QW barriers separating the light emitting layers (quantum wells) may contain one or a combination of these elements: Al, Ga, In (ternary of quaternary layer). The QW barrier can be AlN, AlGaN of any Al % 0.01-99.9%, GaN and InGaN of any In % 0.01-15%. Preferably the QW barrier layers contain AlN and/or AlGaN.

(62) The QW capping layer(s) and QW barriers are not indicated with individual reference numerals in the Figures, as these layers form part of the light emitting region 3.

(63) The QW capping layers may be grown after each QW but before the barrier growth. For example, if an LED contains 3 QWs then each of these QWs may be overgrown with a QW capping layer and then a QW barrier layer, so that the light emitting region contains 3 such QW capping layers and three such QW barrier layers. 1. One can grow the cap at the same conditions as the QW. 2. One can ramp without growth to higher temperature, and grow this cap (effectively this is an annealing step) and here the ramp can be carried out in a different gas mixture. 3. One can ramp and grow during the temperature ramp.

(64) The design of the light-emitting region may be varied according to parameters that are well understood in the art and conventional in LED design. For example, depending on the target EL emission wavelength of the LED, the composition, thickness and number of light-emitting layers and barrier layers may be varied. As described earlier in the application, the indium content of InGaN light-emitting layers may be increased when longer-wavelength emission is desired.

(65) As described above, the present invention may be provided by growing a known LED structure, known to emit at a first wavelength under electrical bias, over a template containing a porous region. The strain relaxation caused by the porous region beneath the LED structure enables incorporation of more indium into the light-emitting layer(s) under the same growth conditions, so the wavelength of the resulting LED is red-shifted when compared to the same LED structure grown under the same conditions over a non-porous substrate. A greater variety of emission wavelengths may therefore be achieved using the present invention than has been possible in the prior art, and in particular, longer wavelengths can be achieved at higher InGaN growth temperatures. This leads to superior quality crystal structures in the LED, and thus higher performance LEDs.

(66) For the manufacture of longer-wavelength LEDs the large amount of Indium in the light emitting layer(s) makes the capping layer even more important, as previous attempts to manufacture longer wavelength yellow, orange or red LEDs have failed due to not enough Indium being incorporated. So capping is very important to make sure that there is sufficient Indium trapped within the light emitting region.

(67) FIG. 7Cap Layer

(68) After growth of the light emitting layer(s) a non-doped cap layer 4 is grown. Non-doped cap layer 4 may be termed a light-emitting-region cap layer, as this layer is formed after growth of the complete light emitting region, for example after the growth of the stack of QWs, QW capping layers and QW barrier layers.

(69) The cap layer (light-emitting-region cap layer) 4 is a standard layer which is very well known in the growth schemes for III-nitride LEDs.

(70) The thickness of the cap layer can be between 5-30 nm, preferably between 5-25 nm or 5-20 nm.

(71) The purpose of the light-emitting-region cap layer 4, is to protect the indium in the light emitting region (QW stack) and prevent it from desorbing/evaporating during subsequent processing. Because the InGaN QW is normally grown at lower temperature, that is not favourable for GaN/AlGaN, there is typically a temperature ramp step needed before further layers can be overgrown above the light emitting region. The cap layer is used to ensure that the InGaN light emitting layer(s) are properly capped and protected, so that there is a chance and time window to change the p-doped layer growth conditions for better material quality. The light-emitting-region cap layer 4 also ensures that no Mg dopant is entering the QW region during the growth of p-type layers.

(72) Electron Blocking Layer (EBL)

(73) After the growth of quantum wells, capping and barrier layers, an electron blocking III-nitride layer (EBL) 5 containing Aluminium is grown. The Al % can be between 5-25% for example, though higher Al content is possible.

(74) The EBL is doped with a suitable p-type doping material. The p-type doping concentration of the EBL is preferably between 51.sup.18 cm.sup.3-810.sup.20 cm.sup.3

(75) The thickness of the EBL can be between 10-50 nm, preferably 20 nm.

(76) FIG. 8P-Doped Layer

(77) A p-doped layer 6 is grown above the electron blocking layer (EBL) 5.

(78) The p-type region is preferably doped with Mg, and the p-type doping concentration of the p-type layer is preferably between 510.sup.18 cm.sup.3-810.sup.20 cm.sup.3.

(79) The p-doped III-nitride layer may contain In and Ga.

(80) The doping layer is preferably between 20-200 nm thick, particularly preferably between 50-100 nm thick. The doping concentration may vary across the p-type layer and can have a spike in doping levels in the last 10-30 nm of the layer towards the LED surface, in order to allow better p-contact.

(81) For activation of Mg acceptors in the p-doped layer, the structure may be annealed inside of MOCVD reactor or in an annealing oven. The annealing temperature may be in the range of 700-850 C. in N.sub.2 or in N.sub.2/O.sub.2 ambient.

(82) As both the EBL and the p-doped layer are p-type doped, these layers may be referred to as the p-doped region.

(83) FIG. 9Transparent Conducting Layer

(84) The stack of active semiconductor layers is covered with a transparent conducting layer 7. The transparent conducting layer can be made of Ni/Au, indium tin oxide, indium zinc oxide, graphene, Pd, Rh, silver, ZnO etc., or a combination of these materials.

(85) The thickness of the transparent conducting layer can be between 10-250 nm.

(86) Transparent conducting layers are well known in the art, and any suitable material and thickness may be used.

(87) An annealing step may be required for making the p-contact ohmic.

(88) FIG. 10

(89) Depending on the LED structure being manufactured, the semiconductor structure may be processed into LED, mini-LED or micro-LED devices.

(90) Normal LEDs are typically larger than 200 m (referring to the lateral dimensions of width and length of the LED structure. Mini-LEDs are typically 100-200 m in lateral size, while Micro-LEDs are typically less than 100 m in size.

(91) FIG. 10 onwards illustrates the semiconductor structure following etching of layers 2-7 of the semiconductor structure into multiple discrete LED stacks, or mesas, each having the same structure.

(92) The steps of LED fabrication are conventional and well-known to those skilled in the art. The order of the following fabrication steps are not specific to the present invention, and the skilled person will be appreciated that LED devices within the scope of the present invention may be prepared using alternative fabrication steps to those illustrated below. For the purposes of illustration only, however, one preferred fabrication route to prepare LEDs according to the present invention is described below.

(93) In the next step, the transparent conducting layer 7 is structured in such a way that it covers only the top surface of the active emission element. The structuring can be done using standard semiconductor processing methods that included resist coating and photolithography. The transparent conducting layer is etched by using wet chemistry or a sputter etch process using Argon. This step is followed by wet or dry etching of the III-nitride structure. An inductively couple plasma reactive ion etching, only reactive ion etching or neutral beam etching is used to create mesas in the III-nitride layer. The dry etch process may include either one or more of Cl, Ar, BCl.sub.3, SiCl.sub.4 gases.

(94) The purpose of this step is to isolate the individual emitting elements and access the buried n-doped layer of the p-n junction.

(95) After the dry etch process a wet etch process is done to remove the dry etching damage from the sidewalls of the mesa. The wet chemistry may involve KOH (1-20%), TMAH or other base chemistries.

(96) FIG. 11Passivation

(97) The next step is to deposit a passivation layer 8 or a combination of passivation layers. The starting passivation layer can be Al2O3 (10-100 nm) (deposited by atomic layer depositions) followed by sputtered or plasma enhanced chemical vapor deposited SiO2, SiN or SiON (50-300 nm).

(98) The Al2O3 can be deposited between 50-150 C.

(99) The SiO2, SiN and SiON can be deposited between 250-350 C.

(100) The sputter process can be done at room temperature.

(101) FIGS. 12-13

(102) The next step is to create openings in the oxide passivation layer 8 to expose the top of the LED structure. This can be done via wet or dry etching or a combination of both.

(103) For wet etching buffered oxide etch, diluted hydrofluoric acid phosphoric acid or a mixture of these can be used.

(104) Channels are also etched through the connecting layer 1 between the LED structures, followed by electrically isolating the LED structures from one another by depositing dielectric mask material 8 into the channels, so that the LEDs are operable independently from one another.

(105) The next step in device fabrication is to cover the transparent conducting layers 7 on the p-doped layers 6 with metal layers to act as electrical p-contacts. The covering can be done with a single step or multiple steps. The metals can be covering the pixels completely or partially. In this example a single step is used to simplify the details.

(106) The metal may contain Ti, Pt, Pd, Rh, Ni, Au. The thickness of the complete metal stack can be between 200-2000 nm.

(107) FIG. 14Exposing Connecting Layer

(108) Standard photolithography techniques can be used to create openings in the second mask layer 8 to expose a plurality of regions of the connecting layer 1. The size of the openings can vary between 200 nm-50000 nm. This distance between the openings can be between 500 nm-30000 nm. The opening are creating only in the regions of the wafer that are not occupied by LED structures.

(109) Dry etching is preferably used to etch the second mask layer 8 using fluorine based gases.

(110) FIG. 15N-Contacts

(111) The next step in device fabrication is to cover the openings in the oxide 8 with metal contacts 10 to access the connecting layer 1, which is in electrical contact with the n-doped layers of the LED structures. The covering can be done with a single step or multiple steps. The metals can be covering the pixels completely or partially. In this example a single step is used to simplify the details.

(112) The metal may contain Ti, Pt, Pd, Rh, Ni, Au. The thickness of the complete metal stack can be between 200-2000 nm.

(113) FIGS. 16-18

(114) After this processing, the substrate can be thinned, and/or the porous region can be removed so that the connecting layer 1 is exposed.

(115) Surface structuring or texturing can be done on the substrate, at the porous region, or layer 1 to enhance the light output and control the emission angle, as well as other optical engineering and design.

(116) Finally, the wafer/devices can be flipped, and bonded to another carrier substrate either can be silicon/sapphire or any type as passive devices, alternatively, the devices can be bonded to a CMOS silicon backplane for active matrix micro-LED display panel.

(117) As shown in FIG. 16, the top side of the device may be bonded to another carrier wafer/substrate/backplane 11, or to a microdriver circuit board to form an array of pixels.

(118) As shown in FIG. 17, the substrate may then be removed from the device, and the bottom-side of the device may be bonded to a cover glass or transparent material 12.

(119) As shown in FIG. 18, the substrate and the porous and non-porous region may be removed from the device. The top side of the device may be bonded to another carrier wafer/substrate/backplane 11, or to a microdriver circuit board to form an array of pixels. The bottom-side of the device may be bonded to a cover glass or transparent material 12.

(120) The skilled person will understand that the emission wavelengths of the individual LED structures may be controlled by altering the composition and layer structures of the LED structures according to known principles of LED construction. Thus a variety of variable-wavelength LED devices emitting over different emission wavelength ranges may be provided using the present invention, and colour combinations other than green to red may be provided.

(121) FIGS. 19-23

(122) FIG. 19 shows an example of an InGaN LED over a porous layer that emits at a peak wavelength of around 625 nm due to the wavelength red-shift caused by the porous region.

(123) FIGS. 20 and 21 compare the emission characteristics of an InGaN LED on a non-porous substrate (FIG. 20) and the same InGaN LED grown on a template comprising a porous layer of III-nitride material. Comparison of these two graphs demonstrates the shift towards longer emission wavelengths caused by the porous underlayer, as the emission of the LED on the porous template is consistently between 21 nm and 45 nm longer than that of the same LED on the non-porous template.

(124) FIGS. 22 and 23 compare the I-V characteristics of yellow InGaN micro-LEDs on a non-porous substrate (FIG. 22) with red InGaN micro-LEDs on a template containing a porous layer.

(125) FIGS. 24A-24C

(126) The experiments of FIGS. 24A-24C were carried out on Chip on Wafer (CoW) LEDs to test the wavelength shift at blue, green and yellow wavelengths.

(127) FIGS. 24A-C are graphs of the luminous intensity, or brightness, vs the peak EL emission wavelength emitted by an array of chip-on-wafer micro-LEDs. FIGS. 24A-C were obtained for LEDs configured to emit at a variety of EL wavelengths between 400 nm and 600 nm, showing that the red-shift effect of the present invention is obtained across a wide range of LEDs with different emission wavelengths.

(128) In FIG. 24A, a standard 450 nm LED A grown on GaN and flat sapphire substrate (FSS) has been tested, and found to emit light mainly in the range of 440-450 nm under electrical bias. Data for LED A is shown in pink data points in FIG. 24A.

(129) An LED structure LED B known to emit light at around 420 nm has been grown on a non-porous GaN template. As shown in FIG. 19A, LED B emits light around 425-425 nm under electrical bias. Data for LED B is shown in dark red data points in FIG. 24A.

(130) In order to illustrate the wavelength red-shift provided by the present invention, LED C with the same LED structure as LED B has been grown on a template containing a porous GaN region. Data for LED C is shown in green data points in FIG. 24A. LED B (which emits at a peak wavelength of around 420 nm on a non porous substrate) was chosen as a suitable LED structure for the target of providing an LED C with a peak EL emission wavelength in the range of 430-450 nm, so that LED C emits in the violet region of the visible spectrum when overgrown on the porous template.

(131) LEDs B and C have the same LED structure (the same active region and n- and p-type regions) and were grown in the same epitaxial growth run under identical growth conditions. As shown in FIG. 24A, however, the fact that LED C is formed over a porous region leads to significant differences in emission behaviour. Firstly, LED C on porous GaN emits at longer wavelengths than LED B, in the range of 430-445 nm compared to 420 nm. The overgrowth over the porous region has thus caused a wavelength red-shift averaging around 10-25 nm for the LEDs in the array. Secondly, the formation of LED C over a porous GaN template rather than a non-porous template has led to a significant increase in LED emission intensity, as a result of the improved quality of the semiconductor layers overgrown over the strain relaxed porous region.

(132) In FIG. 24B, a standard green LED D was grown on a non-porous GaN template, and found to emit light mainly in the range of 510-530 nm under electrical bias. Data for LED D is shown in green data points in FIG. 24B.

(133) The same green LED structure was overgrown over a similar GaN template containing a porous GaN layer to form LED E. Data for LED E is shown in dark red data points in FIG. 19B. LED E was found to emit light at longer wavelengths of averaging 540-560 nm, compared to the 520 nm emission wavelength of LED D, due to the red-shift resulting from the improved quality of the semiconductor layers overgrown over the strain relaxed porous region.

(134) FIG. 24C shows comparative data for LED F, which is an LED structure known to emit light at around 540-560 nm nm under electrical bias. Data for LED F is shown in blue data points in FIG. 24C.

(135) In order to illustrate the wavelength red-shift provided by the present invention, LED G with the same LED structure as LED F has been grown on a template containing a porous GaN region. Data for LED G is shown in dark red data points in FIG. 24C. LED F (which emits at a peak wavelength of around 540-560 nm on a non porous substrate) was chosen as a suitable LED structure for the target of providing an LED G with a peak EL emission wavelength in the range of 550-570 nm, so that LED G emits in the green region of the visible spectrum when overgrown on the porous template.

(136) LEDs F and G have the same LED structure (the same active region and n- and p-type regions) and were grown in the same epitaxial growth run under identical growth conditions. As shown in FIG. 24C, however, the fact that LED G is formed over a porous region means that LED G on porous GaN emits at longer wavelengths than LED F, in the range of 550-570 nm compared to 540-560 nm. As the strain relaxation caused by the porous region allows LED G to incorporate more indium than LED F under the same growth conditions, LED G results in longer-wavelength emission.