Abstract
A differential amplifier circuit is provided. The circuit includes a PWM modulator for generating a PWM signal representative of a difference between the first and the second staircase-like reference signals and the digital input signal, a DM-IDAC for receiving the PWM signal and providing a first and second differential mode current, a CM-IDAC for receiving the PWM signal and providing a common mode current, first and second loop integrators, and first and second comparators; each loop integrator comprising virtual ground node terminal for receiving the differential mode current, the common mode current, and a feedback signal from an output stage of the differential amplifier circuit via a feedback loop, and integrator output terminal for providing loop integrator output signal proportional to an integral of the signals received at the virtual ground node terminal, the comparators receiving the loop integrator output signal, and triangular reference signal.
Claims
1. A differential amplifier circuit, comprising: a pulse wide modulation, PWM, modulator configured to receive a digital input signal to generate a PWM signal; a differential-mode current digital to analog converter, DM-IDAC configured to receive the PWM signal from the PWM modulator and provided a first and second differential mode current I.sub.DMP and I.sub.DMN; a common-mode current digital-to-analog converter, CM-IDAC configured to receive the PWM signal from the PWM modulator and provide a common mode current, I.sub.CM; a first and a second loop integrator; and a first and a second comparator, wherein each of the first and second loop integrators comprise: a virtual ground node terminal configured to receive the first and second differential mode current from the DM-IDAC, the common mode current from the CM-IDAC, and a feedback signal from an output stage of the differential amplifier circuit via a feedback loop; and an integrator output terminal configured to provide a loop integrator output signal, which is proportional to an integral of the signals received at the virtual ground node terminal; wherein each of the first and second comparators comprise: a comparator non-inverting input terminal configured to receive the loop integrator output signal; a comparator inverting input terminal configured to receive a triangular reference signal; and a comparator output terminal configured to provide a drive signal suitable for driving the output stage of the differential amplifier circuit.
2. The differential amplifier circuit according to claim 1, further comprising a first set and a second set of loop integrators and a first and a second sum module wherein the first set of loop integrators is arranged in cascade with the first loop integrator, the second set of loop integrators is arranged in cascade with the second loop integrator, the first sum module is arranged to provide a weighted sum of the outputs of the first loop integrator and each of the loop integrators in the first set of loop integrators and the second sum module is arranged to provide a weighted sum of the outputs of the second loop integrator and each of the loop integrators in the second set of loop integrators.
3. The differential amplifier circuit according to claim 1, wherein the DM-IDAC comprises four current sources and four switches wherein each of the current sources is arranged to generate a first reference current, I.sub.REF, and wherein the DM-IDAC is arranged to receive four control signals to respectively control the four switches and to generate, based on the received four control signals, the first and second differential mode currents, I.sub.DMP and I.sub.DMN, to drive the virtual ground nodes terminals.
4. The differential amplifier circuit according to claim 3, wherein the PWM modulator is a delta-PWM, DPWM, modulator, and the four control signals are generated by the DPWM modulator by comparing the digital input signal respectively to a first and second staircase-like reference signals, REF.sub.N, REF.sub.P, and wherein each of the first and second differential mode currents, I.sub.DMP and I.sub.DMN, can be I.sub.REF, I.sub.REF or zero depending on the four control signals.
5. The differential amplifier circuit according to claim 4, wherein the first differential mode current is equal to: IREF if the first staircase-like reference signal, REFP, is below the digital input signal; IREF if the second staircase-like reference signal, REFN, is above the digital input signal; and Zero otherwise; and wherein the second differential mode current, IDMN, is equal to: IREF if the first staircase-like reference signal, REFP, is below the inverse of the digital input signal; IREF if the second staircase-like reference signal, REFN, is above the inverse of the digital input signal; and Zero otherwise.
6. The differential amplifier circuit according to claim 1, wherein the CM-IDAC comprises other four current sources and other four switches wherein each of the other four current sources is arranged to generate a second reference current, and wherein the CM-IDAC is arranged to receive other two control signals to respectively control the other four switches and to generate, based on the received other two control signals, the common mode current I.sub.CM to drive the virtual ground nodes terminals.
7. The differential amplifier circuit according to claim 4, wherein the other two control signals are generated by the DPWM modulator and wherein the common current I.sub.CM is equal to I.sub.REF/2 or to I.sub.REF.
8. The differential amplifier circuit according to claim 5, wherein the common mode current I.sub.CM is equal to: IREF if a shifted version of the first staircase-like reference signal, REFP is below the digital input signal and a shifted version of the second staircase-like reference signal, REFN, is above the inverse of the digital input signal; IREF/2 if the shifted version of the first staircase-like reference signal, REFP is below the digital input signal or the shifted version of the second staircase-like reference signal, REFN is above the inverse of the digital input signal; and Zero otherwise.
9. The differential amplifier circuit according to claim 6, wherein the shifted version of the first and second staircase-like reference signals is respectively generated by adding a value N.sub.SKIP to the first staircase-like reference signal and by subtracting the value N.sub.SKIP to the second staircase-like reference signal.
10. The differential amplifier circuit according to claim 1, further configured to generate a feedback common current I.sub.CMFB, wherein the feedback common current I.sub.CMFB is equal to I.sub.REF/2 between a first and a second time wherein the first time is a time at which the triangular reference signal reaches its minimum value and the loop integrator output signal of the first loop integrator or the loop integrator output signal of the second loop integrator is below the minimum value, and the second time is another time at which the loop integrator output signal of the first loop integrator or the loop integrator output signal of the second loop integrator reaches the minimum value and wherein the CM-IDAC generates the feedback common current.
11. The differential amplifier circuit according to claim 1, further comprising another current digital-to-analog converter, IDAC configured to generate a current if, when the triangular reference signal reaches its maximum value, the loop integrator output signal of the first loop integrator or the loop integrator output signal of the second loop integrator is above the maximum value.
12. The differential amplifier circuit according to claim 1, wherein the DM-IDAC is configured to stop generating the first and second differential mode currents if, when the triangular reference signal reaches its maximum value, the loop integrator output signal of the first loop integrator or the loop integrator output signal of the second loop integrator is above the maximum value.
13. The differential amplifier circuit according to claim 1, further comprising at least one of a first, second, third and fourth extra comparators respectively configured to compare a maximum value of the triangular reference signal and the loop integrator output signal of the first loop integrator, a minimum value of the triangular reference signal and the loop integrator output signal of the first loop integrator, the maximum value and the loop integrator output signal of the second loop integrator, and the minimum value and the loop integrator output signal of the second loop integrator.
14. The differential amplifier circuit according to claim 1, where the comparator non-inverting input terminal of the first comparator is coupled to a first set of switches and the comparator non-inverting input terminal of the second comparator is coupled to a second set of switches wherein each of the first and second sets of switches comprises a first, second and third switch respectively coupled to the maximum value, the minimum value and the triangular reference signal.
15. The differential amplifier circuit according to claim 1, wherein the PWM signal is representative of a difference between the first and second staircase-like reference signals and the digital input signal.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0031] In the following, aspects of the invention will be elucidated by means of examples, with reference to the drawings in which:
[0032] FIG. 1A shows a schematic of a circuit comprising a load driven by the output stages of a differential amplifier according to the prior art.
[0033] FIGS. 1B and 1C show diagram representations of several signals of the differential amplifier of FIG. 1A.
[0034] FIG. 2A shows a schematic of a circuit of a differential amplifier.
[0035] FIGS. 2B, 2C and 2D show diagram representations of several signals of the differential amplifier of FIG. 2A.
[0036] FIGS. 3A and 3B shows a schematic of a circuit of a differential amplifier according to embodiments of the invention.
[0037] FIG. 4A shows a schematic of a circuit of the DM-IDAC of the differential amplifier of FIG. 3A according to an embodiment of the invention.
[0038] FIG. 4B shows diagram representations of several signals of the differential amplifier of FIG. 3A.
[0039] FIG. 5A shows a schematic of a circuit of the CM-IDAC of the differential amplifier of FIG. 3A according to an embodiment of the invention.
[0040] FIGS. 5B, 5C, 6, 7A-7B and 8A-8C, 9A-9B show diagram representations of several signals of the differential amplifier of FIG. 3A according to embodiments of the invention.
[0041] FIGS. 10 and 11 shows schematics of circuits of differential amplifiers according to embodiments of the invention.
DETAILED DESCRIPTION
[0042] Examples will now be described, by way of illustration only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts. In the drawings, like numerals designate like elements. Multiple instances of an element may each include separate letters appended to the reference number. For example, two instances of a particular element 112 may be labeled as 112a and 112b. The reference number may be used without an appended letter (e.g., 112) to generally refer to an unspecified instance or to all instances of that element, while the reference number will include an appended letter (e.g., 112a) to refer to a specific instance of the element.
[0043] FIG. 3A shows an amplifier circuit 300 according to an embodiment of the invention. The amplifier circuit 300 of FIG. 3A comprises a sigma delta modulator 302, a delta-PWM (DPWM) modulator 304, a differential-mode current-DAC (DM-IDAC) 306 and a common-mode current-DAC (CM-IDAC) 308. The sigma delta modulator 302 is configured to receive a digital input signal D.sub.IN. The digital input signal D.sub.IN may be an oversampled high resolution digital input signal comprising, for instance, 24 bits. The sigma delta modulator 302 is further configured to generate an output signal D which is a quantized version of the digital input signal D.sub.IN with less bits, for instance, with 8 bits, and wherein the resulting quantization noise has been shaped out of the audio bandwidth. The DPWM modulator 304 is configured to receive the output signal D.sub.M from the sigma delta modulator 302 and to generate a three level analog DPWM signal (that is, an analog DPWM signal that can have three different values or levels) which is then sent to the DM-IDAC 306 and to the CM-IDAC 308. The DM-IDAC 306 generates differential mode current I.sub.DMP at line 305 and differential mode current I.sub.DMN in line 307 as shown in FIG. 11. The CM-IDAC 308 generates common mode current I.sub.CM at both lines 309a and 309b as also shown in FIG. 11.
[0044] The differential amplifier circuit 300 of FIG. 3A also comprises loop integrators 320a and 320b. The loop integrator 320a comprises an integrator non-inverting input terminal 323a, an integrator inverting input terminal (or virtual ground node terminal) 321a and an integrator output terminal 325a. The loop integrator 320b comprises an integrator non-inverting input terminal 323b, an integrator inverting input terminal (or virtual ground node terminal) 321b and an integrator output terminal 325b. The integrator non-inverting input terminals 323a of the loop integrators 320a are configured to receive a common mode reference voltage V.sub.CM. The integrator inverting input terminal 321a of the loop integrator 320a is a virtual ground node terminal configured to receive a feedback signal from an output stage 340a, which generates an output voltage V.sub.OUTP, of the differential amplifier circuit via a feedback loop 390, a differential mode current I.sub.DMP from the DM-IDAC 306, and the common mode current I.sub.CM from the CM-IDAC 308. The CM-IDAC 308 can only sink current which means current I.sub.CM flows into CM-IDAC 308. The integrator inverting input terminal 321b of the loop integrator 320b is also a virtual ground node terminal configured to receive a feedback signal from another output stage 340b, which generates an output voltage V.sub.OUTN, of the differential amplifier circuit 300 via a feedback loop 390, the differential mode current I.sub.DMN from the DM-IDAC 306, and the common mode current I.sub.CM from the CM-IDAC 308.
[0045] The integrator output terminals 325 of the loop integrators 320 are configured to respectively provide loop integrator output signals V.sub.INTP and V.sub.INTN which are proportional to an integral of the signals received at the respective integrator inverting terminals 321 of the loop integrators 320.
[0046] The differential amplifier circuit 300 of FIG. 3A also comprises comparators 330a and 330b. The comparator 330a comprises a comparator non-inverting input terminal configured to receive V.sub.INTP, a comparator inverting input terminal 331a and a comparator output terminal. The comparator 330b comprises a comparator non-inverting input terminal configured to receive V.sub.INTN, a comparator inverting input terminal 331b and a comparator output terminal. The comparator inverting input terminals 331 of each of the comparators 330 are configured to receive a triangular reference signal V.sub.TRI that corresponds to the integral of a square wave carrier signal. The comparator non-inverting input terminal of the comparator 330a is connected to the integrator output terminal 325a of the loop integrator 320a and the comparator non-inverting input terminal of the comparator 330b is connected to the integrator output terminal 325b of the loop integrator 320b. The comparator output terminal of each of the comparators 330a and 330b is configured to provide a drive signal suitable for respectively driving the output stages 340a and 340b of the differential amplifier circuit 300. The Gate Drivers GDRV respectively translates the output signals of the comparators 330a and 330b to appropriate drive signals for the gates of the power FETs of the output stages 340a and 340b. This includes level shifting for the high side power FET and break-before-make timing to prevent that in each the output stages 340a and 340b both power FETs conduct simultaneously.
[0047] FIG. 3B shows a modification of the differential amplifier circuit of FIG. 3A. The differential amplifier circuit of FIG. 3B is identical to the differential amplifier circuit of FIG. 3A with the addition of another two loop integrators 360 and 370 and a sum module 380 after each of the loop integrators 320a and 320b. The cascade of the three loop integrators 320, 360 and 370 forms a third order loop filter in each half bridge. The sum module 380 in each half bridge generates a weighted sum of the outputs of each the three loop integrators. The weighing of integrator outputs is to achieve a stable loop transfer. As the gain of the configuration of the three loop integrators is equal to the multiplication of the gains of the three loop integrators, this higher order loop filter configuration increases the loop gain which results in lower distortion at the output of the differential amplifier. The gain of the integrators multiply and more integrators contribute to more gain. As shown in FIG. 3B, the output of the loop integrator 320 is connected to the inverting input of the loop integrator 320, to the sum module 380 and to the inverting input of the loop integrator 360, the output of the loop integrator 360 is connected to the inverting input of the loop integrator 360, to the sum module 380 and to the inverting input of the loop integrator 370, and the output of the loop integrator 370 is connected to the inverting input of the loop integrator 370 and to the sum module 380. The non-inverting input of each of the three loop integrators 320, 360 and 370 is connected to V.sub.CM. The rest of the description will refer to FIG. 3A but identically applies to FIG. 3B.
[0048] FIG. 4A shows a schematic of a circuit implementation of the DM-IDAC 306 according to an embodiment of the invention. The DM-IDAC 306 comprises four current sources 402a, 402b, 402c and 402d and four switches 406a, 406b, 406c and 406d. Each of the current sources 402 is arranged to generate a reference current I.sub.REF. The DM-IDAC 306 is arranged to receive four control signals srcp, snkp srcn, and snkn and generate, based on the received control signals, two current outputs I.sub.DMP and I.sub.DMN respectively at lines 305 and 307 that drive the virtual ground nodes of the feedback loop 390 as shown in FIG. 11. Each current I.sub.DMP(N) can be either +I.sub.REF, zero or I.sub.REF, depending on the control signals srcp, snkp srcn, and snkn that respectively control the switches 406a, 406b, 406c and 406d. The control signals srcp, snkp srcn, and snkn are generated by the DPWM modulator 304 as explained below.
[0049] The DPWM modulator 304 of FIG. 3A is configured to receive the output signal D.sub.M from the sigma delta modulator 302 and compare the output signal D.sub.M to two staircase-like reference signals REF.sub.P and REF.sub.N, wherein the two staircase-like reference signals REF.sub.P and REF.sub.N are staircase-like signals that are generated inside the DPWM modulator 304 using digital counters. FIG. 4B shows the two staircase-like reference signals REF.sub.P and REF.sub.N as a function of time. REF.sub.P and REF.sub.N are digital signals and each step of the staircase corresponds to one Least Significant Bit (LSB) and the high and low limits are plus/minus FS (Full Scale). The peaks in the reference signals are there to enforce a constant transition rate of the DPWM signal. U.S. Pat. No. 10,367,460 B2 provides examples of how to generate REF.sub.P and REF.sub.N, though any other suitable method could be used. In FIG. 4B, line 450 represents REFP, line 452 represents REFN, line 454 represents D.sub.M, line 456 represents the negative value of D.sub.M and the zero is the horizontal dashed line 490 in the middle. FIG. 4B shows in line 458 the generated current I.sub.DMP as a function of time and FIG. 4B shows in line 460 the generated current I.sub.DMN as a function of time. As it can be seen from FIG. 4B, if the output signal D.sub.M is higher than the staircase-like reference signal REF.sub.P, then the current output I.sub.DMP is positive and equal to I.sub.REF. Therefore the DM-IDAC 306 sources a positive current I.sub.REF into the virtual ground node of the feedback loop 390. A positive I.sub.DMP current causes the (average) output voltage V.sub.OUTP at the output terminal of the amplifier circuit to go down towards ground.
[0050] The current I.sub.DMP from the DM-IDAC 306 and the current I.sub.CM from the CM-IDAC 308 are sent towards the virtual ground node of the feedback loop 390 which is connected to the negative terminal of the loop integrator 320a. In a similar way, the current I.sub.DMN from the DM-IDAC 306 and the current I.sub.CM from the CM-IDAC 308 are sent towards the virtual ground node of the feedback loop 390 which is connected to the negative terminal of the loop integrator 320b. To maintain the virtual grounds, the currents provided at the virtual ground nodes need to be compensated by the feedback current flowing through the resistors R.sub.FBP and R.sub.FBN. So if a positive current flows towards the virtual ground then a negative current of equal magnitude needs to flow from the virtual ground towards the output terminal of the amplifier circuit. In this case, the output voltages V.sub.OUTP and V.sub.OUTP of the amplifier circuit need to be lower than the voltage on the corresponding virtual ground node. Hence a positive input current in the virtual ground node results in a negative output voltage at the output terminal of the amplifier circuit, and vice versa.
[0051] Going back to FIG. 4B, if D.sub.M is lower than REF.sub.N then I.sub.DMP sinks a negative current. In all other cases I.sub.DMP is zero. Output current I.sub.DMN is generated in a similar way but using the inverse signal D.sub.M. The peaks 480 on the reference signals REFP and REFN guarantee that D.sub.M crosses each reference signal REFP and REFN exactly once each period thereby resulting in a constant transition rate and eliminating inter-symbol interference (ISI). As can be seen in FIG. 4B, while D.sub.M is higher than REFP, IDMP stays positive, and if D.sub.M is lower than REF.sub.N, then I.sub.DMP is negative. For I.sub.DMN, the opposite occurs.
[0052] The averages of I.sub.DMP and I.sub.DMN are equal in magnitude but have opposite sign. Consequently, at the output V.sub.OUTP of the differential amplifier, the (average) value of V.sub.OUTP goes down, i.e. it's duty-cycle reduces, and the (average) value of V.sub.OUTN goes up, i.e. it's duty-cycle increases. The duty-cycle of V.sub.OUTP cannot go below zero. In this case output V.sub.OUTP stops switching between positive and negative values and this results in severe distortion since essentially one half of the amplifier circuit is now clipping and does not contribute further to the (differential) output signal.
[0053] This situation can be prevented by adding the common mode sink current I.sub.CM to both I.sub.DMP and I.sub.DMN. As shown in FIG. 3A, I.sub.CM is provided by CM-IDAC 308 to the inverting input of the loop integrators and I.sub.DMP and I.sub.DMN are respectively provided by DM-IDAC 306 to the inverting input of the loop integrators. The effect of this I.sub.CM is that the (average) common-mode value of V.sub.OUTP and V.sub.OUTN increases whereas the voltage difference between V.sub.OUTP and V.sub.OUTN remains unchanged and thus no distortion is caused.
[0054] FIG. 5A shows a schematic of a circuit implementation of the CM-IDAC 308 according to an embodiment of the invention. The CM-IDAC 308 comprises four current sources 502a, 502b, 502c and 502d and four switches 506a, 506b, 506c and 506d. Each of the current sources 502 is arranged to generate a current I.sub.REF/2. The CM-IDAC 308 is arranged to receive two control signals cmp and cmn and generate, based on the received control signals, two identical current outputs I.sub.CM at lines 309a and 309b (shown in FIG. 11) that respectively drive the virtual ground nodes and are thus respectively summed with the DM-IDAC output currents I.sub.DMP and I.sub.DMN. Each I.sub.CM current is the sum of two currents I.sub.CMP and I.sub.CMN. Each current I.sub.CM can be either 0, I.sub.REF/2 or I.sub.REF, depending on the control signals cmp and cmn that control the switches 506 and are generated by the DPWM modulator 304.
[0055] In the following, several embodiments for generating ICM will be described.
Feedforward Generation of ICM
[0056] According to this embodiment, the DPWM modulator 304 of FIG. 3A is configured to receive the output signal D from the sigma delta modulator 302 and compare the output signal D to a shifted version of the two staircase-like reference signals REF.sub.P and REF.sub.N. FIG. 5B shows the two staircase-like reference signals REF.sub.P and REF.sub.N and the shifted versions REFCMP and REFCMN as a function of time. The peaks 480 of the two staircase-like reference signals REF.sub.P and REF.sub.N are removed in the shifted versions REFCMP and REFCMN. In FIG. 5B, line 550 represents REF.sub.P, line 551 represents REFCMP which is the shifted version of REFP, line 552 represents REF.sub.N, line 553 represents REF.sub.CMN which is the shifted version of REF.sub.N, line 554 represents D.sub.M and line 556 represents the negative value of D.sub.M. FIG. 5B shows in line 558 the current I.sub.CMN, and FIG. 5B shows in line 560 the current I.sub.CMP as a function of time. And FIG. 5B shows in line 562 the generated current I.sub.CM as a function of time.
[0057] As it can be seen from FIG. 5B, I.sub.CM can be generated with feedforward by comparing compare D.sub.M to the shifted versions of the references REF.sub.P and REF.sub.N. REF.sub.CMP is shifted up with respect to REF.sub.P and REF.sub.CMN is shifted down with respect to REF.sub.N by the same offset called N.sub.SKIPP.
[0058] If D.sub.M is higher than REF.sub.CMP or lower than REF.sub.CMN then I.sub.CMP sinks a current I.sub.REF/2, otherwise I.sub.CMP is zero. If the inverted signal D.sub.M is higher than REF.sub.CMP or lower than REF.sub.CMN then I.sub.CMN sinks a current I.sub.REF/2, otherwise I.sub.CMN is zero. When both I.sub.CMP and I.sub.CMN are sinking current their values are summed together yielding I.sub.REF.
[0059] Because of the offset N.sub.SKIP that has been applied to the reference signals REF.sub.P and REF.sub.N to obtain the shifted versions REF.sub.CMP and REF.sub.CMN, there is a range of values for D.sub.M where I.sub.CMP, and I.sub.CMN are zero. Line 570 shows an example of a specific value of D.sub.M for which I.sub.CMP and I.sub.CMN are zero. This means that for small values of D.sub.IN (D.sub.M), that is values of D.sub.IN (D.sub.M) between zero and the minimum value of REF.sub.CMP, no common-mode currents I.sub.CM are added and therefore also no noise is added. Ideally, the CM-IDAC 308 is arranged to generate two identical currents I.sub.CM. However, in a real implementation there will also be noise in the current sources 502 that is uncorrelated so the noise is not strictly common-mode and therefore the noise has a differential-mode component. This differential-mode noise component adds to the differential noise at the output terminals V.sub.OUTP and V.sub.OUTN. However, if the common-mode currents I.sub.CM are zero no additional noise will be produced.
[0060] So for small values of the input signal D.sub.IN (D.sub.M), it is advantageous that I.sub.CM is zero to improve the differential noise. For large values of the input signal D.sub.IN (D.sub.M), it is advantageous to generate non zero I.sub.CM to prevent distortion as the added noise will be masked by the value of the input signal D.sub.IN thereby becoming inaudible.
[0061] The effect of the feedforward common-mode current I.sub.CM is that it fixes the lowest level of the average value of either V.sub.OUTP or V.sub.OUTN depending on the value of N.sub.SKIP. FIG. 5C shows an example of V.sub.LPFP and V.sub.LPFN, which are the respective (low-pass filtered) single-ended outputs V.sub.OUTP and V.sub.OUTN as a function of time for different values of N.sub.SKIP. At zero value of the input signal D.sub.IN both V.sub.LPFN and V.sub.LPFP equal V.sub.CM. For positive values of the input signal D.sub.IN, V.sub.LPFP increases with respect to V.sub.CM and V.sub.LPFN decreases with respect to V.sub.CM.
[0062] As shown in FIG. 5C, when N.sub.SKIP equals zero, neither V.sub.LPFP nor V.sub.LPFN respectively represented as lines 570a and 570b will go below the common mode reference voltage V.sub.CM. In this case the common mode feedforward current I.sub.CM generated by CM-IDAC 308 exactly matches the rectified version of the currents I.sub.DMP and I.sub.DMN generated by the DM-IDAC 306. This is because, if N.sub.SKIP equals zero, the shifted versions REF.sub.CMP and REF.sub.CMN fall on top of the reference signals REF.sub.P and REF.sub.N used to generate the I.sub.DMP and I.sub.DMN in the DM-IDAC 306. In this case the common-mode part of V.sub.LPFN and V.sub.LPFP becomes a rectified version of the differential-mode part of V.sub.LPFN and V.sub.LPFP. In each bridge-halve this means that negative signal excursions are cancelled, and positive excursions are doubled.
[0063] As an example, with N.sub.SKIP having a value equivalent to 15, the minimum level of V.sub.LPFP and V.sub.LPFN respectively represented in FIG. 5C by 572a and 572b hovers just above ground. In this case the feedback loop 390 maintains stable regulation but both output stages 340 keep switching. N.sub.SKIP is a digital value which units are LSB (Least Significant Bit). N.sub.SKIP having a value equivalent to 15 used in this example is related to the resolution of D.sub.M , and with D.sub.M being a 8-bit signal, its resolution range is 127 to +127. If D.sub.M would be a 9-bit signal, then its range would double and we would have to double N.sub.SKIP to get the same behaviour. The output signals V.sub.OUTP and V.sub.OUTN of both output stages or bridge-halves 340 are PWM signals that can only switch between ground GND and supply V.sub.DD with a fixed frequency. Only the respective duty-cycle D.sub.P and D.sub.N of the output signals V.sub.OUTP and V.sub.OUTN is variable. The average value of V.sub.OUTP equals D.sub.P*V.sub.DD and the average value of V.sub.OUTN equals D.sub.N*V.sub.DD.
[0064] The output stages or bridge-halves 340 stop switching only if D.sub.P or D.sub.N is zero per cent, that is, if V.sub.OUTP or V.sub.OUTN is GND; or if D.sub.P or D.sub.N is 100 percent, that is, if V.sub.OUTP or V.sub.OUTN is V.sub.DD. So, if the average value of V.sub.OUTP or V.sub.OUTN is between GND and V.sub.DD, the respective duty-cycle, D.sub.P or D.sub.N, is between zero and 100 percent and thus the corresponding output is switching.
[0065] The feedback loop 390 maintains stable operation because the virtual ground nodes are maintained as the current pushed into the virtual ground nodes is matched by the feedback currents.
[0066] If, for example, N.sub.SKIP equals 30, both V.sub.LPFP and V.sub.LPFN respectively represented in FIG. 5C by 572a and 572b are clipped to ground. In this case the corresponding bridge-half 340 stops switching and the differential mode signal V.sub.LPFPV.sub.LPFN gets distorted. If one bridge-half stops switching the feedback loop 390 of that bridge-half cannot maintain regulation as more current is pushed into the virtual ground that can be compensated by the feedback loop 390 because the output of the amplifier circuit cannot go lower than GND. If one bridge-half cannot maintain regulation this causes an error in the differential-mode signal which is distortion
[0067] An NSKIP value exists that is exactly on the boundary where the feedback loop 390 is still in regulation while one of the bridge halves stops switching. However, this NSKIP value is very sensitive to small variations in the amplifier circuit caused by process, supply and temperature changes.
Feedback Generation of ICM
[0068] FIG. 6 is identical to FIG. 2B and schematically shows outputs V.sub.INTP and V.sub.INTN as lines 262 and 264, the triangular reference signal V.sub.TRI as line 248, and the output node signals V.sub.OUTP and V.sub.OUTN as lines 242 and 244 in the situation when V.sub.OUTN has stopped switching and the loop integrator output signal V.sub.INTN at the output terminal 325b of the loop integrator 320b is just over the edge of regulation. As can be seen in FIG. 6, V.sub.INTN is slowly diverging away from the range of the triangular reference signal V.sub.TRI. This situation can be detected by identifying a first time 602 at which the value of the loop integrator output signal V.sub.INTN is below the lowest value V.sub.TRIMIN of V.sub.TRI. V.sub.TRIMIN is represented as line 748 in FIG. 7B. A feedback common current I.sub.CMFB having a value of I.sub.REF and represented by line 700 in FIG. 7B will be generated and send to the virtual ground nodes of the feedback loops 390 at the identified first time 602. The feedback common mode current I.sub.CMFB will correct the divergence of V.sub.INTN. Both V.sub.INTN and V.sub.INTP will increase such that V.sub.INTN moves up towards V.sub.TRIMIN as respectively shown by lines 764 and 762 in FIG. 7B. At a second time 702 when V.sub.INTN reaches V.sub.TRIMIN, the generation of the feedback common current I.sub.CMFB will stop. After that second time 702, V.sub.INTN will diverge down again and, at the next time that V.sub.TRI reaches V.sub.TRIMIN, a new current pulse I.sub.CMFB will be generated restarting the process.
[0069] Because the current sink pulses of I.sub.CMFB are common mode, not only V.sub.INTN but also V.sub.INTP is affected as can be seen in FIG. 7A. The duty-cycle of the output voltage V.sub.OUTP increases and makes up for the part that is now missing from V.sub.OUTN as shown by line 742 and the distortion that would otherwise have been caused by V.sub.OUTN clipping to ground is corrected.
Combining Feedback and Feedforward Generation of ICM
[0070] In an embodiment of the invention, the common mode feedback current I.sub.CMFB could be generated by the CM-IDAC 308 as shown in FIG. 5A that also generates the common mode feedforward common currents I.sub.DMP or I.sub.DMN. The common mode feedback current I.sub.CMFB need to be generated when V.sub.TRI reaches V.sub.TRIMIN. As shown in FIG. 5B, in the peaks REF.sub.P and REF.sub.N only one of the common mode feedforward common currents I.sub.DMP or I.sub.DMN needs to be generated, which means that the other current output of the CM-IDAC 308 is available to generate the common mode feedback current I.sub.CMFB. Therefore, when the CM-IDAC 308 is not generating the common mode feedforward common current I.sub.DMP at line 305, the CM-IDAC 308 can generate the common mode feedback current I.sub.CMFB at that line 305, and when the CM-IDAC 308 is not generating the common mode feedforward common current I.sub.DMN at line 307, the CM-IDAC 308 can generate the common mode feedback current I.sub.CMFB at that line 30.
Supply Clipping Control
[0071] Generating both the common mode feedforward currents I.sub.CMP or I.sub.CMN and the common mode feedback current I.sub.CMFB allows that V.sub.OUTN and V.sub.OUTP clip to ground while maintaining low distortion. In differential amplifiers wherein V.sub.OUTN and V.sub.OUTP working at low duty cycle pulse width modulation, the common mode correction becomes active at relatively low input signal levels. When the input signal level is increased further, the duty-cycle of the output signal V.sub.OUTN/P that is still switching increases until it reaches 100%.
[0072] In that case integrator output V.sub.INTN or V.sub.INTP of the differential amplifier will clip against the supply rail V.sub.DD and a similar situation appears as when V.sub.INTN or V.sub.INTP are clipping to ground but now when the reference V.sub.TRI reaches its highest value V.sub.TRIMAX. FIG. 8A shows V.sub.INTN, V.sub.INTP, V.sub.OUTN, V.sub.OUTP, V.sub.TRI and V.sub.TRIMIN when a large (negative) input signal is applied to the differential amplifier. In this case, the output V.sub.OUTN is already clipping to ground and the common mode correction as explained above prevents V.sub.INTN from diverging. When the input signal increases further, the duty-cycle of V.sub.OUTP increases as can be seen in FIG. 8B. Compared V.sub.INTP in FIG. 8A and FIG. 8B, when the input signal increases further, V.sub.INTP also increases towards the maximum value V.sub.TRIMAX of V.sub.TRI. When the input signal is increased even more the duty-cycle of V.sub.OUTP becomes 100%, V.sub.OUTP stops switching and V.sub.INTP grows above the range of V.sub.TRI as shown in FIG. 8C.
[0073] In an alternative embodiment, the DM-IDAC 306 can stop generating I.sub.DMP or I.sub.DMN at certain times to prevent V.sub.INTP from diverging as in FIG. 8C. In this embodiment and as shown in FIGS. 9A and 9B, if at a third time 904 when V.sub.TRI reaches the maximum value V.sub.TRIMAX, the value of V.sub.INTP is higher than V.sub.TRIMAX, then DM-IDAC 306 will stop generating the current I.sub.DMP until a fourth time 906 at which the value of V.sub.INTP is below V.sub.TRIMAX again. The same mechanism applies to the generation of I.sub.DMN for large positive input signals.
[0074] This clipping control arrangement does not prevent distortion: the output cannot be driven beyond the supply rails, that is, the output is clipping to the supply value V.sub.DD, and thus distortion is inevitable. However, preventing divergence of the loop integrators results in a smooth and immediate recovery from clipping as soon as the input signal is reduced again. This prevents audible artifacts related to so-called sticking and settling responses.
[0075] The Implementation of the complete common-mode feedforward/feedback and clipping control requires the addition of four new comparators to the differential amplifier 300 shown in FIG. 3A to compare the outputs V.sub.INTP/N to the reference triangle boundaries V.sub.TRIMIN and V.sub.TRIMAX and a couple of simple finite-state machines that combine the comparator outputs with the three level analog DPWM signal from the DPWM modulator 304 to drive the DM-IDAC 306 and the CM-IDAC 308.
[0076] In an embodiment, the comparison of V.sub.INTP and V.sub.INTN to the upper and lower boundaries V.sub.TRIMIN and V.sub.TRIMAX of V.sub.TRI can be implemented by adding four additional comparators 1002a, 1002b, 1002c and 1002d on top of the two comparators 330 as shown in FIG. 10.
[0077] However, the same can also be achieved with the existing comparators 330 by multiplexing the inverting input terminals 331 of the comparators 330 between V.sub.TRI, V.sub.TRIMIN and V.sub.TRIMAX as shown in FIG. 11. FIG. 11 is similar to FIG. 3A with the addition of the block 1100 comprising a first set of switches and a second set of switches wherein the first ser of switches is connected to the comparator inverting input terminal 331a of the first comparator 330a and the second set of switches is connected to the comparator inverting input terminal 331b of the second comparator 330b. Each of the first and second sets of switches of block 1100 of FIG. 11 comprises a first, second and third switch respectively coupled to the maximum value V.sub.TRIMAX, the minimum value V.sub.TRIMIN and the triangular reference signal V.sub.TRI such that the inverting input 331 can switch between the three values and the comparator 330 can provide a comparison with each of the three values when needed.
[0078] This provides a hardware efficient implementation and has the additional benefit that all comparisons have the same offset. Switching between different signals at the inverting input terminals 331 can be done with minimal disturbance at the peaks of V.sub.TRI where the value is equal to either V.sub.TRIMIN or V.sub.TRIMAX.
[0079] The present invention may be exemplified or embodied in other specific forms without departing from its essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive to the inventive concept. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. It will be apparent to the person skilled in the art that alternative and equivalent examples of the invention can be conceived and reduced to practice. In addition, many modifications may be made to adapt a particular configuration or material to the teachings of the invention without departing from the essential scope thereof. All modifications which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
