SIC MOSFET STRUCTURES WITH ASYMMETRIC TRENCH OXIDE

Abstract

We herein describe a silicon-carbide (SiC) based power semiconductor device comprising: a drain region of a first conductivity type; a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region; a body region of a second conductivity type, opposite to the first conductivity type, disposed over the drift region; a contact region of the first conductivity type, disposed within the body region; a source Ohmic contact being disposed on the source region; and one or more trench gate regions being in contact with the source region, the body region and the drift region. Each of the one or more trench gate regions are configured to form a channel region in the body region between the source region and the drift region. At least one trench gate region comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface. The insulation layer comprises different thicknesses such that the insulation layer is thinner at a portion of one of the vertical sidewalls including the channel region than at the other vertical side wall and the trench bottom.

Claims

1. A silicon-carbide (SiC) based power semiconductor device comprising: a drain region of a first conductivity type; a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region; a body region of a second conductivity type, opposite to the first conductivity type, disposed over the drift region; a contact region of the first conductivity type, disposed within the body region; a source Ohmic contact being disposed on the source region; and one or more trench gate regions being in contact with the source region, the body region and the drift region, wherein each of the one or more trench gate regions are configured to form a channel region in the body region between the source region and the drift region, wherein at least one trench gate region comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer comprises different thicknesses such that the insulation layer is thinner at a portion of one of the vertical sidewalls including the channel region than at the other vertical side wall and the trench bottom.

2. The silicon-carbide (SiC) based semiconductor device according to claim 1, wherein, in the trench gate region, the insulation layer along one vertical side wall comprises different thicknesses and the insulation layer along another vertical side wall comprises a constant thickness.

3. The silicon-carbide (SiC) based semiconductor device according to claim 1, wherein each vertical side wall of the trench gate comprises an upper portion and a lower portion.

4. The silicon-carbide (SiC) based semiconductor device according to claim 3, wherein a thickness of the insulation layer along the lower portion is greater than a thickness of the insulation layer along the upper portion of one vertical side wall, and wherein, for another vertical side wall, the thickness of the insulation layer along the lower portion and the upper portion is the same.

5. The silicon-carbide (SiC) based semiconductor device according to claim 3, wherein the thickness of the insulation layer along the bottom surface of the trench gate is the same as the thickness of the insulation layer along the lower portion of both vertical side walls; wherein the channel region is formed along the insulation layer along the upper portion.

6. (canceled)

7. The silicon-carbide (SiC) based semiconductor device according to claim 3, wherein the vertical length of the lower portion is greater than the vertical length of the upper portion; or wherein the ratio of the vertical length of the lower portion and the vertical length of the upper portion is equal to or greater than 1.

8. (canceled)

9. The silicon-carbide (SiC) based semiconductor device according to claim 1, wherein the device comprises a first gate trench region and a second gate trench region, and wherein each of the first trench gate region and the second trench gate region have a first sidewall and a second sidewall and wherein the second sidewall of the first trench is adjacent to the first sidewall of the second trench, and wherein the insulation layer along the second sidewall of the first trench and the first sidewall of the second trench comprises a constant thickness, and wherein the insulation layer along the first sidewall of the first trench and the second sidewall of the second trench comprises different thicknesses.

10. The silicon-carbide (SiC) based semiconductor device according to claim 1, wherein the device comprises at least two gate trench regions, and wherein the device comprises a contact region of a second conductivity type located within the body region and between two gate trench regions and having a higher doping concentration than the body region.

11. The silicon-carbide (SiC) based semiconductor device according to claim 10, wherein a first portion of the body region between two gate trench regions extends to a bottom surface of the two trench gate regions.

12. The silicon-carbide (SiC) based semiconductor device according to claim 11, wherein the first portion of the body region extends lower in the semiconductor device than a second portion of the body region.

13. The silicon-carbide (SiC) based semiconductor device according to claim 12, wherein the channel region is located in the second portion of the body region.

14. The silicon-carbide (SiC) based semiconductor device of claim 1, wherein the device comprises a Schottky contact located between adjacent trench gate regions of the one or more trench gate regions.

15. The silicon-carbide (SiC) based semiconductor device according to claim 14, wherein the device comprises at least two gate trench regions and wherein the Schottky contact is located between the at least two trench gate regions.

16. The silicon-carbide (SiC) based semiconductor device according to claim 1, wherein the device is a vertical metal oxide semiconductor field effect transistor (MOSFET).

17. A method of manufacturing a silicon-carbide (SiC) based power semiconductor device comprising one or more gate trench regions with an insulation layer, wherein the one or more trench gate regions with an insulation layer are manufactured using the steps of: performing an etching process to form the one or more trenches; forming a thick insulation layer on a lower surface and sidewalls of the one or more trenches; depositing a hydrophilic layer over the thick insulation layer; depositing a photoresist material in the one or more trenches, wherein depositing a photoresist material comprises exposing the hydrophilic layer on an upper region of a first side of the one or more trenches; performing a wet etch process to etch the insulation layer on the sidewall of the first side of the one or more trenches to a predetermined distance below a surface of the photoresist material; removing the photoresist material; removing the hydrophilic layer; growing a thin insulation layer on the sidewall of the first side of the one or more trenches, wherein the thin insulation layer is thinner than the thick insulation layer.

18. A method according to claim 17, wherein the method further comprises depositing a filling material after growing the thin insulation layer.

19. A method according to claim 17, wherein the hydrophilic layer comprises nitride; or wherein forming a thick insulation layer comprises depositing a thick oxide layer.

20. (canceled)

21. A method according to claim 17, wherein the thick insulation layer has a thickness between 3000 Å and 5000 Å; or wherein the thin insulation layer has a thickness between 500 Å to 2000 Å.

22. (canceled)

23. A method according to claim 17, wherein before performing an etching process, the method further comprises: forming a silicon carbide layer; forming a body region of a second conductivity type over the silicon carbide layer; and depositing a thick insulation layer over the body region.

24. A method according claim 17, wherein the method comprises manufacturing at least two gate trench regions each with an insulation layer, wherein a first gate trench region is separated from a second trench gate region; and wherein each of the first trench gate region and the second trench gate region have a first side and a second side and wherein the second side of the first trench is adjacent to the first side of the second trench; and wherein depositing a photoresist material comprises exposing the hydrophilic layer on the first side of the first trench gate region and the second side of the second trench gate region.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0057] Some preferred embodiments of the invention will now be described, by way of example only and with reference to the accompanying drawings, in which:

[0058] FIG. 1 illustrates a SiC based power MOSFET according to an embodiment;

[0059] FIG. 2 illustrates an alternative SiC based power MOSFET according to a further embodiment;

[0060] FIG. 3 shows performance of the power MOSFETs shown in FIG. 1 and FIG. 2;

[0061] FIG. 4 illustrates an alternative SiC based power MOSFET according to a further embodiment; and

[0062] FIGS. 5(a) to 5(j) illustrate steps of a method of manufacturing a SiC based power MOSFET according to a further embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0063] FIG. 1 is a schematic cross-sectional view of a silicon carbide (SiC) based semiconductor device 100 with according to one embodiment. In this device, SiC based means that every region in the device apart from the metal (contacts), insulation, trench gate, and insulation (oxide) layers are formed from SiC. In this embodiment, the device 100 is an n-type voltage sustaining region or n-base (or a drift region) 106 over a drain 104 and a drain metal contact 102.

[0064] The device 100 includes two gate trenches 114 extending down into the n-base 106 from the surface of an n+ contact region 110. The device acts a MOSFET with a channel formed between the n+ contact region 110 and the drift region 106 in an on-state by application of a positive voltage. Within the n-base 106 and adjacent to the gate trench regions 114, there is provided a p-well or p-body (or a body region) 108. Within the p-base or p-body 108, the n+contact region 110 of the source is formed.

[0065] In the embodiment of FIG. 1, two gate trenches 114 are formed, which are laterally spaced from each other. Each gate trench 114 includes vertical sidewalls and a bottom surface between the vertical sidewalls. The gate trenches 114 can be filled trenches with an oxide region on the side walls and a gate metal electrode within the trench. The trenches may be filled with a conducting material such as metal or doped polysilicon.

[0066] An emitter p+contact layer (or the second contact region) 116 is formed above the A-base (p-well layer) 108. The p+ contact layer 116 is located in a region below the n+ contact region 110.

[0067] The gate trenches 114 have an oxide layer having two thicknesses. One portion of the oxide layer has a greater thickness compared to another portion of the same oxide layer. The oxide layer with the greater thickness is referred to as a thick oxide layer 120 and the oxide layer of the same trench having a smaller thickness is referred to as a thin oxide layer 118. The same definitions apply to all the embodiments of the specification.

[0068] In this embodiment, the gate trenches 114 have two side walls. The conduction channel is formed along only one side wall and no conduction channel is formed along another side wall. The thin oxide layer 118 is generally located along the conduction channel region, which is located along the upper portion of one vertical side wall of each trench. The gate trenches 114 have a thick oxide layer or portion 120 on vertical sidewall regions where conduction channels or accumulation layers are not formed. The thick oxide layer 120 is generally located along the bottom surface, and the remaining vertical sidewall regions of the gate trenches 114. The gate trenches 114 have a thick oxide layer 120 (or an oxide layer having a constant thickness) along a complete vertical sidewall of the trench. The asymmetric oxide layer reduces the gate to drain capacitance (Cgd) and improves the switching speed. It also improves the BVdss RonA trade-off due to reduced cell dimension. Reduced cell dimensions leads to a greater number of cells in the chip, and hence the output current of the chip increases. By reducing the cell dimension the trenches will be closely spaced which results in improved shielding of the regions, which previously were subjected to high electric field, and therefore increases overall voltage blocking capability of the device.

[0069] The thick oxide layers 120 are formed by the local oxidation of silicon (LOCOS) technique. Generally, a thin oxide layer in the trench bottom can suffer from premature breakdown under high electric fields. The feature of trenches with a thick bottom oxide 120 improves immunity to high electric field stress, and allows a higher voltage to be sustained.

[0070] The gate trenches 114 may be formed of (or may have) an upper portion and a lower portion. The upper portion extends for a length y1 downwards from the surface of the trench. The lower portion extends for a length y2 upwards from the bottom of the trench. On trench sidewalls without a thick oxide layer on the upper portion, the transition from the thin oxide 118 to the thick oxide 120 on the vertical sidewalls of the trenches occurs at the boundary between the upper and lower portions. The transition occurs at a distance y1 from the top of the active trenches. The distance from the bottom of the active trenches to the transition from the thin oxide 118 to the thick oxide 120 is given by y2, in which generally y1/y2≥1 and adjusting this ratio alters the Cgd. In this way, y1 and y2 can be adjusted to tune the device performance. The values of y1 and y2 may vary for different trenches within the same device. y2 may be greater than 0.5 μm. y1 can be least as big as depth of the p-well 108.

[0071] The thick oxide layer 120 on the bottom surface of the gate trenches 114 increases the maximum voltage that can be sustained within the device, therefore improving reliability of the device 100. Having one trench sidewall with constant thickness 120 and one trench sidewall with thin oxide 118 in the conduction channel and thick oxide 120 on a lower portion reduces the cell dimension and there improves BVdss RonA trade-off.

[0072] An insulator, such as oxide, layer 122 is formed over the gate trench regions of the device not connected to the source metal contact 112.

[0073] A p+ implant 124 is formed between two adjacent gate trenches 114, in the mesa region between sidewalls of adjacent trenches having thick oxide. The asymmetric trench oxide means that a deep p+ implant may not be required.

[0074] FIG. 2 illustrates a schematic cross-sectional view of an alternative SiC based semiconductor device according to a further embodiment. In this embodiment, the p-body region 108 extends to the depth of the bottom of the gate trenches 114 of the device 100. This improves robustness of the device and scalability to higher voltages.

[0075] FIG. 3 shows reverse conducting bias against reverse leakage for a semiconductor device with a shallow p-well 326 and a deep p-well 328. This shows that by having a deep p-well, the semiconductor device is able to sustain higher blocking voltage. The depth of the p-well can be altered to increase the chip rating e.g. from 1200V to 1700V, and up to 3300V.

[0076] FIG. 4 illustrates a schematic cross-sectional view of an alternative SiC based semiconductor device according to a further embodiment. In this embodiment, an integrated Schottky contact 430 is formed between the two gate trenches 114, and extends from the source metal contact 112 to the n-drift region 106. The integrated Schottky contact improves reliability. It also improves area efficiency of the device, ad reduces system cost as there is no requirement for Freewheeling diode (FWD). As a SIC Scottky diode is integrated in the area between the thick oxide trench region which is not used for MOSFET conduction, the device makes more efficient use of the SiC material to include two power devices in the same area, rather than just one. While building a power module a transistor is always accompanied by a complimentary Freewheeling diode (FWD). By including an integrated Schottky diode in the transistor (in this example, SiC MOSFET), a FWD is not required. This reduces the cost of the semiconductor modules.

[0077] FIGS. 5(a) to 5(j) illustrate steps within a method of manufacturing a SiC based power MOSFET according to a further embodiment.

[0078] FIG. 5(a) illustrates the first step of manufacturing two trenches with asymmetric insulation layers, which is as follows: [0079] (a) Step 1 [0080] A p-base layer is implanted and a thin oxide layer is deposited on a silicon carbide (SiC) substrate. The thin oxide layer has thickness of approximately 250 Å to 1800 Å.

[0081] FIG. 5(b) illustrates the second step of manufacturing two trenches, which is as follows: [0082] (b) Step 2 [0083] Photolithography and then a dry etch step using plasma source to form trenches to desired depth z in the SiC substrate. In this embodiment, the desired depth z of the trenches is 1.0 μm to 6 μm.

[0084] FIG. 5(c) illustrates the third step of manufacturing two trenches, which is as follows: [0085] (c) Step 3 [0086] A thick oxide layer is thermally grown or deposited on the sidewalls and bottom surface of the trenches. The thick oxide layer may be deposited using TEOS. The thick oxide layer has a thickness of approximately 3000 Å to 4000 Å.

[0087] FIG. 5(d) illustrates the fourth step of manufacturing two trenches, which is as follows: [0088] (d) Step 4 [0089] A hydrophilic layer such as nitride is deposited over the oxide layer. The nitride layer has a thickness of approximately 500 Å to 2500 Å.

[0090] FIG. 5(e) illustrates the fifth step of manufacturing two trenches, which is as follows: [0091] (e) Step 5 [0092] A mask is applied over the two trenches. [0093] The mask is deposited such that the hydrophilic layer is exposed on a first side of a first trench and a second side of the second trench, where the first side and the second side are opposite sides. The mask covers the mesa region between the trenches the other sides of the trenches. [0094] The first side of the first trench and the second side of the second trench (the sides where the hydrophilic layer is exposed) are the sides of the trenches that will be manufactured to have a thin oxide layer, whilst the sides of each trench that will be manufactured to have thick oxide remain covered by the photoresist. [0095] The thickness of the photoresist is 1.0 μm to 1.5 μm for a 1.5 μm trench. [0096] An etch process is performed on the exposed hydrophilic layer. The etch process can be a wet or dry etch, and stops on the thick oxide layer to expose a region of the oxide layer where the hydrophilic layer was exposed. [0097] In embodiments where the hydrophilic layer is nitride, the etch process may be done in plasma ambient using CF4/HBr chemistry.

[0098] FIG. 5(f) illustrates the sixth step of manufacturing two trenches, which is as follows: [0099] (f) Step 6 [0100] The whole wafer is immersed in a BOE (buffered oxide etch) such as 7:1 HF. The buffered oxide etchant etches the exposed region of the oxide layer on the trench sidewalls extending down from the surface of the exposed region to a desired depth Y below the surface of the trench. [0101] The hydrophilic layer creates a capillary action so that the etchant etches the oxide layer along the narrow channel between the hydrophilic layer itself and the silicon carbide. [0102] The presence of the hydrophilic layer allows control of the etch depth and uniformity of the etch process. The hydrophilic layer reduces defects formed during the etch process.

[0103] FIG. 5(g) illustrates the seventh step of manufacturing two trenches, which is as follows: [0104] (g) Step 7 [0105] The photoresist is stripped (removed) using any suitable wet or dry chemistry. [0106] The hydrophilic layer is stripped (removed) using any suitable wet or dry chemistry, i.e. any suitable mixture of a certain number of reactive gases. This leaves the trenches having only oxide on regions not exposed in Step 5.

[0107] FIG. 5(h) illustrates the eighth step of manufacturing two trenches, which is as follows: [0108] (h) Step 8 [0109] A thin oxide layer is grown on the exposed silicon in a furnace step at 900° C. to 1100° C. The thin oxide layer grows on the side of each trench in which the hydrophilic layer was exposed in Step 5. [0110] The thin oxide layer has thickness of approximately 250 Å to 1800 Å.

[0111] FIG. 5(i) illustrates the ninth step of manufacturing two trenches, which is as follows: [0112] (i) Step 9 [0113] Doped polysilicon is deposited to fill the trenches. The polysilicon is planarised by etching the top of the polysilicon to level off the surface of the polysilicon.

[0114] FIG. 5(j) illustrates the tenth step of manufacturing two trenches, which is as follows: [0115] (j) Step 10 [0116] An n+ source region is implanted. The n+ source region can be, for example, phosphorous, arsenic, or similar material [0117] A dielectric layer is formed over the trench gate regions. The dielectric layer can be, for example, oxide or nitride [0118] A source metal contact is formed over the device and in contact with the source region. The source metal material can be, for example, Al, Ni, or Ti.

[0119] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘overlap’, ‘under’, ‘lateral’, etc. are made with reference to conceptual illustrations of an apparatus, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.

[0120] It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with embodiments of the present invention.

[0121] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

LIST OF REFERENCE NUMERALS USED

[0122] 100—MOSFET device

[0123] 102—drain contact metal

[0124] 104—drain region

[0125] 106—drift region

[0126] 108—body region

[0127] 110—source region

[0128] 112—source contact

[0129] 114—gate trench region

[0130] 116—p+ region

[0131] 118—thin insulation layer

[0132] 120—thick insulation layer

[0133] 122—insulator

[0134] 124—p+ implant

[0135] 326—shallow p−

[0136] 328—deep p−

[0137] 430—Schottky contact

[0138] 508—p-body region

[0139] 510—source region

[0140] 512—Source metal contact

[0141] 514—gate trench

[0142] 518—thin oxide layer

[0143] 520—thick oxide layer

[0144] 522—insulation layer

[0145] 532—SiC substrate

[0146] 534—oxide layer

[0147] 536—hydrophilic layer

[0148] 538—doped polysilicon