High-efficiency silicon heterojunction solar cell and manufacturing method thereof

Abstract

The present disclosure discloses a high-efficiency silicon heterojunction (HJT) solar cell and a manufacturing method thereof, and belongs to the technical field of solar cells. In the solar cell of the present disclosure, an N-type crystal silicon wafer is successively provided with a thin SiO.sub.2 layer, a hydrogenated amorphous carbon silicon oxide film layer, a carbon doped SiO.sub.2 layer, an amorphous silicon doped N-type layer, a TCO conductive layer, and an electrode on a front surface; and successively provided with a thin SiO.sub.2 layer, a hydrogenated amorphous carbon silicon oxide film layer, a carbon doped SiO.sub.2 layer, an amorphous silicon doped P-type layer, a TCO conductive layer, and an electrode on a rear surface. The amorphous silicon doped P-type layer includes a lightly boron doped amorphous silicon layer and a heavily boron doped amorphous silicon layer.

Claims

1. A high-efficiency silicon heterojunction (HJT) solar cell, comprising: an N-type crystal silicon wafer, a first thin SiO.sub.2 layer, a first hydrogenated amorphous carbon silicon oxide film layer, a first carbon doped SiO.sub.2 layer, an amorphous silicon doped N-type layer, a first TCO conductive layer, and a front electrode being successively arranged on a front surface of the N-type crystal silicon wafer; and a second thin SiO.sub.2 layer, a second hydrogenated amorphous carbon silicon oxide film layer, a second carbon doped SiO.sub.2 layer, an amorphous silicon doped P-type layer, a second TCO conductive layer, and rear electrode being successively arranged on a rear surface of the N-type crystal silicon wafer; wherein the amorphous silicon doped P-type layer has a thickness in a range from 10 nm to 30 nm; the amorphous silicon doped P-type layer comprises a lightly boron doped amorphous silicon layer and a heavily boron doped amorphous silicon layer, the lightly boron doped amorphous silicon layer is close to the second carbon doped SiO.sub.2 layer, and the heavily boron doped amorphous silicon layer is close to the second TCO conductive layer.

2. The high-efficiency silicon HJT solar cell according to claim 1, wherein each of the first thin SiO.sub.2 layer and the second thin SiO.sub.2 layer has a thickness in a range from 1 nm to 3 nm.

3. The high-efficiency silicon HJT solar cell according to claim 1, wherein each of the first hydrogenated amorphous carbon silicon oxide film layer and the second hydrogenated amorphous carbon silicon oxide film layer has a thickness in a range from 2 nm to 10 nm and an energy gap in a range from 1.7 eV to 2.3 eV.

4. The high-efficiency silicon HJT solar cell according to claim 3, wherein each of the first hydrogenated amorphous carbon silicon oxide film layer and the second hydrogenated amorphous carbon silicon oxide film layer is non-stoichiometric and has a chemical formula expressed as a-SiOxCy:H, with a non-stoichiometric ratio x changing in a range from 0.05 to 0.95 and a non-stoichiometric ratio y changing in a range from 0.05 to 0.95.

5. The high-efficiency silicon HJT solar cell according to claim 4, wherein each of the first carbon doped SiO.sub.2 layer and the second carbon doped SiO.sub.2 layer has a thickness in a range from 1 nm to 5 nm.

6. The high-efficiency silicon HJT solar cell according to claim 1, wherein the lightly boron doped amorphous silicon layer is formed by TMB gas doping, and has a thickness in a range from 2 nm to 20 nm and an energy gap in a range from 1.7 eV to 1.8 eV.

7. The high-efficiency silicon HJT solar cell according to claim 6, wherein the heavily boron doped amorphous silicon layer is formed by B.sub.2H.sub.6 gas doping, and has a thickness in a range from 2 nm to 20 nm and an energy gap in a range from 1.4 eV to 1.6 eV.

8. The high-efficiency silicon HJT solar cell according to claim 1, wherein the amorphous silicon doped N-type layer has a thickness in a range from 10 nm to 30 nm; the amorphous silicon doped N-type layer comprises a lightly phosphorus doped amorphous silicon layer and a heavily phosphorus doped amorphous silicon layer, the lightly phosphorus doped amorphous silicon layer is close to the first carbon doped SiO.sub.2 layer, and the heavily phosphorus doped amorphous silicon layer is close to the first TCO conductive layer; the lightly phosphorus doped amorphous silicon layer has a thickness in a range from 2 nm to 20 nm, and the heavily phosphorus doped amorphous silicon layer has a thickness in a range from 2 nm to 20 nm.

9. The high-efficiency silicon HJT solar cell according to claim 7, wherein the amorphous silicon doped N-type layer has a thickness in a range from 10 nm to 30 nm; the amorphous silicon doped N-type layer comprises a lightly phosphorus doped amorphous silicon layer and a heavily phosphorus doped amorphous silicon layer, the lightly phosphorus doped amorphous silicon layer is close to the first carbon doped SiO.sub.2 layer, and the heavily phosphorus doped amorphous silicon layer is close to the first TCO conductive layer; the lightly phosphorus doped amorphous silicon layer has a thickness in a range from 2 nm to 20 nm, and the heavily phosphorus doped amorphous silicon layer has a thickness in a range from 2 nm to 20 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a structural diagram of a high-efficiency silicon HJT solar cell according to the present disclosure.

(2) 1: N-type crystal silicon wafer; 201 (301): thin SiO.sub.2 layer; 202 (302): hydrogenated amorphous carbon silicon oxide film layer; 203 (303): carbon doped SiO.sub.2 layer; 401: lightly boron doped amorphous silicon layer; 402: heavily boron doped amorphous silicon layer; 501: lightly phosphorus doped amorphous silicon layer; 502: heavily phosphorus doped amorphous silicon layer; 6 (7): TCO conductive layer; 8 (9): electrode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(3) In order to further understand the content of the present disclosure, the present disclosure is described in detail with reference to the accompanying drawings and embodiments.

Embodiment 1

(4) Referring to FIG. 1, a high-efficiency silicon HJT solar cell in this embodiment includes an N-type crystal silicon wafer 1. A thin SiO.sub.2 layer 301, a hydrogenated amorphous carbon silicon oxide film layer 302, a carbon doped SiO.sub.2 layer 303, an amorphous silicon doped N-type layer, a TCO conductive layer 7, and an electrode 9 are successively arranged on a front surface of the N-type crystal silicon wafer 1. A thin SiO.sub.2 layer 201, a hydrogenated amorphous carbon silicon oxide film layer 202, a carbon doped SiO.sub.2 layer 203, an amorphous silicon doped P-type layer, a TCO conductive layer 6, and an electrode 8 are successively arranged on a rear surface of the N-type crystal silicon wafer 1.

(5) The high-quality thin SiO.sub.2 layer has a thickness of 1 nm, and passivates a surface of a silicon substrate.

(6) The hydrogenated amorphous carbon silicon oxide film layer has a thickness of 2 nm. In this embodiment, the hydrogenated amorphous carbon silicon oxide film layer is non-stoichiometric and has a chemical formula expressed as a-SiOxCy:H, with a non-stoichiometric ratio x changing in a range from 0.05 to 0.95 and a non-stoichiometric ratio y changing in a range from 0.05 to 0.95. By changing the non-stoichiometric ratios x and y, the energy gap may be adjusted in a range from 1.7 eV to 2.3 eV.

(7) Silicon carbide is an important anti-reflection layer and a passivation layer of a crystalline silicon cell. In combination with advantages of silicon oxide, silicon carbide, and intrinsic amorphous silicon, the hydrogenated amorphous carbon silicon oxide film (a-SiOxCy:H) layer can be obtained by adjusting the composition. By changing the non-stoichiometric ratios x and y, the performance of the hydrogenated amorphous carbon silicon oxide film layer, such as optical energy gap, can be adjusted to achieve excellent passivation performance and a thick film thickness.

(8) In this embodiment, the hydrogenated amorphous carbon silicon oxide film layer has a non-stoichiometric ratio x of 0.05 and a non-stoichiometric ratio y of 0.95, and the energy gap may be modulated to 2.3 eV.

(9) The carbon doped SiO.sub.2 layer has a thickness of 1 nm.

(10) The amorphous silicon doped P-type layer has a thickness of 10 nm, and the amorphous silicon doped N-type layer has a thickness of 10 nm. The TCO conductive layer has a thickness of 70 nm.

(11) In this embodiment, a surface of a silicon substrate is passivated by a high-quality thin SiO.sub.2 layer to passivate broken bonds on the surface of crystalline silicon, and an intrinsic hydrogenated amorphous carbon silicon oxide film (a-SiOxCy:H) layer can modulate an energy gap to provide excellent passivation performance and provide a hydrogen passivation interface.

Embodiment 2

(12) A high-efficiency silicon HJT solar cell in this embodiment is basically the same as that in Embodiment 1, except that the high-quality thin SiO.sub.2 layer has a thickness of 3 nm. The hydrogenated amorphous carbon silicon oxide film layer has a thickness of 10 nm. The hydrogenated amorphous carbon silicon oxide film layer has a non-stoichiometric ratio x of 0.95, a non-stoichiometric ratio y of 0.05, and an energy gap of 1.7 eV. The carbon doped SiO.sub.2 layer has a thickness of 5 nm. The amorphous silicon doped P-type layer has a thickness of 30 nm, and the amorphous silicon doped N-type layer has a thickness of 30 nm. The TCO conductive layer has a thickness of 110 nm.

Embodiment 3

(13) Referring to FIG. 1, a high-efficiency silicon HJT solar cell in this embodiment includes an N-type crystal silicon wafer 1. A thin SiO.sub.2 layer 301, a hydrogenated amorphous carbon silicon oxide film layer 302, a carbon doped SiO.sub.2 layer 303, an amorphous silicon doped N-type layer, a TCO conductive layer 7, and an electrode 9 are successively arranged on a front surface of the N-type crystal silicon wafer 1. A thin SiO.sub.2 layer 201, a hydrogenated amorphous carbon silicon oxide film layer 202, a carbon doped SiO.sub.2 layer 203, an amorphous silicon doped P-type layer, a TCO conductive layer 6, and an electrode 8 are successively arranged on a rear surface of the N-type crystal silicon wafer 1.

(14) The high-quality thin SiO.sub.2 layer has a thickness of 2 nm, and passivates a surface of a silicon substrate.

(15) The hydrogenated amorphous carbon silicon oxide film layer has a thickness of 5 nm. In this embodiment, the hydrogenated amorphous carbon silicon oxide film layer has a non-stoichiometric ratio x of 0.55, a non-stoichiometric ratio y of 0.45, and an energy gap of 1.95 eV.

(16) The carbon doped SiO.sub.2 layer has a thickness of 3 nm, and a small number of lightly boron doped or lightly phosphorus doped atoms are contained in a manner of doping the SiO.sub.2 layer with the same family, so as to prevent the influence on the passivation effect due to unnecessary doping of the intrinsic hydrogenated amorphous carbon silicon oxide film (a-SiOxCy:H) layer.

(17) The amorphous silicon doped P-type layer has a thickness of 20 nm, the amorphous silicon doped P-type layer includes a lightly boron doped amorphous silicon layer 401 and a heavily boron doped amorphous silicon layer 402, the lightly boron doped amorphous silicon layer 401 is close to the carbon doped SiO.sub.2 layer 203, and the heavily boron doped amorphous silicon layer 402 is close to the TCO conductive layer 6. By changing a doping source and a doping concentration, the energy gap of the doped layer can be modulated, and a doped layer with high thermal stability and a large energy gap can be formed on a light receiving surface, so that more incident light can pass through the doped layer on the light receiving surface and more light waves can be effectively absorbed to generate photon-generated carriers. In this embodiment, the lightly boron doped amorphous silicon layer 401 is formed by TMB gas doping, and has a thickness of 2 nm and an energy gap of 1.7 eV. The heavily boron doped amorphous silicon layer 402 is formed by B.sub.2H.sub.6 gas doping, and has a thickness of 18 nm and an energy gap of 1.4 eV.

(18) The amorphous silicon doped N-type layer has a thickness of 20 nm. The amorphous silicon doped N-type layer includes a lightly phosphorus doped amorphous silicon layer 501 and a heavily phosphorus doped amorphous silicon layer 502, the lightly phosphorus doped amorphous silicon layer 501 is close to the carbon doped SiO.sub.2 layer 303, and the heavily phosphorus doped amorphous silicon layer 502 is close to the TCO conductive layer 7. The lightly phosphorus doped amorphous silicon layer 501 has a thickness of 2 nm, and the heavily phosphorus doped amorphous silicon layer 502 has a thickness of 18 nm.

(19) The TCO conductive layer has a thickness of 70 nm.

(20) In this embodiment, a small number of lightly boron doped or lightly phosphorus doped atoms diffusing into the intrinsic hydrogenated amorphous carbon silicon oxide film (a-SiOxCy:H) layer are contained in a manner of doping the SiO.sub.2 layer with the same family, so as to prevent unnecessary doping of the intrinsic hydrogenated amorphous carbon silicon oxide film (a-SiOxCy:H) layer and ensure the passivation effect. At the same time, P-type and N-type heavily doped amorphous silicon layers can form good electrical contact with the TCO layer. The P-type amorphous silicon doped layer on a backlight surface is of a dual stacked structure, and TMB gas is used for doping near the carbon doped SiO.sub.2 layer to prevent the diffusion of the doped atoms B (boron) into the intrinsic layer of amorphous silicon, so as to ensure a passivation effect of intrinsic amorphous silicon and increase an open-circuit voltage Voc. The doped amorphous silicon layer close to crystalline silicon is doped with TMB gas, and has a large energy gap, so the light can pass through the doped layer in a higher proportion, thereby increasing absorption of the light by crystalline silicon and increasing a short-circuit current Isc. The doped amorphous silicon layer close to one side of the TCO is heavily doped with B.sub.2H.sub.6 gas. The conductivity of the doped layer is better, and series resistance Rs of the solar cell is lower, so that an FF is higher. Finally, the photoelectric conversion efficiency of the HJT solar cell is improved.

(21) A preparation process for a high-efficiency silicon HJT solar cell in this embodiment includes the following steps.

(22) In step one, the N-type crystal silicon wafer 1 is textured and cleaned.

(23) In step two, thin SiO.sub.2 layers are formed on two surfaces of the N-type crystal silicon wafer 1 by thermal oxidation.

(24) In step three, a hydrogenated amorphous carbon silicon oxide film layer is grown, by PECVD, on each of a front surface and a rear surface of the N-type crystal silicon wafer 1 on which the thin SiO.sub.2 layers are formed. In an embodiment, vacuuming to below 510.sup.4 Pa is performed, H.sub.2 and SiH.sub.4 are taken as reaction gases, CO is taken as a carbon source, and an oxygen source is provided to grow the hydrogenated amorphous carbon silicon oxide film layer under conditions that the N-type crystal silicon wafer 1 is at a temperature of 150 C. and deposition pressure is 10 Pa. A percentage of a volume of carbon monoxide in a sum of volumes of carbon monoxide and SiH.sub.4 is 5%.

(25) In step four, a carbon doped SiO.sub.2 layer is prepared by PECVD, wherein a C source is CO.

(26) In step five, an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer are prepared by PECVD. The amorphous silicon doped N-type layer includes a lightly phosphorus doped amorphous silicon layer (i.e., an N-type amorphous silicon layer lightly doped with P atoms) and a heavily phosphorus doped amorphous silicon layer (i.e., an N-type amorphous silicon layer heavily doped with P atoms), and the amorphous silicon doped P-type layer includes a P-type amorphous silicon layer lightly doped with B atoms formed by TMB gas doping and a P-type amorphous silicon layer heavily doped with B atoms formed by B.sub.2H.sub.6 gas doping.

(27) A deposition process of the doped layers involves: after base vacuum of a vacuum chamber reaches 510.sup.4 Pa, growing the amorphous silicon doped N-type layer and the amorphous silicon doped P-type layer on the hydrogenated amorphous carbon silicon oxide film layer on the rear surface at a temperature of a silicon wafer substrate of 100 C. by taking H.sub.2, SiH.sub.4, doped TMB, B.sub.2H.sub.6, and PH.sub.3 as reaction gases, and deposition pressure of 10 Pa.

(28) In step six, a transparent conductive ITO film is deposited on each of the front and rear surfaces by magnetron sputtering, wherein the film has transmittance above 98% and sheet resistance of 50/.

(29) In step seven, another layer of low-temperature conductive silver paste is printed on the TCO conductive layers on the front and rear surfaces by screen printing, and then sintered at a low temperature of 150 C. to form good ohmic contact. An Ag electrode has a thickness of 5 m, a width of 20 m, and a spacing of 1 mm.

(30) The HJT solar cell with non-stoichiometric hydrogenated amorphous silicon oxide films as an intrinsic passivation layer and a double diffused boron doped P-type layer has photoelectric conversion efficiency above 24.2%, and the short-circuit current and the open-circuit voltage are increased significantly.

Embodiment 4

(31) A high-efficiency silicon HJT solar cell in this embodiment is basically the same as that in Embodiment 3, except the following differences.

(32) The amorphous silicon doped P-type layer has a thickness of 10 nm, and the lightly boron doped amorphous silicon layer 401 has a thickness of 8 nm and an energy gap of 1.8 eV. The heavily boron doped amorphous silicon layer 402 has a thickness of 2 nm and an energy gap of 1.6 eV.

(33) The amorphous silicon doped N-type layer has a thickness of 10 nm, the lightly phosphorus doped amorphous silicon layer 501 has a thickness of 8 nm, and the heavily phosphorus doped amorphous silicon layer 502 has a thickness of 2 nm.

(34) A preparation process for a high-efficiency silicon HJT solar cell in this embodiment includes the following steps.

(35) In step one, the N-type crystal silicon wafer 1 is textured and cleaned.

(36) In step two, thin SiO.sub.2 layers are formed on two surfaces of the N-type crystal silicon wafer 1 by thermal oxidation.

(37) In step three, a hydrogenated amorphous carbon silicon oxide film layer is grown, by PECVD, on each of a front surface and a rear surface of the N-type crystal silicon wafer 1 on which the thin SiO.sub.2 layers are formed. In an embodiment, vacuuming to below 510.sup.4 Pa is performed, H.sub.2 and SiH.sub.4 are taken as reaction gases, CO is taken as a carbon source, and an oxygen source is provided to grow the hydrogenated amorphous carbon silicon oxide film layer under conditions that the N-type crystal silicon wafer 1 is at a temperature of 180 C. and deposition pressure is 30 Pa. A percentage of a volume of carbon monoxide in a sum of volumes of carbon monoxide and SiH.sub.4 is 5%.

(38) In step four, a carbon doped SiO.sub.2 layer is prepared by PECVD, wherein a C source is CO.

(39) In step five, an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer are prepared by PECVD. A deposition process of the doped layers involves: after base vacuum of a vacuum chamber reaches 510.sup.4 Pa, growing the amorphous silicon doped N-type layer and the amorphous silicon doped P-type layer on the hydrogenated amorphous carbon silicon oxide film layer on the rear surface at a temperature of a silicon wafer substrate of 150 C. by taking H.sub.2, SiH.sub.4, doped TMB, B.sub.2H.sub.6, and PH.sub.3 as reaction gases, and deposition pressure of 50 Pa.

(40) In step six, a transparent conductive ITO film is deposited on each of the front and rear surfaces by magnetron sputtering, wherein the film has a thickness of 80 nm, transmittance above 98% and sheet resistance of 50/.

(41) In step seven, another layer of low-temperature conductive silver paste is printed on the TCO conductive layers on the front and rear surfaces by screen printing, and then sintered at a low temperature of 150 C. to form good ohmic contact. An Ag electrode has a thickness of 15 m, a width of 30 m, and a spacing of 3 mm.

Embodiment 5

(42) A high-efficiency silicon HJT solar cell in this embodiment is basically the same as that in Embodiment 3, except the following differences.

(43) The amorphous silicon doped P-type layer has a thickness of 30 nm, and the lightly boron doped amorphous silicon layer 401 has a thickness of 18 nm and an energy gap of 1.75 eV. The heavily boron doped amorphous silicon layer 402 has a thickness of 12 nm and an energy gap of 1.5 eV.

(44) The amorphous silicon doped N-type layer has a thickness of 30 nm, the lightly phosphorus doped amorphous silicon layer 501 has a thickness of 18 nm, and the heavily phosphorus doped amorphous silicon layer 502 has a thickness of 12 nm.

(45) A preparation process for a high-efficiency silicon HJT solar cell in this embodiment includes the following steps.

(46) In step one, the N-type crystal silicon wafer 1 is textured and cleaned.

(47) In step two, thin SiO.sub.2 layers are formed on two surfaces of the N-type crystal silicon wafer 1 by thermal oxidation.

(48) In step three, a hydrogenated amorphous carbon silicon oxide film layer is grown, by PECVD, on each of a front surface and a rear surface of the N-type crystal silicon wafer 1 on which the thin SiO.sub.2 layers are formed. In an embodiment, vacuuming to below 510.sup.4 Pa is performed, H.sub.2 and SiH.sub.4 are taken as reaction gases, CO is taken as a carbon source, and an oxygen source is provided to grow the hydrogenated amorphous carbon silicon oxide film layer under conditions that the N-type crystal silicon wafer 1 is at a temperature of 300 C. and deposition pressure is 100 Pa. A percentage of a volume of carbon monoxide in a sum of volumes of carbon monoxide and SiH.sub.4 is 30%.

(49) In step four, a carbon doped SiO.sub.2 layer is prepared by PECVD, wherein a C source is CO.

(50) In step five, an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer are prepared by PECVD. A deposition process of the doped layers involves: after base vacuum of a vacuum chamber reaches 510.sup.4 Pa, growing the amorphous silicon doped N-type layer and the amorphous silicon doped P-type layer on the hydrogenated amorphous carbon silicon oxide film layer on the rear surface at a temperature of a silicon wafer substrate of 300 C. by taking H.sub.2, SiH.sub.4, doped TMB, B.sub.2H.sub.6, and PH.sub.3 as reaction gases, and deposition pressure of 300 Pa.

(51) In step six, a transparent conductive ITO film is deposited on each of the front and rear surfaces by reactive ion deposition, wherein the film has a thickness of 110 nm, transmittance above 98% and sheet resistance of 100 /.

(52) In step seven, another layer of low-temperature conductive silver paste is printed on the TCO conductive layers on the front and rear surfaces by screen printing, and then sintered at a low temperature of 190 C. to form good ohmic contact. An Ag electrode has a thickness of 50 m, a width of 60 m, and a spacing of 5 mm.

(53) The present disclosure and implements thereof are illustrated above, but the description is not restrictive. The accompanying drawings are only one of the implementations of the present disclosure, and an actual structure is not limited thereto. Therefore, if those of ordinary skill in the art are inspired to design structures and embodiments similar to the technical solution without departing from the creation purpose of the present disclosure and without creativity, such structures and embodiments fall within the protection scope of the present disclosure.