WAFER LEVEL PACKAGE

Abstract

A fullcover package solution in comnination with copper pillars or solder bumps and acoustic cavities is propsed to provide maximum usable design area compared to current thin film acoustic wafer level packages. Manufacturing can be done in a self-aligned interconnection process.

Claims

1. (canceled)

2. A wafer level package, comprising: a substrate having a functional layer and electric device structures realized in the functional layer, on the functional layer, or under the functional layer; a first package layer applied on the substrate, the first package layer defining cavities between the substrate and the first package layer, at least part of the electric device structures being arranged in the cavities; a second package layer applied over a surface of the first package layer; pads arranged on the substrate and connected to the electric device structures, a partial area of each pad forming a respective contact area that is not covered by the first package layer or the second package layer; and an interconnect structure deposited on each respective contact area and extending up to an interconnected height (h.sub.i) over the substrate, the interconnected height being higher than a package height (h.sub.p) of the first package layer and the second package layer over the substrate; wherein a plurality of gaps are disposed between edges of the first package layer and respective circumferences of respective interconnect structures surrounded by corresponding edges of the first package layer.

3. The wafer level package of claim 2, wherein: the first package layer is a rigid inorganic layer; and the second package layer is a polymer layer.

4. The wafer level package of claim 2, wherein a margin along at least one edge of the substrate excludes the second package layer, wherein at least some of the respective contact areas and corresponding interconnect structures are fully enclosed by the second package layer, and wherein other contact areas are situated at an edge of the second package layer such that the other contact areas are only partially surrounded by the second package layer.

5. The wafer level package of claim 2, wherein cutouts in a selected package layer defines shapes of the respective contact areas, and wherein the selected package layer is chosen from first package layer, the second package layer, or an additional resist layer that is optionally applied over the second package layer.

6. The wafer level package of claim 2, wherein the first package layer is formed of SiO.sub.2 or SiN.

7. The wafer level package of claim 2, wherein the electric device structures are acoustic resonators.

8. The wafer level package of claim 2, wherein the second package layer has a planar surface parallel to a surface of the substrate and comprises a photosensitive resist.

9. The wafer level package of claim 2, wherein the interconnect structure and the substrate have a common edge vertical to a surface of the substrate.

10. The wafer level package of claim 2, wherein the first package layer, the second package layer, and an additional dielectric layer on top of the second package layer have non-coincident structure edges, and wherein a complete surface of the first package layer is covered by one or more of the second package layer or the additional dielectric layer.

11. A wafer level package, comprising: a substrate having a functional layer and electric device structures realized in the functional layer, on the functional layer or under the functional layer; a plurality of pads arranged on the substrate and each connected to at least one of the electric device structures, a partial area of each pad forming a respective contact area; a first package layer applied on the substrate, the first package layer extending partially over at least one pad of the plurality of pads, a second package layer extending over a surface of the first package layer and extending partially over the at least one pad; and an interconnect structure deposited on each respective contact area, wherein a distance between a center of the interconnect structure and the second package layer is less than a distance between the center of the interconnect structure and the first package layer.

12. The wafer level package of claim 11, wherein the at least one pad extends under the first package layer and the second package layer.

13. The wafer level package of claim 11, wherein: the first package layer is a rigid inorganic layer; and the second package layer is a polymer layer.

14. The wafer level package of claim 11, wherein a margin along at least one edge of the substrate excludes the second package layer, wherein at least some of the respective contact areas and corresponding interconnect structures are fully enclosed by the second package layer, and wherein other contact areas are situated at an edge of the second package layer such that the other contact areas are only partially surrounded by the second package layer.

15. The wafer level package of claim 11, wherein cutouts in a selected package layer defines shapes of the respective contact areas, and wherein the selected package layer is chosen from first package layer, the second package layer, or an additional resist layer that is optionally applied over the second package layer.

16. The wafer level package of claim 11, wherein the first package layer is formed of SiO.sub.2 or SiN.

17. The wafer level package of claim 11, wherein the electric device structures are acoustic resonators.

18. The wafer level package of claim 11, wherein the second package layer has a planar surface parallel to a surface of the substrate and comprises a photosensitive resist.

19. The wafer level package of claim 11, wherein the interconnect structure and the substrate have a common edge vertical to a surface of the substrate.

20. The wafer level package of claim 11, wherein the first package layer, the second package layer, and an additional dielectric layer on top of the second package layer have non-coincident structure edges, and wherein a complete surface of the first package layer is covered by one or more of the second package layer or the additional dielectric layer.

21. The wafer level package of claim 11, wherein the interconnect structure comprises copper (Cu) pillars or solder bumps.

Description

[0025] In the following the wafer level package will be explained in more detail with reference to specific embodiments and the accompanied figures. The figures are schematic only and may not show all elements as far as these omitted elements are known in the art and can easily be complemented by a skilled worker. Moreover the figures are not drawn to scale and some details may be depicted enlarged for clarity reason and better understanding.

[0026] FIG. 1 shows a wafer level package according to a first embodiment in a schematic cross section

[0027] FIG. 2 shows a wafer level package according to a second embodiment in a schematic cross section

[0028] FIG. 3 shows a wafer level package according to a third embodiment in a schematic cross section

[0029] FIG. 4 shows a larger depiction of a wafer level package in a schematic cross section

[0030] FIG. 5 shows a schematic block diagram of a filter device that may be encapsulated by the new wafer level package

[0031] FIG. 6 shows a schematic sectional top view onto the new wafer level package

[0032] FIG. 7 shows a schematic top view onto a variant of the new wafer level package

[0033] FIG. 8 shows a schematic top view onto another variant of the new wafer level package.

[0034] FIG. 1 shows a wafer level package according to a first embodiment in a schematic cross section. The package is depicted partially only and generally shows the area around the interconnect structure. In the following the process of manufacturing is explained.

[0035] The package is formed on a substrate SU that includes a functional material or has at least a functional layer as a top layer. The functional layer comprises a material that is functional for the electric device formed therein or thereon. The functional material is e.g. a piezoelectric material and the device is a micro acoustic device, e.g. a SAW filter or a BAW device. The filter device is formed by applying device structures DS (as shown in FIG. 4) on the top surface of the substrate or to the functional layer. The device structures of a SAW device comprise interdigital transducers, reflectors and pads PD for electrically contacting the device. The device structures of a BAW device comprise top and bottom electrodes applied under the functional layer. Only a pad connected to the device structures is shown in this figure.

[0036] Acoustically active device structures (not shown in this figure) are generally mechanically and may be also hermetically protected by a package. A first package layer PL1 applied above the device structures forms domes over mechanically sensitive device structures that are in the example acoustically active device structures. For this purpose the first package layer of e.g. a dielectric is sufficiently rigid to freely span over the device structures in a distance forming a dome and keeping enclosed thereunder a cavity. SiO.sub.2 or SiN are exemplary useful materials. The thickness of the first package layer is chosen to provide sufficient stability for the dome and depends on the diameter of the enclosed cavity. The cavities may be pre-formed in the first package layer or may be produced by way of a structure of sacrificial material that has to be removed after deposition of the package layer(s).

[0037] However other electric devices like MEMS devices or sensors may be packaged by way of the proposed wafer level package.

[0038] After being applied to the entire surface the first package layer is structured such that it rests on and seals to the substrate at least around the circumference of the domes. Further, after structuring the first package layer the contact areas of the pads PD are exposed.

[0039] In the next step a second package layer PL2 is deposited, e.g. in a planar manner, on the entire surface on the first package layer PL1. In a variant it is possible to leave a margin at the edge of the substrate uncovered. A polymer may be a photosensitive polymer like a photoresist is useful as the second package layer PL2 that is required for reinforcing the first package layer PL1. The polymer may be applied as a foil or in liquid or viscous form. The top surface may be already planar after deposition and no pressure is necessary for planarization.

[0040] In the next step the second package layer PL2 is structured by removing the layer where underlying structures need to be exposed. In the depicted embodiment the structural edges of the second package layer overlay the respective edges of the first package layer at the edge to the pad PD. At the outer edge towards the edge of the substrate SU structural edges of first and second package layer may comply. Here in the depicted example the second package layer covers a larger area than the first package layer.

[0041] In the region of the pad PD, the contact area exposed from both package layers is here completely defined by the surrounding edges of the second package layer PL2.

[0042] Then interconnect structures IS are formed in the next step selectively on the exposed contact areas. A selective metal deposition can be performed galvanically or current-less in a chemical metal deposition bath. A material may be Cu. However, forming interconnects from a solder is possible too.

[0043] The interconnect structures IS are grown up to a height h.sub.i that is higher than the combined height h.sub.p of the two package layers PL1, PL2. Then it is possible to easily mount the package as a whole to a PCB for example by way of the interconnect structures IS.

[0044] In case that the interconnect structure is a copper pillar a solder cap SC is applied on top thereof. An intermediate layer of e.g. Ni may be arranged between solder cap and Cu pillar.

[0045] Due to the full die coverage some of the safety distances do not need to be considered for spacing. An used exemplary distance employs a ratio of interconnect radius r.sub.i to package distance d.sub.ip of 1.4. In the dicing street region the ratio of the radius of the interconnect structures IS and the distance between the center of the interconnect structure IS to the outermost layer edge at the dicing street is currently around 2 to 3. With the proposed wafer level package both ratios can be reduced to one.

[0046] The full active die area is covered by the polymer of the second package layer PL2. Within this area the interconnects can be placed freely.

[0047] The possibility to fully enclose interconnects allows a placement of interconnects much closer to the sensitive active structures e.g. to resonators of a filter circuit. Thermal management is improved as well as the electrical performance of the device in the package. Moreover the embedding under the two package layers enhances the mechanical stability of the final device that is a die after dicing the large area package that is usually formed on a substrate wafer.

[0048] FIG. 2 shows a feature of a wafer level package according to a second embodiment in a schematic cross section.

[0049] Similar to the embodiment shown in FIG. 1 the interconnect structure IS is formed here by defining a contact area on the pad PD by means of structural edges of the second package layer PL2. However, at pads arranged near the outer edge of the substrate the structural edges of the second package layer do not fully surround the later contact area. On the remaining circumference uncovered edges of the pad are terminating the contact area. Hence, the interconnect structure IS is not fully surrounded and bounded by the first or second package layer. Here, the ratio of the radius of the interconnect structure IS and the distance between the center of the interconnect structure IS to the outermost layer edge at the dicing street is just one and hence, minimized.

[0050] When depositing or growing the interconnect structure IS, this structure may grow over the exposed outer edge of the pad PD which is the right edge in FIG. 2.

[0051] In a wafer level package different interconnects may be present at the same time. Where pads are located near the center of the package, these pads are interconnected by interconnect structures according to first embodiment shown in FIG. 1. Pads that are located near the edge of the substrate or near a later dicing street are interconnected by interconnect structures according to second embodiment shown in FIG. 2. FIG. 2 shows the second package layer overlapping the edge of the first package layer at the left edge of the pad PD. However it is possible that the edges of both package layers comply with each other.

[0052] FIG. 3 shows how the contact areas and interconnects have been formed according to the art. Here, exclusively an additional package layer AR has been applied over the second package layer PL2 to reinforce same and to define the contact area. When doing this, overlay errors and process deviations for each layer forming step have to be taken into account that high tolerances are required that enlarge the substrate area required.

[0053] In the cross section of FIG. 3 two different edges of the contact area are shown. On the right side an edge of the first package layer PL1 lays on the pad. Here, the additional package layer AR is applied on a section of the first package layer PL1 further confining the contact area that is smaller in area than the pad. On the left side of the figure the contact area is bounded similarly by an edge of the first package layer and an overlaying section of the additional package layer. A section of the second package layer PL2 is shown to be situated between first package layer and additional package layer but not direct at the boundary of the contact area. On the right side the shown edge of the substrate complies with the dicing street along which dies with single electric devices are singulated.

[0054] FIG. 4 shows a greater cross section of the wafer level package including the cavities CV under the first package layer PL1 in which the device structures DS are arranged. The depicted interconnect structure IS is formed according to the first embodiment shown in FIG. 1 for example.

[0055] The first package layer PL1 is relatively thin compared to the second package layer PL2 that reinforces the package and further provides a planar surface. The structural edges of first or second package layer may serve to bound the contact area and to define the area of the interconnect structure. The ladder is formed as a copper pillar and its top is covered with a solder cap SC.

[0056] FIG. 5 shows a block diagram of an exemplary filter circuit that may be packaged with the proposed package. This filter circuit comprises a number of e.g. four series resonators RS arranged in a series signal line SSL between an input and an output terminal. Respective nodes between each two neighbored series resonators are connected to ground via a parallel branches in which a parallel resonator RP or another impedance element may be arranged. An inductance (not shown) may be circuited between a parallel resonator and ground. A pair of a series resonator RS and a parallel resonator RP or impedance element form together a basic section BS of the filter circuit. Further series elements chosen from an inductance, a capacitance or another passive element may be present too. A filter circuit may have more or less basic sections dependent on the desired selectivity of the filter. More basic section can be used to further tune the filter functionality.

[0057] The resonators may be embodied as SAW resonators. However, also BAW and GBAW resonators can be packaged with the proposed package.

[0058] FIG. 6 is a schematic sectional top view onto the new wafer level package to show the extension of the package layer PL on the substrate SU. As can be seen the interconnect structures IS may be arbitrarily placed on the chip/substrate SU just where an active device structures needs to be contacted, for example along the edges. All interconnect structures are defined by respective cutouts in the second package layer PL2 such that each cutout is completely surrounded by remaining areas of package layer. These interconnects correspond to that shown in FIG. 1 for example. Here the second package layer PL2 does not fully cover the substrate SU but leaves a margin thereof exposed.

[0059] FIG. 7 is a similar schematic sectional top view onto the new wafer level package. Here two different locations of interconnect structures are existing in parallel. Centered interconnections IS.sub.C are embodied as shown in FIG. 6. Further interconnect structures IS.sub.E are situated directly on the edge of a package layer such that the edge intersects the contact area and interconnects formed thereon. This embodiment has the advantage that interconnects can be placed nearer to the edge of substrate SU or die and saves space on the die.

[0060] In both cases as shown in FIGS. 6 and 7 the edges of the package layers E.sub.PL do not extend to the edge of the die or substrate SU but keep a safety margin of the substrate uncovered.

[0061] FIG. 8 is similar to FIG. 7 with the only difference that the second package layer PL fully covers the substrate SU. Hence, edge E.sub.PL2 complies with the edge of the substrate. As no margin is left surface area can be saved on the substrate without violating safety requirements for achieving a high yield and reliable components.

[0062] The invention has been explained with regard to some embodiments and figures but may not be restricted to the exact combination of features according to the embodiments. Any feature that has been described to provide advantage to the wafer level package shall be regarded to be independent from companying other features that are depicted on a common figure or described together in the same embodiment.

LIST OF USED TERMS AND REFERENCE SYMBOLS

TABLE-US-00001 AR additional resist package layer BS Basic section of a ladder type filter circuit CA contact area formed from a partial area of each pad CV cavity d.sub.ie distance between center of interconnect and edge of substrate d.sub.ip Distance between center of interconnect and package layer edge DS electric device structures FL functional layer h.sub.i height of interconnect structure over substrate h.sub.p height of package layers over substrate IS interconnect structure PL1 first package layer PL2 second package layer r.sub.i Radius of interconnect RF Parallel resonator RS Series resonator SSL Series signal line SU substrate