COMMON MODE COMPENSATION CIRCUIT FOR DIFFERENTIAL AMPLIFIERS, CORRESPONDING DEVICE AND METHOD

Abstract

A differential input stage includes first and second input transistors with current flow paths are coupled between a tail transistor current flow path and first and second nodes, respectively. An output stage includes first and second output transistors having current flow paths between a supply line and first and second output nodes, respectively, coupled to the first and second nodes. First and second common-mode control transistors have current flow paths jointly coupled to a ground current flow path of a common-mode tail transistor. The first common-mode control transistor has a control terminal resistively coupled to the first and second output nodes. A bias duplicate transistor has a current flow path arranged in a bias current flow line between the supply line and ground. The bias duplicate transistor is coupled in a 1:N current mirror arrangement with the tail transistor in the differential input stage.

Claims

1. A circuit, comprising: a differential input stage including a first input transistor, a second input transistor and a tail transistor, wherein the first and second input transistors have control terminals configured to receive a differential input signal applied therebetween, wherein the first input transistor has a current flow path coupled between a current flow path of the tail transistor and a first node, while the second input transistor has a current flow path coupled between the current flow path of the tail transistor and a second node; a differential output stage including a first output transistor and a second output transistor, wherein the first output transistor has a current flow path between a supply line and a first output node, and wherein a control terminal of the first output transistor is coupled to the first node in the differential input stage; wherein the second output transistor has a current flow path between the supply line and a second output node; and wherein a control terminal of the second output transistor is coupled to the second node in the differential input stage; common-mode control circuitry comprising a first common-mode control transistor and a second common-mode control transistor having current flow paths jointly coupled to a ground current flow path through a common-mode tail transistor, wherein the first common-mode control transistor has a control terminal resistively coupled to both the first output node and the second output node in the differential output stage; and bias generation circuitry comprising a bias duplicate transistor having a current flow path arranged in a bias current flow line between the supply line and ground, the bias duplicate transistor coupled in a 1:N current mirror circuit arrangement with the tail transistor in the differential input stage.

2. The circuit of claim 1, wherein the differential input stage includes a third input transistor and a fourth input transistor, wherein the current flow path through the first input transistor is configured to be coupled to the supply line at the first node via a current flow path of the third input transistor with the first input transistor intermediate the third input transistor and the tail transistor, wherein the current flow path of the second input transistor is configured to be coupled to the supply line at the second node via a current flow path of the fourth input transistor with the second input transistor intermediate the fourth input transistor and the tail transistor, and wherein the third input transistor and the fourth input transistor have control terminals mutually coupled via a control line.

3. The circuit of claim 2, wherein the differential output stage includes: a third output transistor with a current flow path between the first output node and ground; and a fourth output transistor with a current flow path between the second output node and ground.

4. The circuit of claim 2, wherein the current flow path of the first common-mode control transistor is configured to be coupled to the supply line via a current flow path of a diode-connected third common-mode control transistor having a control terminal coupled to the control line between the control terminals of the third input transistor and the fourth input transistor in the differential input stage with the first common-mode control transistor intermediate the third common-mode control transistor and the common-mode tail transistor, and wherein the current flow path of the second common-mode control transistor is configured to be coupled to the supply line via a current flow path of a diode-connected fourth common-mode control transistor with the second common-mode control transistor intermediate the fourth common-mode control transistor and the common-mode tail transistor.

5. The circuit of claim 1, wherein the bias current flow line between the supply line and ground comprises a cascaded connection of the current flow path of the bias duplicate transistor and the current flow path of a cascaded bias transistor with the cascaded bias transistor between the supply line and the bias duplicate transistor.

6. The circuit of claim 5, further comprising a further bias transistor having a bias current flow path coupled to the supply line and a control terminal coupled to a control terminal of the cascaded bias transistor.

7. The circuit of claim 6, wherein the control terminal of the further bias transistor is coupled both to the control terminal of the cascaded bias transistor and to a control terminal of another bias transistor having a current flow path cascaded with the current flow path of another bias duplicate transistor in a current flow line between the supply line and ground.

8. The circuit of claim 7, wherein the control terminal of the further bias transistor is directly coupled to the control terminal of the cascaded bias transistor.

9. The circuit of claim 5, wherein the bias current flow line between the supply line and ground comprises a complementary pair of transistors having current flow paths arranged in parallel between the current flow path of the bias duplicate transistor and the current flow path of the cascaded bias transistor, and wherein the transistors in the complementary pair of transistors have control terminals configured to receive said differential input signal applied therebetween.

10. The circuit of claim 9, wherein: the bias duplicate transistor and the tail transistor in the differential input stage have 1:N current mirror ratios therebetween; and the transistors in said complementary pair of transistors and the first input transistor and the second input transistor in the differential input stage have 1:N current mirror ratios therebetween.

11. The circuit of claim 6, wherein the control terminal of the further bias transistor is coupled to the control terminal of the cascaded bias transistor via a resistor in a resistor capacitor (RC) network, the RC network comprising a capacitor coupled between the control terminal of the cascaded bias transistor and the common current flow path of the tail transistor.

12. The circuit of claim 1, wherein said supply line is configured to receive a supply voltage up to 1.1 V.

13. The circuit of claim 1, wherein the tail transistor in the differential input stage and said bias duplicate transistor are PMOS transistors.

14. A device including the circuit according to claim 1, wherein the device comprises a capacitive sensor.

15. A method, comprising: applying a differential input signal across the control terminals a first input transistor and a second input transistor in a differential input stage of an amplifier including a tail transistor, wherein the first input transistor has a current flow path coupled between a current flow path of the tail transistor and a first node and wherein the second input transistor has a current flow path coupled between the current flow path through the tail transistor and a second node; providing in said amplifier a differential output stage including a first output transistor and a second output transistor, wherein the first output transistor has a current flow path between a supply line and a first output node that is coupled to the first node in the differential input stage and wherein the second output transistor has a current flow path between the supply line and a second output node that is coupled to the second node in the differential input stage; controlling common-mode operation of the amplifier via a first common-mode control transistor and a second common-mode control transistor having current flow paths jointly coupled to a ground current flow path through a common-mode tail transistor by resistively coupling the control terminal of the first common-mode control transistor to the first output node and the second output node in the differential output stage; providing bias generation circuitry comprising a bias duplicate transistor having a current flow path arranged in a bias current flow line between the supply line and ground; and coupling the bias duplicate transistor in a 1:N current mirror arrangement with the tail transistor in the differential input stage.

16. The method of claim 15, further comprising coupling the control terminal of the further bias transistor to the control terminal of the cascaded bias transistor via a resistor in a resistor capacitor (RC) network, the RC network comprising a capacitor coupled between the control terminal of the cascaded bias transistor and the common current flow path of the tail transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0032] FIG. 1 is a diagram illustrative of architecture of a fully differential amplifier;

[0033] FIG. 2 is a diagram illustrative of an equivalent common-mode model of the fully differential amplifier of FIG. 1 implemented using a 2-stage fully differential amplifier;

[0034] FIG. 3 is a diagram illustrative of an equivalent common-mode model of the fully differential amplifier of FIG. 1 implemented using a 3-stage fully differential amplifier;

[0035] FIG. 4 is a circuit diagram of a possible implementation of a 2.sup.nd order operational transconductance amplifier;

[0036] FIG. 5 illustrates the possible presence of an undesired positive common-mode loop in amplifier architecture as illustrated in FIG. 1;

[0037] FIG. 6 illustrates the possible presence of such a positive common-mode loop within the framework of an equivalent common-mode model;

[0038] FIGS. 7 and 8 illustrate, still within the framework of an equivalent common-mode model, the possible application of a general concept underlying solutions as proposed herein;

[0039] FIG. 9 exemplifies a first possible implementation of that concept in an amplifier circuit;

[0040] FIG. 10A illustrates a 2-stage operational transconductance amplifier (OTA) structure showing a possible arrangement of transistors according to solutions as described herein;

[0041] FIG. 10B is a corresponding common-mode model for architecture illustrated in FIG. 10A;

[0042] FIGS. 11A and 12A exemplify possible circuit implementations of solutions as described herein; and

[0043] FIGS. 11B and 12B illustrate respective equivalent common-mode models for architectures as illustrated in FIGS. 11A and 12A.

DETAILED DESCRIPTION

[0044] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

[0045] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0046] Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0047] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0048] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity.

[0049] For the sake of simplicity and ease of explanation: a same designation may be applied throughout this description to designate a certain node or line as well as a signal occurring at that node or line (the supply line or node referred to in the following as VDD may be exemplary of this); a same designation may be applied throughout this description to designate certain component (such as a capacitor, resistor or inductor) as well as electrical parameters thereof.

[0050] Also, when it is mentioned that an element is connected to or coupled to another element, it should be understood that still another element may be interposed therebetween, as well as that the element may be connected or coupled directly to another element.

[0051] On the contrary, when it is mentioned that an element is connected directly to or coupled directly to another element, it should be understood that still another element is not interposed therebetween.

[0052] Low-voltage analog design is a current market trend that is essentially driven by the desire of integrating complex digital functions (that involve scaled technology nodes typically supplied with supply voltages VDD in the order of 1.2V or lower) with analog circuitry that should desirably maintain good performance and reliability despite a reduction in the supply voltage.

[0053] A point to take into account when considering a reduction in the supply voltage of an analog domain is related to the topology of the amplifiers involved.

[0054] An established concept with those skilled in the art is that, in the presence of a given supply voltage VDD, a multistage operational amplifier facilitates achieving a signal voltage swing that is higher than the signal voltage swing that can be reached with single-stage OTAs.

[0055] Multistage OTAs thus represent a current approach adopted by circuit designers when faced with the problem of reducing a supply voltage while maintaining a desired signal-to noise ratio (SNR) of a given application.

[0056] As already noted, various issues may arise in connection with the prospected use of low-voltage multistage OTAs.

[0057] One such issue is related to the stability of the common-mode feedback loop for operational amplifiers expected to operate with supply voltages in the range of 1V or lower.

[0058] FIG. 1 represents architecture of fully differential amplifier circuitry built around an operational transconductance amplifier (hereinafter, briefly OTA) 10. Such a transconductance amplifier can be advantageously incorporated in a capacitive sensor.

[0059] Whatever the specific application envisaged, this kind of amplifier 10 has: two input nodes to the OTA 10, namely V.sub.VGp, V.sub.VGn, each having applied an input (voltage) signal V.sub.INp, V.sub.INn via an input network Z.sub.I; and output nodes from the OTA 10, namely V.sub.OUTn, V.sub.OUTp, each coupled to a respective input node V.sub.VGp, V.sub.VGn to the OTA 10 via a feedback network Z.sub.F so that a (negative) differential feedback is returned to the input according to a desired function to the block.

[0060] FIG. 2 is a diagram illustrative of the equivalent common-mode model of a fully differential amplifier implemented using a 2-stage OTA where single blocks designated Z.sub.I and Z.sub.F are shown under the (reasonable) assumption that the corresponding networks in the differential architecture of FIG. 1 have the same values.

[0061] In the case of the equivalent common-mode model of FIG. 2: GM.sub.CM1 (block 101) is the common-mode transconductance of the first stage of the OTA 10; R.sub.1 is the common-mode output resistance of the first stage of the OTA 10; GM.sub.CM2 (block 102) is the common-mode transconductance of the second stage of the OTA; R.sub.2 is the common-mode output resistance of the second stage of the OTA; GM.sub.CM4 (block 104) is the transconductance of the common-mode control-stage of the OTA; and C.sub.C is a capacitance which can be regarded as arranged across the second stage 102 and the common-mode control-stage 104 of the OTA.

[0062] In the case of the equivalent common-mode model of FIG. 2 the following relationships apply:

[00001]$V_{\mathrm{IN}\_\mathrm{CM}}=\left(V_{\mathrm{INp}}+V_{\mathrm{INn}}\right)/2$$V_{\mathrm{VG}\_\mathrm{CM}}=\left(V_{\mathrm{VGp}}+V_{\mathrm{VGn}}\right)/2$$V_{\mathrm{OUT}\_\mathrm{CM}}=\left(V_{\mathrm{OUTp}}+V_{\mathrm{OUTn}}\right)/2.$

[0063] FIG. 3 is a diagram illustrative of the equivalent common-mode model of a 3-stage OTA. Here again, single blocks designated Z.sub.I and Z.sub.F are shown under the assumption that the corresponding networks in the differential architecture of FIG. 1 have the same values.

[0064] In the case of the equivalent common-mode model of FIG. 3: GM.sub.CM1 (block 101) is the common-mode transconductance of the first stage of the OTA 10; R.sub.1 is the common-mode output resistance of the first stage of the OTA 10; GM.sub.CM2 (block 102) is the common-mode transconductance of the second stage of the OTA; R.sub.2 is the common-mode output resistance of the second stage of the OTA; GM.sub.CM3 (block 103) is the common-mode transconductance of the third stage of the OTA; R.sub.3 is the common-mode output resistance of the third stage of the OTA; GM.sub.CM5 (block 105) is the transconductance of the common-mode control-stage of the OTA; C.sub.C1 is a capacitance which can be regarded as arranged across in parallel to the third stage 103 of the OTA; and C.sub.C2 is a capacitance which can be regarded as arranged across the cascade of the second stage 102 and the third stage 103 of the OTA.

[0065] The representations of FIG. 2 and FIG. 3 are intended to highlight the fact that the issues discussed in the foregoing (and the solutions described herein as well) apply to differential amplifiers such as OTAs irrespective to the number of stages therein.

[0066] As noted, multistage OTAs facilitate achieving a higher output voltage swing for a given supply voltage. This suggests using multistage OTAs in case of low-voltage operation (that is with a supply voltage VDD in the range of 1V or lower).

[0067] FIG. 4 is circuit diagram of a 2.sup.nd order OTA.

[0068] As illustrated in FIG. 4, an exemplary OTA is intended to operate between a supply node or line at a voltage VDD and ground GND, with a differential input signal V.sub.VGp, V.sub.VGn applied at an input stage between the control terminals (gates, in the case of field-effect transistors such as MOSFET transistors) of a first transistor M.sub.1 and a second transistor M.sub.2 having the current flow-paths therethrough (source-drain, in the case of field-effect transistors such as MOSFET transistors) coupled to the line/node VDD via the (source-drain) current flow-paths through a third transistor M.sub.3 and a fourth transistor M.sub.4, respectively.

[0069] The third transistor M.sub.3 and the fourth transistor M.sub.4 have their control terminals (gates, in the case of field-effect transistors such as MOSFET transistors) mutually coupled via a line V.sub.CTRL.

[0070] The source-drain current flow paths through the first transistor M.sub.1 and the second transistor M.sub.2 join at their ends opposite the transistors M.sub.3 and M.sub.4 at a line V.sub.TAIL that is coupled to ground GND via the source-drain current flow-path through a tail transistor M.sub.0.

[0071] The figures and the relative description are illustrative of a field-effect transistor (MOSFET) implementation of the various circuits discussed.

[0072] In fact, solutions as described herein can be advantageously used in connection with MOSFET transistors such as PMOS transistors (see, for instance, the transistors M.sub.C, MD.sub.1, M.sub.E and M.sub.0 discussed in the following).

[0073] At least in principle, at least some of the field-effect transistors described herein could be replaced by bipolar junction transistor (BJT), where the control terminals will be the bases of these transistors and the current paths therethrough will be represented by the emitter-collector current flow path.

[0074] Likewise, the figures and the relative description are illustrative of implementations where VDD is assumed to be a positive voltage with respect to ground GND, with the polarities of the transistors (p-channel/n-channel and p-n-p/n-p-n) selected correspondingly. Those of skill in the art can easily devise corresponding adaptations in case of different voltage/polarity options.

[0075] At a node designated A, located between the transistors M.sub.1 and M.sub.3, a voltage V.sub.1p is applied to the control terminal (gate in the case of a field-effect transistors such as a MOSFET transistor) of a transistor M.sub.5 having the source-drain current flow-path therethrough cascaded with the source-drain current flow-path through a transistor M.sub.7 in a current flow line between the supply node or line VDD and ground GND with an output voltage V.sub.OUTp provided at a node intermediate the transistors M.sub.5 and M.sub.7, with such an intermediate node coupled to the node A via a capacitance C.sub.C (see also FIG. 2).

[0076] At a node designated B, located between the transistors M.sub.2 and M.sub.4, a voltage V.sub.1n is applied to the control terminal (gate in the case of a field-effect transistors such as a MOSFET transistor) of a transistor M.sub.6 having the source-drain current flow-path therethrough cascaded with the source-drain current flow-path through a transistor M.sub.8 in a current flow line between the supply node or line VDD and ground GND with an output voltage V.sub.OUTn provided at a node intermediate the transistors M.sub.6 and M.sub.8 such as the intermediate node coupled to the node B via a capacitance C.sub.C (see again FIG. 2).

[0077] The difference between the voltages V.sub.OUTp and V.sub.OUTn provides a (differential) output from the OTA 10.

[0078] The output nodes V.sub.OUTp and V.sub.OUTn can be regarded as being coupled via respective output resistances R.sub.CM to a common-mode output line V.sub.OUTCM towards the control terminal (gate in the case of a field-effect transistor such as a MOSFET transistor) of a transistor M.sub.CM1 having the source-drain current flow-path therethrough cascaded with the source-drain current flow-path through a diode-connected transistor M.sub.CM3 arranged between the transistor M.sub.CM1 and the supply node/line VDD. The transistor M.sub.CM3 has its control terminal (gate, in the case of a field-effect transistor such as a MOSFET transistor) and the current flow-path therethrough (and its drain, in the case of a field-effect transistor such as a MOSFET transistor) connected to the line named V.sub.CTRL between the gates of the transistors M.sub.3 and M.sub.4.

[0079] A common-mode signal V.sub.CM (generated in a manner known per se to those of skill in the art) is applied to the control terminal (gate, in the case of a field-effect transistor such as a MOSFET transistor) of a transistor M.sub.CM2 having the source-drain current flow-path therethrough cascaded with the source-drain current flow-path through a diode-connected transistor M.sub.CM4 arranged between the transistor M.sub.CM2 and the supply node/line VDD.

[0080] The source-drain current flow paths through the transistor M.sub.CM1 and the transistor M.sub.CM2 join at their ends opposite the transistors M.sub.CM3 and M.sub.CM4 at the source-drain current flow-path through a tail transistor MCMO.

[0081] The control terminals (gates in the case of field-effect transistors such MOSFET transistors) of the transistors M.sub.0, M.sub.7, M.sub.8, and M.sub.CM0 have applied thereto a bias voltage V.sub.BIASn (generated in a manner known per se to those of skill in the art).

[0082] The circuit diagram of FIG. 4 highlights the presence of a common-mode feedback network (OCMFB) from the output nodes V.sub.OUTp, V.sub.OUTn towards the nodes A, B (and thus the nodes V.sub.VGp, V.sub.VGn) via the resistors R.sub.CM and the line V.sub.OUTCM.

[0083] As otherwise known to those skilled in the art, the OCMFB working principle involves reading an output common-mode voltage of the OTA defined as:

[00002]$V_{\mathrm{OUT}}\mathrm{CM}=\left(V_{\mathrm{OUTp}}+V_{\mathrm{OUTn}}\right)/2$

using the resistances R.sub.CM, and comparing this signal with a reference voltage V.sub.CM using a differential pair represented by the common-mode control transistors M.sub.CM1 and M.sub.CM2. The error signal generated by this differential pair is mirrored to the active load of the operational amplifier (transistors M.sub.3 and M.sub.4) with the aim of obtaining an output common-mode voltage V.sub.OUTCM that matches the signal V.sub.CM.

[0084] This common-mode voltage is usually defined at system level and determines also the DC potential of the virtual ground (nodes V.sub.VGp and V.sub.VGn in FIGS. 1 and 4) of the analog block that uses the OTA.

[0085] A value for signal V.sub.CM can be selected as V.sub.CM=VDD/2 as this may maximize the output swing of the stages.

[0086] By way of possible numerical example, one may consider VDD=1.2V and V.sub.CM=0.6V, which is the same for V.sub.VGp and V.sub.VGn in FIG. 2.

[0087] This means that the gate-to-source voltage V.sub.GS of the input differential pair including the transistors M.sub.1 and M.sub.2 must be accommodated in such a small range of 0.6V while leaving enough room for the current generator (transistor M.sub.0) to preserve an acceptable output resistance r.sub.outM.sub.0 for that current generator.

[0088] In practice, this will result in operation of the input transistors M.sub.1 and M.sub.2 in a deep subthreshold region, also with the transistor M.sub.0 biased in this region, in so far as the parameter V.sub.DS_SAT (drain-to-source saturation voltage) is reduced, thus facilitating preserving an acceptable output resistance.

[0089] The area of the differential pair (transistors M.sub.1 and M.sub.2) and the current generator transistor M.sub.0 may be attempted to be selected with the aim of reducing the V.sub.GS voltages and the saturation voltage V.sub.DS_SAT.

[0090] It is otherwise observed that, in the presence of a low value of the supply voltage VDD, there will be PVT (Process-Voltage-Temperature) corners where the output resistance of transistor M.sub.0 will drop, with a detrimental effect on the common-mode-rejection-ratio (CMRR) of the operational amplifier.

[0091] In these corners the OCMFB can potentially became unstable.

[0092] As schematically represented in FIG. 5 (by direct comparison with FIG. 1) this instability is related to a positive common-mode loop PCML expressed by the multistage OTA 10 in response to a reduction of the output resistance r.sub.OUTM.sub.0 at tail generator transistor M.sub.0.

[0093] This positive common-mode loop is also represented in FIG. 6 by referring to the common-mode model of FIG. 2.

[0094] In FIGS. 5 and 6 (where the undesired positive common-mode loop PCML is highlighted) parts/elements/entities already introduced in connection with FIGS. 1 and 2 are indicated with the same reference symbols and a corresponding description will not be repeated here for brevity.

[0095] It is observed that, for a given application, the output common-mode is brought back to the inputs through the specific feedback network of the block, and it is then amplified by the common-mode gain of the OTA defined as:

[00003]$G_{\mathrm{CM}}=\left(V_{\mathrm{OUTp}}+V_{\mathrm{OUTn}}\right)/\left(V_{\mathrm{INp}}+V_{\mathrm{INn}}\right).$

[0096] This common-mode loop PCML as represented in FIGS. 5 and 6 (with positive gain for multistage OTAs, and negative gain for single-stage OTAs) works together with the internal OCMFB of the OTA modifying its properties.

[0097] In a typical corner, the effect of this undesired additive loop may be limited by the CMRR of the OTA 10 that reduce the value of G.sub.CM, but on some PVT corner where the CMRR drops (usually at cold temperature), the interaction of the two loops PCML could lead to instability.

[0098] The stability of an OCMFB loop in a 2-stage OTA can be investigated by noting that, for instance, while a TYP 27 C. corner can be tolerated (no instability) for a certain OTA, stability is severely deteriorated at the SSA 40 C. corner, as expressed by both a poor phase margin PM (with PM=35 in SSA 40 C. in comparison to PM=52 in TYP 27 C.) of the Bode plot and a resulting ringing noticeable in transient simulation.

[0099] Solutions as proposed herein are represented in FIGS. 7 and 8 by referring at first to an equivalent common-mode model as already introduced in connection with FIG. 2 and FIG. 6.

[0100] In FIGS. 7 and 8 parts/elements/entities already introduced in connection with FIGS. 2 and 6 are indicated with the same reference symbols and a corresponding description will not be repeated here for brevity.

[0101] Essentially, a first possible implementation of solutions as proposed herein can be based on the introduction of a resistor capacitor (RC) network (essentially the block GM.sub.COMP indicated as 200 in FIG. 7) with the purpose of partially restoring the CMRR of the OTA at least for the range of frequency near the 0 dB crossing of the OCMFB.

[0102] By introducing the block/stage 200 with GM.sub.COMP=GM.sub.CM1 (block 101) the undesired positive common-mode loop PCML is removed.

[0103] Stated otherwise (and as depicted in FIG. 8), under the condition GM.sub.COMP=GM.sub.CM1, the CMRR of the OTA is virtually infinite with the possibility of effectively reducing extra noise/area/current consumption.

[0104] FIG. 9 is a first example of a possible circuit implementation of a solution as proposed herein.

[0105] It is again recalled that solutions as proposed herein can be advantageously used in connection with small supply voltages VDD (1.1 V or lower).

[0106] In FIG. 9, the first stage of the OTA of FIG. 4 including the transistors M.sub.0, M.sub.1, M.sub.2, M.sub.3 and M.sub.4 is reproduced (a detailed description is not repeated for brevity) by highlighting the output resistance r.sub.outM.sub.0 of the tail transistor M.sub.0 traversed by a current IC.sub.M.

[0107] It is noted that, while represented as a distinct component for clarity of illustration, the resistance r.sub.outM.sub.0 is in fact an intrinsic parameter of the source-drain current flow path through the transistor M.sub.0.

[0108] The network associated to the first stage of the OTA illustrated in FIG. 9 includes three transistors M.sub.A, M.sub.B, M.sub.C (MOSFET transistors for instance).

[0109] The (diode-connected) transistor M.sub.A and the transistor M.sub.B have their control terminals (gates, in the case of field-effect transistors such as MOSFET transistors) coupled via a resistor R.sub.COMP with a capacitor C.sub.COMP having a first end connected to a node between the resistor R.sub.COMP and the gate of the transistor M.sub.B and a second end connected to the line V.sub.TAIL between the tail transistor M.sub.0 and the mutually connected current flow paths through the transistors M.sub.1 and M.sub.2.

[0110] Both transistors M.sub.A and the transistor M.sub.B have the current flow-paths therethrough coupled (at their sources, for instance) to the supply line/node VDD.

[0111] The (diode-connected) transistor M.sub.A (whose control terminal coupled to the resistor R.sub.COMP is at a voltage V.sub.BIASp) has a bias current I.sub.BIAS flowing therethrough (generated in a manner known per se to those skilled in the art) that serves as a reference current of the circuit.

[0112] The transistor M.sub.B (whose control terminal coupled to the resistor R.sub.COMP is at a voltage V.sub.BIASp_COMP) has a current flow path therethrough cascaded with the current flow path through the (diode connected) transistor M.sub.C.

[0113] The (diode connected) transistor M.sub.C is arranged between the transistor M.sub.B and ground GND and has its control terminal (gate, in the case of a field-effect transistor such as a MOSFET transistor) coupled in a current-mirror arrangement to the control terminal of the tail transistor M.sub.0 via a line at a voltage V.sub.BIASn_COMP.

[0114] The action of the network associated to the first stage of the OTA as illustrated in FIG. 9 in improving the stability of the OCMFB can be explained by considering a common-mode perturbation taking place on the outputs of the amplifier.

[0115] Such a perturbation (labeled V in FIG. 9) is brought to the inputs V.sub.VGp and V.sub.VGn of the OTA through the feedback network (Z.sub.F in FIG. 5, for immediate reference).

[0116] This perturbation results in a common-mode current IC.sub.M:

[00004]$I_{\mathrm{CM}}=V_T/r_{\mathrm{OUT}}{M}_0$

where V.sub.T is the amplitude of the common-mode perturbation that actually reaches the node V.sub.TAIL of the OTA and r.sub.OUTM.sub.0 is the output resistance of the transistor M.sub.0.

[0117] As discussed, this undesired current should be kept as low as possible, which may not be feasible due to the detrimental effect that low-voltage designs have on the resistance r.sub.OUTM.sub.0, especially at PVT corners.

[0118] The circuit of FIG. 9 is exemplary of the possibility of duplicating the network that generates the bias point of the tail current generator M.sub.0 (via the transistors M.sub.A, M.sub.B and M.sub.C) and with the C-R path represented by the capacitance C.sub.COMP and the resistance R.sub.COMP.

[0119] With this path, the perturbation V.sub.T is propagated to (the gate of) the transistor M.sub.B that generates the signal V.sub.C, and the consequent current I.sub.COMP read from the transistor M.sub.C and mirrored into the transistor M.sub.0.

[0120] In response to a judicious sizing of the components R.sub.COMP, C.sub.COMP and M.sub.B, the current I.sub.COMP gives in return an AC cancellation of the current IC.sub.M thus reducing, in AC operation, the common-mode gain G.sub.CM of the operational amplifier.

[0121] This was found to result in a marked improvement of the OCMFB phase margin and transient response both in the corners TYP 27 C. and SSA 40 C.

[0122] FIG. 10A again recalls a base 2-stage OTA structure showing the possible arrangement of the transistors M.sub.A, M.sub.B, and M.sub.C in combination with conventional OTA circuitry as represented in FIG. 4 (with the C-R network not yet included).

[0123] A general concept underlying the solutions of FIGS. 10A, 11A and 12A (and FIG. 9 as well) is the provision of a differential input stage including a first input transistor M.sub.1 and a second input transistor M.sub.2 having control terminals configured to receive a differential input signal V.sub.Gp, V.sub.Gn applied therebetween as well as a tail transistor M.sub.0.

[0124] As illustrated, the first input transistor M.sub.1 has a current flow path therethrough coupled between a common current flow path through the tail transistor M.sub.0 and the (first) node A while the second input transistor M.sub.2 has a current flow path therethrough coupled between the common current flow path through the tail transistor M.sub.0 and the (second) node B.

[0125] The solutions of FIGS. 10A, 11A and 12A (and FIG. 9 as well) also include an output stage including a first output transistor M.sub.5 and a second output transistor M.sub.6.

[0126] As illustrated, the first output transistor M.sub.5 has a current flow path therethrough between the supply line VDD and a first output node V.sub.OUTp that is coupled (via a capacitor C.sub.C) to the node A in the differential input stage and the second output transistor M.sub.6 has a current flow path therethrough between the supply line VDD and a second output node V.sub.OUTn that is coupled (again via a capacitor C.sub.C) to the node B in the differential input stage.

[0127] The solutions as illustrated further include common-mode control circuitry comprising a first input transistor M.sub.CM1 and a second input transistor M.sub.CM2 having current flow paths therethrough jointly coupled to a ground current flow path through a tail bias transistor M.sub.CM0: the first common-mode control transistor M.sub.CM1 has a control terminal coupled resistively (via the resistors R.sub.CM) to the first output node V.sub.OUTp and to the second output node V.sub.OUTn in the differential output stage.

[0128] Additionally, these solutions include a bias generation circuitry that comprises a bias duplicate transistor (this may be any of the transistors M.sub.C, M.sub.D1, or M.sub.E, depending on the embodiment considered) having a current flow path therethrough arranged in a current flow line (this may be through M.sub.B, M.sub.C, through M.sub.D, M.sub.D1 or through M.sub.D, M.sub.COMP1, M.sub.DCOMP2, M.sub.E depending on the embodiment considered) between the supply line VDD and ground GND with the bias duplicate transistor M.sub.C, M.sub.D1 or M.sub.E coupled in a (1:N, for instance) current mirror arrangement with the tail transistor M.sub.0 in the differential input stage.

[0129] Advantageously, such a differential input stage may include a third (load) transistor M.sub.3 and a fourth (load) transistor M.sub.4.

[0130] The current flow path through the first input transistor M.sub.1 may thus be configured to be coupled to the supply line VDD at the node A via a current flow path through the third transistor M.sub.3 with the first input transistor M.sub.1 intermediate the third transistor M.sub.3 and the tail transistor M.sub.0 and the current flow path through the second input transistor (M.sub.2) may be likewise configured to be coupled to the supply line VDD at the node B via a current flow path through the fourth transistor M.sub.4 with the second input transistor M.sub.2 intermediate the fourth transistor M.sub.4 and the tail transistor M.sub.0.

[0131] As illustrated, the third transistor M.sub.3 and the fourth transistor M.sub.4 may have control terminals mutually coupled via a control line V.sub.CTRL.

[0132] Still advantageously, the differential output stage may include a third output (load) transistor (the transistor M.sub.7) with a current flow path therethrough between the first output node V.sub.OUTp and ground GND as well as a fourth output (load) transistor (the transistor M.sub.8) with a current flow path therethrough between the second output node V.sub.OUTn and ground GND.

[0133] As illustrated, the current flow path though the first common-mode control transistor M.sub.CM1 is configured to be coupled to the supply line VDD via a current flow path through a third common-mode control transistor M.sub.CM3 having a control terminal coupled to the control line V.sub.CTRL between the control terminals of the third transistor M.sub.3 and the fourth transistor M.sub.4 in the differential input stage with the first common-mode control transistor M.sub.CM1 intermediate the third common-mode control transistor M.sub.CM3 and the bias tail transistor M.sub.CM0 and the current flow path through the second common-mode control transistor M.sub.CM2 configured to be coupled to the supply line VDD via a current flow path through a fourth common-mode control transistor M.sub.CM4 with the second common-mode control transistor M.sub.CM2 intermediate the fourth common-mode control transistor M.sub.CM4 and the common-mode control tail transistor M.sub.CM0.

[0134] FIGS. 11A and 12A introduce possible circuit implementations of solutions as described herein with and without the C-R network C.sub.COMP, R.sub.COMP added.

[0135] Respective equivalent common-mode models for architectures illustrated in FIGS. 10A, 11A and 12A are reproduced in FIGS. 10B, 11B and 12B.

[0136] Throughout FIGS. 10A, 10B, 11A, 11B, 10C, 11C parts/elements/entities already introduced in connection with the previous figures are indicated with the same reference symbols and a detailed description will not be repeated for brevity.

[0137] In FIG. 10A, the transistors M.sub.A (diode connected) and M.sub.B are shown with their gates mutually coupled with the source-drain current flow lines through the transistors M.sub.B are M.sub.C cascaded in a current flow line between the supply node/line VDD and ground GND. In this case the transistor M.sub.C is shown coupled to the tail transistor M.sub.0 in a 1:N current mirror arrangement (the same representation is adopted in FIGS. 10A, 11A, and 12A to indicate the associated form factors, namely 1 and N).

[0138] In the equivalent common-mode model of FIG. 10B,

[00005]$V_{\mathrm{GM}\_\mathrm{CM}}=\left(V_{\mathrm{VGp}}+V_{\mathrm{VGn}}\right)/2$$V_{\mathrm{OUT}\_\mathrm{CM}}=\left(V_{\mathrm{OUTp}}+V_{\mathrm{OUTn}}\right)/2$ [0139] gmM.sub.x is the transconductance of the transistor M.sub.x [0140] r.sub.outM.sub.x is the output resistance of the transistor M.sub.x [0141] and

[00006]${\mathrm{GM}}_{\mathrm{CM}1}=1/2r_{\mathrm{OUT}}{M}_0$$R1r_{\mathrm{OUT}}{M}_{3/4}$${\mathrm{GM}}_{\mathrm{CM}2}=g_m{M}_5$$R2=r_{\mathrm{OUT}}{M}_{5/6}||r_{\mathrm{OUT}}{M}_{7/8}$${GM}_{\mathrm{CM}3}=g_m{M}_{CM1}.Math.g_m{M}_{3/4}/2g_m{M}_{CM3}.$

[0142] In the implementation of FIG. 11A, the C-R network including the resistor R.sub.COMP and the capacitor C.sub.COMP (coupled to the tail node or line V.sub.TAIL) is not coupled between the gates of the transistors M.sub.A and M.sub.B as exemplified in FIG. 9 but rather between: the mutually coupled gates of the transistors M.sub.A, M.sub.B, and the gate of a transistor M.sub.D having the current flow path therethrough cascaded at a node Q with the current flow path through a transistor M.sub.D1 in a current flow line between the supply node/line VDD and ground GND.

[0143] The control terminal (gate in the case of a field-effect transistor such as a MOSFET transistor) of the transistor M.sub.D1 has applied thereto a bias voltage V.sub.BIASn2.

[0144] The voltages V.sub.BIASn and V.sub.BIASn2 have the same DC value, but the node V.sub.BIASn2 is coupled to the node V.sub.TAIL through the capacitance C.sub.COMP making the cascade of the transistor M.sub.D and M.sub.D2 a compensation current flow line.

[0145] In the equivalent common-mode model of FIG. 11B,

[00007]$V_{\mathrm{VG}\_\mathrm{CM}}=\left(V_{\mathrm{VGp}}+V_{\mathrm{VGn}}\right)/2$$V_{\mathrm{OUT}\_\mathrm{CM}}=\left(V_{\mathrm{OUTp}}+V_{\mathrm{OUTn}}\right)/2$ [0146] gmM.sub.x is the transconductance of the transistor M.sub.x [0147] r.sub.outM.sub.x is the output resistance of the transistor M.sub.x [0148] C.sub.gM.sub.x is the gate capacitance of the transistor M.sub.x [0149] and

[00008]${\mathrm{GM}}_{\mathrm{CM}1}=1/2r_{\mathrm{OUT}}{M}_0$$R1r_{\mathrm{OUT}}{M}_{3/4}$${\mathrm{GM}}_{\mathrm{CM}2}=g_m{M}_5$$R2=r_{\mathrm{OUT}}{M}_{5/6}||r_{\mathrm{OUT}}{M}_{7/8}$${GM}_{\mathrm{CM}3}=g_m{M}_{CM1}.Math.g_m{M}_{3/4}/2g_m{M}_{CM3}.$$\mathrm{Also}:$${\mathrm{GM}}_{\mathrm{COMP}}=G_m{M}_D.Math.C_{\mathrm{COMP}}/\left(C_{\mathrm{COMP}}+C_g{M}_D\right).Math.N$

where N is the current mirror factor of the 1:N current mirror arrangement coupling the transistor M.sub.C to the tail transistor M.sub.0.

[0150] This solution was found to operate adequately for frequencies higher than f.sub.COM=1/(2R.sub.COMP.Math.(C.sub.COMP+C.sub.gM.sub.D)), namely for a common-mode-feedback bandwidth higher than f.sub.COMP.

[0151] In the implementation of FIG. 12A (seen in comparison with the implementation of FIG. 11A) the C-R network including the resistor R.sub.COMP and the capacitor C.sub.COMP is no longer provided and the transistor M.sub.D1 having the current flow path therethrough cascaded with the current flow path through the transistor M.sub.D (having the gate coupled to the mutually coupled gates of the transistors M.sub.A, M.sub.B) is replaced by the cascaded arrangement (between the node Q and ground GND) of: a complementary transistor pair M.sub.COMP1, M.sub.COMP2, and a transistor M.sub.E having the current path therethrough configured to receive the current from the parallel connection of the current paths through the transistors M.sub.COMP1, M.sub.COMP2 that receive the signals V.sub.VGp and V.sub.VGn at their control terminals (gates, in the case of field-effect transistors such as MOSFET transistors).

[0152] In the implementation of FIG. 12A, the signal V.sub.BIASn2 is applied both to the node Q between the transistor M.sub.D and the transistors M.sub.COMP1, M.sub.COMP2 and to the control terminal (gate, in the case of a field-effect transistor such as a MOSFET transistor) of the transistor M.sub.E, which exhibits an output resistance equal to N.Math.r.sub.outM.sub.0, where N is the current mirror factor of the 1:N current mirror arrangement coupling the transistor M.sub.E to the tail transistor M.sub.0.

[0153] In the equivalent common-mode model of FIG. 12B,

[00009]$V_{\mathrm{VG}\_\mathrm{CM}}=\left(V_{\mathrm{VGp}}+V_{\mathrm{VGn}}\right)/2$$V_{\mathrm{OUT}\_\mathrm{CM}}=\left(V_{\mathrm{OUTp}}+V_{\mathrm{OUTn}}\right)/2$ [0154] gmM.sub.x is the transconductance of the transistor M.sub.x [0155] r.sub.outM.sub.x is the output resistance of the transistor M.sub.x [0156] and

[00010]${\mathrm{GM}}_{\mathrm{CM}1}=1/2r_{\mathrm{OUT}}{M}_0$$R1r_{\mathrm{OUT}}{M}_{3/4}$${\mathrm{GM}}_{\mathrm{CM}2}=g_m{M}_5$$R2=r_{\mathrm{OUT}}{M}_{5/6}||r_{\mathrm{OUT}}{M}_{7/8}$${GM}_{\mathrm{CM}3}=g_m{M}_{CM1}.Math.g_m{M}_{3/4}/2g_m{M}_{CM3}.$$\mathrm{Also}:$${\mathrm{GM}}_{\mathrm{COMP}}=N/\left(N.Math.r_{\mathrm{OUT}}{M}_0\right)={\mathrm{GM}}_{\mathrm{CM}1}$

[0157] The solution of FIG. 12A with the additional stage including the transistors labelled M.sub.COMP1/2 and M.sub.E was found to be effective also for DC conditions.

[0158] It is observed that a given current mirror factor/ratio 1:N of the transistors M.sub.E and M.sub.0, it is advantageous to preserve the same ratio 1:N between the MOS transistors M.sub.COMP1/2 and M.sub.1/2.

[0159] The ratio in question refers to the form factor of the transistors. For instance, N=10 means that M.sub.0 is ten times more conductive than M.sub.E (which may be achieved also by including in M.sub.0 ten elementary modules equal to M.sub.E).

[0160] To summarize, in all of the solutions of FIGS. 10A, 11A and 12A (and FIG. 9 as well) a current flow line (through the transistors M.sub.B, M.sub.C or through the transistors M.sub.D, M.sub.D1 or through the transistors M.sub.D, M.sub.COMP1, M.sub.DCOMP2, M.sub.E) can be provided between the supply line VDD and ground GND that comprises the cascaded connection of the current flow path through the bias duplicate transistor (that is the transistor M.sub.C, the transistor M.sub.D1 or the transistor M.sub.E) and the current flow path through a cascaded bias transistor (this may be the transistor M.sub.B or the transistor M.sub.D, with the parallel connection of the transistors M.sub.COMP1, M.sub.COMP2 possibly in turn cascaded thereto) with such a cascaded bias transistor arranged between the supply line (VDD) and the bias duplicate transistor M.sub.C, M.sub.D1 or M.sub.E.

[0161] In all of the solutions of FIGS. 10A, 11A and 12A (and FIG. 9 as well) a further bias transistor (namely, the transistor M.sub.A) is provided having a flow path therethrough for a bias current I.sub.BIAS that is coupled to the supply line VDD and a control terminal coupled to a control terminal of the cascaded bias transistor: this may be either the transistor M.sub.B (in FIGS. 9 and 10A) of the transistors M.sub.D (in FIGS. 11A and 12A).

[0162] In the case of FIG. 11A, the control terminal of the further bias transistor M.sub.A is coupled both to the control terminal of the cascade bias transistor M.sub.D and to a control terminal of another bias transistor M.sub.B having a current flow path therethrough cascaded with the current flow path through another bias duplicate transistor M.sub.C in a current flow line between the supply line VDD and ground GND.

[0163] As exemplified in FIGS. 10A and 12A, the control terminal of the further bias transistor M.sub.A is directly coupled to the control terminal of the cascaded bias transistor (namely the transistor M.sub.B or the transistor M.sub.D).

[0164] Conversely, as exemplified in FIGS. 9 and 11A, the control terminal of the further bias transistor M.sub.A can be coupled to the control terminal of the cascaded bias transistor (the transistor M.sub.B or the transistor M.sub.D) via a resistor R.sub.COMP in an RC network; such an RC network comprises a capacitor C.sub.COMP coupled between the control terminal of the cascaded bias transistor (the transistor M.sub.B or the transistor M.sub.D) and the common current flow path through the tail transistor M.sub.0.

[0165] As exemplified in FIG. 12A, the bias current flow line between the supply line VDD and ground GND comprises a complementary pair of transistors (namely the transistors M.sub.COMP1 and M.sub.COMP2) having current flow paths therethrough arranged in parallel between the current flow path through the bias duplicate transistor (here M.sub.E) and the current flow path through the cascaded bias transistor M.sub.D; these transistors in the complementary pair M.sub.COMP1, M.sub.COMP2 have control terminals configured to receive applied therebetween the differential input signal V.sub.Gp, V.sub.Gn.

[0166] Once again it is noted that solutions as described herein are suited to operate with small supply voltages (supply line VDD) up to 1.1 V, namely 1.1 V or lower.

[0167] Advantageously, at least the tail transistor (M.sub.0) in the differential input stage and the bias duplicate transistor (be it any of the transistors M.sub.C, M.sub.D1, or M.sub.E) depending on the embodiments include PMOS transistors.

[0168] However, at least some of the field-effect transistors (MOSFET transistors) illustrated herein can be replaced by bipolar junction transistor (BJT), where the control terminals will be the bases of these transistors and the current paths therethrough will be represented by the emitter-collector current flow path.

[0169] The figures and the relative description are illustrative of implementations where VDD is assumed to be a positive voltage, with the polarities of the transistors (p-channel/n-channel and p-n-p/n-p-n) selected correspondingly. Those of skill in the art can easily devise corresponding adaptations in case of different voltage/polarity options.

[0170] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0171] The claims are an integral part of the disclosure provided herein in respect of the embodiments.

[0172] The extent of protection is determined by the annexed claims.