Calibrating device for digital-to-analog conversion

Abstract

A calibrating device can mitigate the static mismatch error of a digital-to-analog converter (DAC), and includes a digital code generating circuit, the DAC, an analog-to-digital converter (ADC), a filter circuit, an indicating circuit, and a statistical circuit. The digital code generating circuit generates a digital code of N digital codes. The DAC generates an analog signal corresponding to one of N signal levels according to the digital code. The ADC generates a digital signal according to the analog signal. The filter circuit generates a gradient value according to the difference between the digital code and the digital signal. The indicating circuit generates a selection signal according to the digital code. The statistical circuit learns from the selection signal that the gradient value is corresponding to a K.sup.th digital code of the N digital codes, and determines whether the K.sup.th digital code should be adjusted according to the gradient value.

Claims

1. A calibrating device for digital-to-analog conversion, the calibrating device being capable of mitigating a static mismatch error of a local digital-to-analog converter (DAC), the calibrating device comprising: a digital code generating circuit configured to generate a digital code, wherein the digital code is one of N digital codes, N initial values of the N digital codes are inconsecutive digital values, and the N is an integer greater than one; a DAC configured to generate an analog signal according to the digital code, wherein the DAC is the local DAC and the analog signal is corresponding to one of N signal levels; an analog-to-digital converter (ADC) configured to generate a digital signal according to the analog signal; a filter circuit coupled to the digital code generating circuit and the ADC, and configured to generate a gradient value according to a difference between the digital code and the digital signal, wherein the difference correlates with the static mismatch error of the DAC; an indicating circuit configured to generate a selection signal according to the digital code; and a statistical circuit configured to learn from the selection signal that the gradient value is a K.sup.th gradient value corresponding to a K.sup.th digital code of the N digital codes, and configured to determine whether to request the digital code generating circuit to adjust the K.sup.th digital code according to the K.sup.th gradient value, wherein the K is a positive integer not greater than the N.

2. The calibrating device of claim 1, wherein the N digital codes are N values of M consecutive digital values, the M is an integer not less than 2.sup.X, the X is an integer not less than three, the N is not less than 2.sup.Y, and the Y is a positive integer not greater than (X−2).

3. The calibrating device of claim 1, wherein an N.sup.th digital code of the N digital codes and a first digital code of the N digital codes are fixed, the N.sup.th digital code is a maximum digital code among the N digital codes, the first digital code is a minimum digital code among the N digital cods, and the K is less than the N but greater than one.

4. The calibrating device of claim 1, wherein the N initial values are at regular intervals.

5. The calibrating device of claim 1, wherein the filter circuit applies a Least Mean Squares (LMS) algorithm.

6. The calibrating device of claim 1, wherein the filter circuit includes: an echo canceler configured to generate a cancellation signal according to the digital code; an error signal generating circuit configured generate an error signal according to the cancellation signal and the digital signal; and a filter configured to generate the gradient value according to the error signal.

7. The calibrating device of claim 6, wherein the echo canceler is another filter, and coefficients of the filter is a mirror image of coefficients of the another filter.

8. The calibrating device of claim 1, wherein the indicating circuit includes a delay circuit, and a first delay amount caused by the delay circuit is equal to a second delay amount caused by the filter circuit.

9. The calibrating device of claim 1, wherein the statistical circuit updates a K.sup.th accumulated gradient value according to the K.sup.th gradient value, and then determines whether the K.sup.th accumulated gradient value is greater than a K.sup.th positive threshold value or less than a K.sup.th negative threshold value; and when the K.sup.th accumulated gradient value is greater than the K.sup.th positive threshold value or less than the K.sup.th negative threshold value, the statistical circuit requests the digital code generating circuit to adjust the K.sup.th digital code and to reset the K.sup.th accumulated gradient value or update the K.sup.th positive threshold value and the K.sup.th negative threshold value.

10. The calibrating device of claim 9, wherein the statistical circuit subtracts a product from a current value of the K.sup.th accumulated gradient value to update the K.sup.th accumulated gradient value, and the product is equal to a coefficient multiplied by the K.sup.th gradient value.

11. The calibrating device of claim 9, wherein when the K.sup.th accumulated gradient value is greater than the K.sup.th positive threshold value, the statistical circuit requests the digital code generating circuit to decrease the K.sup.th digital code.

12. The calibrating device of claim 11, wherein the digital code generating circuit subtracts one from a current value of the K.sup.th digital code and thereby decreases the K.sup.th digital code.

13. The calibrating device of claim 9, wherein when the K.sup.th accumulated gradient value is less than the K.sup.th negative threshold value, the statistical circuit requests the digital code generating circuit to increase the K.sup.th digital code.

14. The calibrating device of claim 13, wherein the digital code generating circuit adds up a current value of the K.sup.th digital code and one and thereby increases the K.sup.th digital code.

15. The calibrating device of claim 9, wherein the statistical circuit resets the K.sup.th accumulated gradient value and thereby makes the K.sup.th accumulated gradient value be zero.

16. The calibrating device of claim 9, wherein the statistical circuit adds a K.sup.th initial value to each of the K.sup.th positive threshold value and the K.sup.th negative threshold value or subtracts the K.sup.th initial value from each of the K.sup.th positive threshold value and the K.sup.th negative threshold value, and thereby updates the K.sup.th positive threshold value and the K.sup.th negative threshold value.

17. The calibrating device of claim 1, wherein in a circumstance that the K.sup.th digital code is adjusted to be a certain value most frequently or stays at the certain value for longest time in a predetermined period of time, the statistical circuit requests the digital code generating circuit to make the K.sup.th digital code be the certain value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 shows a calibrating device for digital-to-analog conversion according to an embodiment of the present disclosure.

[0007] FIG. 2 shows an embodiment of the filter circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present specification discloses a calibrating device for digital-to-analog conversion. The calibrating device is capable of mitigating the static mismatch error of a local digital-to-analog converter (DAC). The static mismatch error means that: although the level of an output signal of the local DAC is supposed to be equal to a predetermined signal level ideally, the level of the output signal is actually equal to the predetermined signal level plus an unwanted offset due to the variation in a process, voltage, or temperature, which may bring a far-end signal receiving device difficulty in determining the level of the output signal accurately. The calibrating device of the present disclosure can be applied to a signal transmission device such as a 2.5GBase-T Ethernet device, and the signal transmission device is coupled to the above-mentioned far-end signal receiving device in a wired manner.

[0009] FIG. 1 shows an embodiment of the calibrating device of the present disclosure. As shown in FIG. 1, the calibration operation of the calibrating device 100 is a close loop operation. The calibrating device 100 includes a digital code generating circuit 110, a DAC 120, an analog-to-digital converter (ADC) 130, a filter circuit 140, an indicating circuit 150, and a statistical circuit 160. These circuits are described in detail in the following paragraphs.

[0010] In regard to the embodiment of FIG. 1, the digital code generating circuit 110 is configured to generate a digital code Code#, wherein the digital code Code# is one of N digital codes, each of the N digital codes is an initial value in the beginning of the calibration operation, the N initial values of the N digital codes are inconsecutive digital values, and the N is an integer greater than one. For example, the N digital codes are N values of M consecutive digital values, the M is an integer not less than 2.sup.X (e.g., 2.sup.8), the X is an integer not less than three, the N is not less than 2.sup.Y (e.g., 2.sup.4), and the Y is a positive integer not greater than (X−2); in brief, the N digital codes are a small part of the M consecutive digital values in this example. For example, the N initial values are at regular intervals. For example, the N is 17, the N digital codes are Code#1, Code#2, . . . , Code#16, and Code#17, the M is 256, the M consecutive digital values are 0, 1, 2, . . . , 254, and 255, and the interval between any two adjacent values of the N initial values is 15, the minimum value of the N initial values is 9, and accordingly the N initial values are as follows: Code#1=009, Code#2=024, Code#3=039, . . . , Code#16=234, and Code#17=249.

[0011] In regard to the embodiment of FIG. 1, the DAC 120 is configured to generate an analog signal S.sub.A according to the digital code Code#, wherein the DAC 120 is the aforementioned local DAC. The analog signal S.sub.A is corresponding to one of N signal levels (e.g., voltage levels), and the N signal levels are corresponding to the N digital codes respectively. For example, the N digital codes are N values of M consecutive digital values, the M is equal to 2.sup.X (e.g., 2.sup.8), and the DAC 120 is a X-bits DAC (e.g., 8-bits DAC). The DAC 120 itself is a known/self-developed circuit, and its detail is beyond the scope of the present disclosure.

[0012] In regard to the embodiment of FIG. 1, the ADC 130 is configured to generate a digital signal S.sub.D according to the analog signal S.sub.A. The ADC 130 itself is a known/self-developed circuit, and its detail is beyond the scope of the present disclosure.

[0013] In regard to the embodiment of FIG. 1, the filter circuit 140 is coupled to the digital code generating circuit 110 and the ADC 130, and configured to generate a gradient value S.sub.G according to a difference between the digital code Code# and the digital signal S.sub.D, wherein the difference correlates with the static mismatch error of the DAC 120. For example, the filter circuit 140 applies a Least Mean Squares (LMS) algorithm to generate the LMS value (i.e., the gradient value S.sub.G) of an error signal S.sub.ERR as mentioned in a later paragraph. The LMS algorithm is known in this technical field, and its detail is beyond the scope of the present disclosure.

[0014] FIG. 2 shows an embodiment of the filter circuit 140, and this embodiment includes an echo canceler 210, an error signal generating circuit 220, and a filter 230. The echo canceler 210 is configured to generate a cancellation signal S.sub.CXL, according to the digital code Code#. The error signal generating circuit 220 (e.g., adder or subtractor) is configured generate an error signal S.sub.ERR according to the cancellation signal S.sub.CXL and the digital signal S.sub.D. The filter 230 is configured to generate the aforementioned gradient value S.sub.G according to the error signal S.sub.ERR. An embodiment of the echo canceler 210 is a specific filter, and the coefficients (e.g., [0 1 0 01]) of the filter 230 is a mirror image of the coefficients (e.g., [0 0 1 01]) of the specific filter. Each of the echo canceler 210, the error signal generating circuit 220, and the filter 230 alone is a known/self-developed circuit, and its detail is beyond the scope of the present disclosure.

[0015] In regard to the embodiment of FIG. 1, the indicating circuit 150 is configured to generate a selection signal S.sub.SEL according to the digital code Code#. The selection signal S.sub.SEL indicates that the digital code Code# is a certain digital code of the N digital codes. For example, the indicating circuit 150 includes a delay circuit (not shown); the delay circuit delays the transmission of the digital code Code# and thereby generate a delayed digital code as the selection signal S.sub.SEL; and the delay amount caused by the delay circuit is equal to the delay amount caused by the filter circuit 140; in brief, the indicating circuit 150 here is for notifying the statistical circuit 160 that the gradient value S.sub.G is corresponding to which digital code. The indicating circuit 150 itself is a known/self-developed circuit, and its detail is beyond the scope of the present disclosure. It is noted that the indicating circuit 150 can be included in the digital code generating circuit 110, or be set outside the digital code generating circuit 110.

[0016] In regard to the embodiment of FIG. 1, the statistical circuit 160 is configured to learn from the selection signal S.sub.SEL that the gradient value S.sub.G is a K.sup.th gradient value corresponding to a K.sup.th digital code of the N digital codes, and configured to determine whether to request the digital code generating circuit 110 to adjust the K.sup.th digital code according to the K.sup.th gradient value, wherein the K is a positive integer not greater than the N. It is noted that the statistical circuit 160 can be included in the digital code generating circuit 110 or be set outside the digital code generating circuit 110.

[0017] On the basis of the above description, in an exemplary implementation the statistical circuit 160 updates a K.sup.th accumulated gradient value (GradAcc#K) according to the K.sup.th gradient value (Grad#K), and then determines whether the K.sup.th accumulated gradient value is greater than a K.sup.th positive threshold value (+THD#K) or less than a K.sup.th negative threshold value (−THD#K), wherein the K.sup.th accumulated gradient value and the K.sup.th gradient value in the beginning of the calibration operation are the same or in a predetermined relation, and each gradient value is assigned an accumulated gradient value, a positive threshold value, and a negative threshold value for the calibration operation; and when the K.sup.th accumulated gradient value is greater than the K.sup.th positive threshold value or less than the K.sup.th negative threshold value, the statistical circuit 160 requests the digital code generating circuit 110 to adjust the K.sup.th digital code and requests the digital code generating circuit 110 to reset the K.sup.th accumulated gradient value or update both the K.sup.th positive threshold value and the K.sup.th negative threshold value. It is noted that the absolute value of the K.sup.th positive threshold value can be equal to the absolute value of the K.sup.th negative threshold value, but the present invention is not limited thereto. It is also noted that all positive threshold values (i.e., +THD#1˜+THD#N) can be the same and all negative threshold values (i.e., −THD#1˜−THD#N) can be the same, but the present invention is not limited thereto.

[0018] In an exemplary implementation, every time the K.sup.th gradient value (Grad#K) is updated, the statistical circuit 160 subtracts a product from a current value of the K.sup.th accumulated gradient value (GradAcc#K) to update the K.sup.th accumulated gradient value, wherein the product is equal to a coefficient (Mu) (e.g.,)2.sup.−10) multiplied by the K.sup.th gradient value (Grad#K). The above calculation can be expressed as follows:

GradAcc#K=GradAcc#K−Mu×Grad#K  (eq. 1)

[0019] In an exemplary implementation, when the K.sup.th accumulated gradient value (GradAcc#K) is greater than the K.sup.th positive threshold value, this implies that the K.sup.th digital code (Code#K) becomes excessively large as time goes by; accordingly, the statistical circuit 160 requests the digital code generating circuit 110 to decrease the K.sup.th digital code and requests the digital code generating circuit 110 to reset the K.sup.th accumulated gradient value or update both the K.sup.th positive threshold value and the K.sup.th negative threshold value. For example, the digital code generating circuit 110 subtracts one from a current value of the K.sup.th digital code and thereby decreases the K.sup.th digital code, which can be expressed as follows:

GradAcc#K≥+THD#K.fwdarw.Code#K=Code#K−1  (eq. 2)

[0020] In an exemplary implementation, when the K.sup.th accumulated gradient value (GradAcc#K) is less than the K.sup.th negative threshold value, this implies that the K.sup.th digital code (Code#K) becomes excessively small as time goes by; accordingly, the statistical circuit 160 requests the digital code generating circuit 110 to increase the K.sup.th digital code and requests the digital code generating circuit 110 to reset the K.sup.th accumulated gradient value or update both the K.sup.th positive threshold value and the K.sup.th negative threshold value. For example, the digital code generating circuit 110 adds up a current value of the K.sup.th digital code and one and thereby increases the K.sup.th digital code, which can be expressed as follows:

GradAcc#K≤−THD#K.fwdarw.Code#K=Code#K+1  (eq. 3)

[0021] In an exemplary implementation, after the adjustment of the K.sup.th digital code, the statistical circuit 160 resets the K.sup.th accumulated gradient value (GradAcc#K) and thereby makes the K.sup.th accumulated gradient value be zero or a predetermined value. In an exemplary implementation, after the adjustment of the K.sup.th digital code, the statistical circuit 160 adds a K.sup.th initial threshold value (e.g., |+THD#K|) to each of the K.sup.th positive threshold value and the K.sup.th negative threshold value in response to the increase in the K.sup.th digital code or subtracts the K.sup.th initial threshold value from each of the K.sup.th positive threshold value and the K.sup.th negative threshold value in response to the decrease in the K.sup.th digital code, and thereby updates the K.sup.th positive threshold value (e.g., +THD#K+(+THD#K)=+2THD#K, or +THD#K−(+THD#K)=0) and updates the K.sup.th negative threshold value (e.g., −THD#K+(+THD#K)=0, or −THD#K−(+THD#K)=−2THD#K).

[0022] It is noted that the output of the DAC 120, that is to say the input of the ADC 130, and the output of the filter circuit 140 may interact with each other and change interdependently, which may lead to the overflow of hardware. In an exemplary implementation, at least two of the N digital codes (e.g., the N.sup.th digital code (i.e., the maximum digital code) of the N digital codes and the 1.sup.st digital code (i.e., the minimum digital code) of the N digital codes) are fixed, and this makes an anchoring effect and prevents the overflow of hardware. In this exemplary implementation, the K is less than the N but greater than one.

[0023] In an exemplary implementation, the N digital codes are 17 values among 256 consecutive digital values. Each of the 17 digital codes (Code#1˜Code#17) is an initial value in the beginning of the calibration operation, and the 17 initial values of the 17 digital codes are 009, 024, 039, 054, 069, 084, 099, 114, 129, 144, 159, 174, 189, 204, 219, 234, 249 in order, wherein the 1.sup.st digital code (i.e., 009) and the 17.sup.th digital code (i.e., 249) remain unchanged to achieve the aforementioned anchoring effect. Table 1 shows the 17 digital codes and the way to adjust the 17 digital codes, wherein THD denotes the aforementioned positive threshold value and −THD denotes the aforementioned negative threshold value.

TABLE-US-00001 TABLE 1 17 digital codes the way to adjust digital codes Code#17 fixed Code#16 if GradAcc#16 ≥ +THD .fwdarw. Code#16 = Code#16 − 1 .fwdarw. reset GradAcc#16 if GradAcc#16 ≤ −THD .fwdarw. Code#16 = Code#16 + 1 .fwdarw. reset GradAcc#16 Code#15 if GradAcc#15 ≥ +THD .fwdarw. Code#15 = Code#15 − 1 .fwdarw. reset GradAcc#15 if GradAcc#15 ≤ −THD .fwdarw. Code#15 = Code#15 + 1 .fwdarw. reset GradAcc#15 Code#14 if GradAcc#14 ≥ +THD .fwdarw. Code#14 = Code#14 − 1 .fwdarw. reset GradAcc#14 if GradAcc#14 ≤ −THD .fwdarw. Code#14 = Code#14 + 1 .fwdarw. reset GradAcc#14 Code#13 if GradAcc#13 ≥ +THD .fwdarw. Code#13 = Code#13 − 1 .fwdarw. reset GradAcc#13 if GradAcc#13 ≤ −THD .fwdarw. Code#13 = Code#13 + 1 .fwdarw. reset GradAcc#13 Code#12 if GradAcc#12 ≥ +THD .fwdarw. Code#12 = Code#12 − 1 .fwdarw. reset GradAcc#12 if GradAcc#12 ≤ −THD .fwdarw. Code#12 = Code#12 + 1 .fwdarw. reset GradAcc#12 Code#11 if GradAcc#11 ≥ +THD .fwdarw. Code#11 = Code#11 − 1 .fwdarw. reset GradAcc#11 if GradAcc#11 ≤ −THD .fwdarw. Code#11 = Code#11 + 1 .fwdarw. reset GradAcc#11 Code#10 if GradAcc#10 ≥ +THD .fwdarw. Code#10 = Code#10 − 1 .fwdarw. reset GradAcc#10 if GradAcc#10 ≤ −THD .fwdarw. Code#10 = Code#10 + 1 .fwdarw. reset GradAcc#10 Code#9 if GradAcc#09 ≥ +THD .fwdarw. Code#09 = Code#09 − 1 .fwdarw. reset GradAcc#09 if GradAcc#09 ≤ −THD .fwdarw. Code#09 = Code#09 + 1 .fwdarw. reset GradAcc#09 Code#8 if GradAcc#08 ≥ +THD .fwdarw. Code#08 = Code#08 − 1 .fwdarw. reset GradAcc#08 if GradAcc#08 ≤ −THD .fwdarw. Code#08 = Code#08 + 1 .fwdarw. reset GradAcc#08 Code#7 if GradAcc#07 ≥ +THD .fwdarw. Code#07 = Code#07 − 1 .fwdarw. reset GradAcc#07 if GradAcc#07 ≤ −THD .fwdarw. Code#07 = Code#07 + 1 .fwdarw. reset GradAcc#07 Code#6 if GradAcc#06 ≥ +THD .fwdarw. Code#06 = Code#06 − 1 .fwdarw. reset GradAcc#06 if GradAcc#06 ≤ −THD .fwdarw. Code#06 = Code#06 + 1 .fwdarw. reset GradAcc#06 Code#5 if GradAcc#05 ≥ +THD .fwdarw. Code#05 = Code#05 − 1 .fwdarw. reset GradAcc#05 if GradAcc#05 ≤ −THD .fwdarw. Code#05 = Code#05 + 1 .fwdarw. reset GradAcc#05 Code#4 if GradAcc#04 ≥ +THD .fwdarw. Code#04 = Code#04 − 1 .fwdarw. reset GradAcc#04 if GradAcc#04 ≤ −THD .fwdarw. Code#04 = Code#04 + 1 .fwdarw. reset GradAcc#04 Code#3 if GradAcc#03 ≥ +THD .fwdarw. Code#03 = Code#03 − 1 .fwdarw. reset GradAcc#03 if GradAcc#03 ≤ −THD .fwdarw. Code#03 = Code#03 + 1 .fwdarw. reset GradAcc#03 Code#2 if GradAcc#02 ≥ +THD .fwdarw. Code#02 = Code#02 − 1 .fwdarw. reset GradAcc#02 if GradAcc#02 ≤ −THD .fwdarw. Code#02 = Code#02 + 1 .fwdarw. reset GradAcc#02 Code#1 fixed

[0024] In an exemplary implementation, if the aforementioned K.sup.th digital code is adjusted to be a certain value most frequently or stays at the certain value for longest time in a predetermined period of time, the statistical circuit 160 requests the digital code generating circuit 110 to make the K.sup.th digital code be the certain value and stop/suspend updating the K.sup.th digital code. In this way, all of the N digital codes can be adjusted appropriately.

[0025] It should be noted that people of ordinary skill in the art can selectively use some or all of the features of any embodiment in this specification or selectively use some or all of the features of multiple embodiments in this specification to implement the present invention as long as such implementation is practicable; in other words, the present invention can be carried out flexibly in accordance with the present disclosure.

[0026] To sum up, the calibrating device of the present disclosure can mitigate the static mismatch error of a local DAC.

[0027] The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.