Cascode arrangement and semiconductor module

Abstract

A cascade arrangement and to a semiconductor module. The cascode arrangement includes: a substrate, a JFET, a MOSFET, and at least one sensor system. A drain terminal of the MOSFET is electrically connected to a source terminal of the JFET and a source terminal of the MOSFET is electrically connected to a gate terminal of the JFET. A first semiconductor layer in which the MOSFET is formed and a second semiconductor layer in which the JFET is formed, are situated stacked on top of one another via a connecting material. Both an electrical and a thermal coupling between the JFET and the MOSFET are implemented via the connecting material. The stacked semiconductor layers are situated on the substrate. The first semiconductor layer includes a first subarea in which the MOSFET is formed and at least one second subarea in which the at least one sensor system is formed.

Claims

1. A cascode arrangement, comprising: a substrate; a self-conducting semiconductor switch; a MOSFET; and at least one sensor system; wherein: a drain terminal of the MOSFET is electrically connected to a source terminal of the self-conducting semiconductor switch, and a source terminal of the MOSFET is electrically connected to a gate terminal of the self-conducting semiconductor switch, a first semiconductor layer in which the MOSFET is formed, and a second semiconductor layer in which the self-conducting semiconductor switch is formed, are situated stacked on top of one another via a connecting material, both an electrical and a thermal coupling between the self-conducting semiconductor switch and the MOSFET being implemented via the connecting material, the stacked semiconductor layers are situated on the substrate, the first semiconductor layer includes a first subarea in which the MOSFET is formed, and includes at least one second subarea in which the at least one sensor system is formed, and the sensor system is configured to detect at least one physical variable relating to the self-conducting semiconductor switch, and to provide a signal representing the physical variable.

2. The cascode arrangement as recited in claim 1, wherein: (i) the self-conducting semiconductor switch is an SiC-JFET and/or a GaN-HEMT, and/or (ii) the MOSFET is an Si-MOSFET, and/or (iii) the connecting material is a sinter material and/or a solder.

3. The cascode arrangement as recited in claim 1, wherein: (i) a surface of the first semiconductor layer and a surface of the second semiconductor layer have an essentially identical size and/or geometry, and/or (ii) the surface of the first semiconductor layer and the surface of the second semiconductor layer s are stacked on top of one another in an essentially completely overlapping manner, and/or (iii) the second semiconductor layer includes an edge structure extending beyond the first semiconductor layer.

4. The cascode arrangement as recited in claim 1, wherein the at least one physical variable includes: a temperature, and/or a voltage, and/or a current.

5. The cascode arrangement as recited in claim 1, wherein, within the second subarea and/or withing further subareas of the semiconductor layer, the following is formed: an actuator system including a gate driver, and/or a logic circuit including an activation circuit for the gate driver, and/or a contact surface.

6. The cascode arrangement as recited in claim 1, wherein the following is integrated into the cascode arrangement: a push/pull stage, and/or a Miller Clamp Transistor for preventing a parasitic reactivation of the self-conducting semiconductor switch, and/or a protective circuit, and/or a communication interface.

7. The cascode arrangement as recited in claim 1, wherein the logic circuit is configured to: ascertain deviations of the at least one physical variable from a predefined setpoint value range, and/or carry out calculations based on the signal, and/or activate the MOSFET as a function of the signal generated by the sensor system, and/or match tolerances of circuit characteristics of the MOSFET and of the self-conducting semiconductor switch to one another.

8. The cascode arrangement as recited in claim 1, wherein: i) the source terminal of the MOSFET is connected via a resistor to the gate terminal of the self-conducting semiconductor switch, the resistor being a temperature-compensated gate resistor, and/or ii) a sensor system and/or an actuator system and/or a logic circuit is additionally provided in the second semiconductor layer.

9. The cascode arrangement as recited in claim 1, wherein: the signal is an initial signal, and the sensor system is configured to detect at least one physical variable of the MOSFET and to provide a second signal representing the physical variable.

10. A semiconductor module, comprising: a plurality of cascode arrangements, each including: a substrate, a self-conducting semiconductor switch, a MOSFET, and at least one sensor system; wherein: a drain terminal of the MOSFET is electrically connected to a source terminal of the self-conducting semiconductor switch, and a source terminal of the MOSFET is electrically connected to a gate terminal of the self-conducting semiconductor switch, a first semiconductor layer in which the MOSFET is formed, and a second semiconductor layer in which the self-conducting semiconductor switch is formed, are situated stacked on top of one another via a connecting material, both an electrical and a thermal coupling between the self-conducting semiconductor switch and the MOSFET being implemented via the connecting material, the stacked semiconductor layers are situated on the substrate, the first semiconductor layer includes a first subarea in which the MOSFET is formed, and includes at least one second subarea in which the at least one sensor system is formed, and the sensor system is configured to detect at least one physical variable relating to the self-conducting semiconductor switch, and to provide a signal representing the physical variable.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments of the present invention are described in detail below with reference to the figures.

(2) FIG. 1 schematically shows a top view of one specific example embodiment of a cascode arrangement according to the present invention.

(3) FIG. 2 schematically shows a cross-sectional view of the cascode arrangement shown in FIG. 1 in connection with a substrate and a drain terminal.

(4) FIG. 3 shows a circuit diagram of an exemplary cascode circuit according to the present invention.

(5) FIG. 4 schematically shows a view of one specific example embodiment of a semiconductor module according to the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(6) FIG. 1 schematically shows a top view of one specific embodiment of a cascode arrangement 5 according to the present invention.

(7) Cascode arrangement 5 includes a first semiconductor layer 50 and a second semiconductor layer 55, an Si-MOSFET 30 being formed in a first subarea 70 of first semiconductor layer 50, whereas an SiC-JFET 20 is formed in second semiconductor layer

(8) First semiconductor layer 50 is thermally, electrically and fixedly connected to second semiconductor layer 55 via a connecting material 60 shown in FIG. 2, which in this case is a sinter material. The electrical connection is formed in such a way that Si-MOSFET 30 and SiC-JFET 20 are interconnected as shown in FIG. 3. Second semiconductor layer 55 extends beyond first semiconductor layer 50 in this case evenly via an edge structure 57 of second semiconductor layer 55.

(9) In a second subarea 72 of first semiconductor layer 50, cascode arrangement 5 according to the present invention also includes a temperature sensor 40, which is designed here as a diode and which is configured to detect a temperature of SiC-JFET 20 on the basis of the thermal coupling between layers 50, 55.

(10) In a third subarea 74 of first semiconductor layer 50, cascode arrangement 5 according to the present invention further includes a current sensor 42, which is designed on the basis of a current mirror.

(11) In addition, an actuator system 80 in the form of a gate driver for Si-MOSFET 30 is formed in a fourth subarea 76 of first semiconductor layer 50. Furthermore, a logic circuit 90 configured to, among other things, receive an initial signal from temperature sensor 40 and a second signal from current sensor 42, to process the signals and to provide a result of the processing via a UART communication interface 110 is situated in fourth subarea 76, the communication interface 110 being formed by respective contact surfaces 100, which are also situated in fourth subarea 76 of first semiconductor layer 50.

(12) Furthermore, two contact surfaces 100 are situated in fourth subarea 76, via which a supply of voltage 120 to logic circuit and to actuator system 80 designed as a gate driver takes place.

(13) Cascode arrangement 5 is configured to receive an external PWM signal for activating the gate driver via a further contact surface 100 situated in fourth subarea 76, which serves as PWM interface 130.

(14) FIG. 2 schematically shows a cross-sectional view of cascode arrangement 5 shown in FIG. 1 in connection with a substrate and a drain terminal 24, the cross section being seen along line A shown in FIG. 1.

(15) It should be noted that to avoid repetitions, only those elements are described in FIG. 2 that are not shown in FIG. 1.

(16) Second semiconductor layer 55 is electrically connected to a drain electrode 24 of SiC-JFET 20 with the aid of connecting material 60 shown in FIG. 1, drain electrode 24 being attached at a substrate 10 of cascode arrangement 5.

(17) FIG. 3 shows a circuit diagram of an exemplary cascode circuit, which facilitates understanding of the present invention.

(18) An Si-MOSFET 30 of the cascode arrangement is connected to a source terminal 22 of a SiC-JFET 20 via a drain terminal 34 of Si-MOSFET 30.

(19) A source terminal 32 of Si-MOSFET 30 is connected to a gate terminal 26 of SiC-JFET 20 via a resistor R.

(20) In this way, the cascode circuit is configured to control a load current between a source terminal 32 of Si-MOSFET 30 and a drain terminal 24 of SiC-JFET 20 with the aid of an activation via a gate terminal 36 of Si-MOSFET 30.

(21) FIG. 4 schematically shows a view of one specific embodiment of a semiconductor module according to the present invention, the semiconductor module in this case including six cascode arrangements 5 according to the present invention, which are configured to transfer measuring signals of a respective sensor system (not shown) to a higher-level evaluation unit 140 via respective communication interfaces 110.

(22) Evaluation unit 140 is configured to monitor respective states of the six cascode arrangements 5 on the basis of the measuring signals.