BOOST CONVERTER CIRCUITS

Abstract

A boost converter circuit is disclosed comprising an input to receive an input voltage from a battery; an output to generate a higher, output voltage for powering a further circuit portion; and a switching arrangement to control generation of the output voltage. The boost converter circuit compares the input voltage with a first reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison. The boost converter circuit monitors a parameter indicative of a condition of the battery, determines a second, lower reference input voltage in response to the monitored parameter, compares the input voltage with the second reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the second reference input voltage.

Claims

1. A boost converter circuit comprising: an input arranged to receive an input voltage from a battery; an output arranged to generate a higher, output voltage for powering a further circuit portion; and a switching arrangement arranged to control generation of the output voltage; wherein the boost converter circuit is arranged: to compare the input voltage with a first reference input voltage; to control the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the first reference input voltage; to monitor a parameter indicative of a condition of the battery; to determine a second, lower reference input voltage in response to the monitored parameter; to compare the input voltage with the second reference input voltage; and to control the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the second reference input voltage.

2. The boost converter circuit of claim 1, arranged to control the switching arrangement to limit the output current of the boost converter circuit if the input voltage is equal to or is less than the first and/or second reference input voltage.

3. The boost converter circuit of claim 1, comprising an input comparator arranged to compare the input voltage with the first and/or second reference input voltage.

4. The boost converter circuit of claim 1, arranged to compare the input voltage with the first reference input voltage when the monitored parameter is above a threshold and to compare the input voltage with the second reference input voltage when the monitored parameter is below the threshold.

5. The boost converter circuit of claim 1, wherein the parameter indicative of a condition of the battery is the output voltage.

6. The boost converter circuit of claim 1, arranged to generate an alert in response to the monitored parameter.

7. The boost converter circuit of claim 1, wherein the first and/or second reference input voltage is selected such that the output current of the boost converter circuit is limited to a level below a maximum possible output current of the boost converter circuit.

8. The boost converter circuit of claim 1, wherein the first and/or second reference input voltage is more than half of an unloaded battery voltage of the battery.

9. The boost converter circuit of claim 1, comprising one or more output capacitors connected in parallel to the output.

10. The boost converter circuit of claim 1, arranged to determine a third reference input voltage in response to the monitored parameter, to compare the input voltage with the third reference input voltage; and to control the switching arrangement to limit the output current of the boost converter circuit in response to the comparison of the input voltage with the third reference input voltage.

11. A circuit system comprising: a battery arranged to generate an input voltage; and a boost converter circuit comprising: an input connected to the input voltage generated by the battery; an output arranged to generate a higher, output voltage for powering a further circuit portion; and a switching arrangement arranged to control generation of the output voltage; wherein the boost converter circuit is arranged: to compare the input voltage with a first reference input voltage; to control the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the first reference input voltage; to monitor a parameter indicative of a condition of the battery; to determine a second, lower reference input voltage in response to the monitored parameter; to compare the input voltage with the second reference input voltage; and to control the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the second reference input voltage.

12. The circuit system of claim 11, wherein battery has a nominal capacity of less than 2000 mWh.

13. The circuit system of claim 11, comprising the further circuit portion connected to the output.

14. The circuit system of claim 13, wherein the further circuit portion has a minimum operational voltage and the second reference input voltage is determined in response to the monitored parameter to maintain the output voltage above the minimum operational voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] One or more non-limiting examples will now be described, by way of example only, and with reference to the accompanying figures in which:

[0046] FIG. 1 is a schematic diagram of a circuit system according to an embodiment of the invention;

[0047] FIGS. 2 and 3 are a timing diagrams illustrating the operation of the circuit portion in FIG. 1;

[0048] FIG. 4 is a schematic diagram of a circuit system according to another embodiment of the invention; and

[0049] FIG. 5 is a timing diagrams illustrating the operation of the circuit portion in FIG. 4.

DETAILED DESCRIPTION

[0050] FIG. 1 shows a circuit system 100 comprising a battery 102, a boost converter circuit 104 and a System-on-Chip (SoC) 108. The battery 102 and the boost converter 104 together power the SoC 108. As will be explained in more detail below, the boost converter circuit 104 receives an input voltage V.sub.DDL from the battery 102 and provides a higher output voltage V.sub.DD to the SoC 108. The SoC 108 requires a minimum operational voltage V.sub.DDRESET of 1.7 V.

[0051] The SoC 108 requires a voltage of between 1.8 and 3.6 V to operate. Allowing for a small margin of error, the SoC 108 specifies a minimum voltage V.sub.DDMIN of 2 V. The battery 102 has a non-zero internal resistance R.sub.int and an unloaded voltage V.sub.unl. R.sub.int and V.sub.unl vary depending on the state of charge of the battery 102 and the age of the battery 102. The unloaded voltage V.sub.unl is typically between 1.1 V and 1.7 V. The internal resistance R.sub.int is typically around 20 .

[0052] The SoC 108 is connected to the output voltage V.sub.DD in parallel with a first decoupling capacitor 110 and a second decoupling capacitor 112. The second decoupling capacitor 112 has a larger capacitance than the first decoupling capacitor 110. During normal operation, the decoupling capacitors 110, 112 decouple the SoC 108 from any noise in the power supplied by the boost converter circuit 104, and also provide a charge reservoir for satisfying transient higher current demands from the SoC 108. Similarly, the boost converter circuit 104 itself is connected to the battery 102 in parallel with a battery decoupling capacitor 114. The battery decoupling capacitor 114 also acts to smooth noise and as a charge reservoir for the boost converter circuit 104.

[0053] The boost converter circuit 104 comprises an inductor 116 connected to the input voltage V.sub.DDL, a switching arrangement 118, a boost control circuit portion 120 and an input voltage control portion 121.

[0054] The boost control circuit portion 120 controls operation of the switching arrangement 118. The switching arrangement 118 comprises a first switch 122 operable to connect the inductor 116 to ground and a second switch 124 operable to connect the inductor 116 to the output of the boost converter 104.

[0055] The boost control circuit portion 120 receives inputs from a first comparator 126 and a second comparator 128. The first comparator 126 compares the input voltage V-.sub.DDL with a reference input voltage provided by the input voltage control portion 121.

[0056] The second comparator 128 compares a divided version of the output voltage V.sub.DD/ (with a determined by a pair of voltage divider resistors 134), with a reference output voltage V.sub.REF, OUT. The reference output voltage V.sub.REF, OUT is selected such that V.sub.REF, OUT equals a target output voltage. In this case, the target voltage is 3 V. The reference output voltage V.sub.REF, OUT may be programmable, to correspond with different target voltages, e.g. for powering different SoCs.

[0057] The input voltage control portion 121 comprises an output voltage comparator 130 and a multiplexer 132. The output voltage comparator 130 receives the divided version of the output voltage V.sub.DD/ at its inverting input, and an output voltage threshold V.sub.DDMIN at its non-inverting input. The multiplexer 132 comprises two inputs, a first reference input voltage V.sub.DDLLMINH and a second, lower reference input voltage V.sub.DDLLMINL. The output of the multiplexer 132 is the reference input voltage supplied to the first comparator 126. When the output of the output voltage comparator 130 is high (i.e. when the divided version of the output voltage V.sub.DD/ is higher than the output voltage threshold V.sub.DDMIN), the multiplexer 132 outputs the first reference input voltage V.sub.DDLLMINH. When the output of the comparator 130 is low (i.e. when the divided version of the output voltage V.sub.DD/ is lower than the output voltage threshold V.sub.DDMIN) the multiplexer 132 outputs the second reference input voltage V.sub.DDLMINL.

[0058] In use, the boost converter circuit 104 boosts the first voltage V.sub.DDL from the battery 102 to the output voltage V.sub.DD by switching the first and second switches 122, 124 on and off repeatedly. Each cycle of boost converter operation involves the following steps: [0059] 1. The first switch 122 closes (with the second switch 124 open) and connects the right end of the inductor 116 to ground (0 V). The current through the inductor 116 ramps up with time, as does the magnetic field generated by the inductor 116. The length of time for which the first switch 122 is closed (and the resulting current set up in the inductor 116) is controlled by the boost control circuit portion 120 based on the output current requirement of the boost converter circuit 104. [0060] 2. The first switch 122 opens and the second switch 124 closes. Now, the right end of the inductor 116 is connected to the output of the boost converter circuit 104. The magnetic field in the inductor 116 will force the current to continue to flow in the same direction as before, to the output of the boost converter circuit 104. A voltage (e.m.f.) is set up over the inductor 116 in series with the input voltage V.sub.DDL, to produce a higher output voltage V.sub.DD. [0061] 3. When the current through the inductor 116 goes to zero, the second switch 124 opens. Both switches 122, 124 now remain open until the beginning of the next boost cycle. Alternatively, in a different mode of boost, the switches 122, 124 remain open until the output voltage V.sub.DD falls below the reference output voltage V.sub.REF, OUT.

[0062] In other words, in boost converter operation the switches 122, 124 are controlled to repeatedly store energy in the magnetic field of the inductor 116 and then release this to produce the boosted output voltage V.sub.DD. As long as sufficient current is supplied from the battery 102, this process maintains the output voltage V.sub.DD at the predetermined target voltage at the output of the boost converter circuit 104.

[0063] FIG. 2 shows a timing diagram 200 illustrating the operation of the boost converter circuit 104 with a new and fully charged battery 102. At an initial time t.sub.0, the SoC 108 is drawing no or very little load 202. The boost converter circuit 104 delivers a stable output voltage V.sub.DD of 3.0 V, with the input voltage V.sub.DDL at 1.1 V. The output voltage V.sub.DD is above V.sub.DDMIN, so the multiplexer 132 provides the first reference input voltage V.sub.DDLMINH to the first comparator 126.

[0064] However, the current demanded by the SoC 108 varies. For instance, operations such as programming, transmitting and receiving may demand relatively large currents while other operations require very little current. At time t.sub.1. the SoC 108 begins to draw an increased load 202 (e.g. because a transmission cycle begins). At first, the boost converter circuit 104 simply reacts to stop V.sub.DD from dropping significantly by providing the necessary increased current, using charge supplied by the battery decoupling capacitor 114. As the charge on the battery decoupling capacitor 114 is used up, the increased current demand on the battery 102 causes V.sub.DDL to drop (due to an increased voltage drop over the internal resistance R.sub.int).

[0065] At t.sub.2, V.sub.DDL drops below the first reference input voltage, V.sub.DDLMINH. This causes the first comparator 126 to output a low signal to the control circuit portion 120. In response, the control circuit portion 120 stops boost converter operation and stops delivering current to the output of the boost converter circuit 104.

[0066] Whilst the boost converter operation is stopped, the current demand at the output is delivered by the first and second decoupling capacitors 110, 112, and the output voltage V.sub.DD slowly falls as the decoupling capacitors 110, 112 are discharged.

[0067] After some time, when V.sub.DDL has recovered to a voltage slightly higher than the reference input voltage, V.sub.DDLMINH (to account for hysteresis of the first comparator 126), the first comparator 126 outputs a high signal to the control circuit portion 120 and boost converter operation starts again. This repeats whilst the current demand remains high, having the effect of stabilising the input voltage V.sub.DDL at reference input voltage, V.sub.DDLMINH and limiting the current output of the boost converter circuit 104.

[0068] The first reference input voltage V.sub.DDLMINH is selected so that the output current of the boost converter circuit 104 is limited at a level below the maximum possible output current. The maximum output current may be delivered when the input voltage V.sub.DDL is equal to half of the unloaded battery voltage (see equation (5) above), so V.sub.DDLMINH is selected to be greater than half of the unloaded battery voltage. In this example the unloaded battery voltage is 1.1 V and V.sub.DDLMINH is 1 V. Allowing the boost converter circuit 104 to draw less than the maximum possible current increases the amount of energy that can be extracted from the battery 102 because less energy is lost to the internal resistance of the battery 102. The size of the capacitors 110, 112 may be chosen to ensure that sufficient current can still be delivered to the SoC 108 during periods of load high load. In other words, the boost converter circuit 104 may act to average the current drawn from the battery 102 to reduce energy losses associated with large current spikes.

[0069] After the current limiting kicks in at t.sub.2, the current demanded by the SoC 108 is higher than the maximum output current of the boost converter circuit 104. Thus, the output voltage V.sub.DD begins to drop as charge is used up from the decoupling capacitors 110, 112. This drop continues until t.sub.3. when the load 202 drawn by the SoC 108 drops back to its initial low value. However, the decoupling capacitors 110, 112 (and the battery decoupling capacitor 114) still need to be recharged. The decoupling capacitors 110, 112 thus continue to draw a large output current from the boost converter circuit 104 (which continues to limit the output current by switching on and off based on the level of V.sub.DDL) until they are fully recharged at time t.sub.4. The current demanded from the boost converter circuit 104 then returns to a low level and the battery decoupling capacitor 114 re-charges to 1.1 V. The system 100 is now ready for the next load pulse e.g. the next transmission cycle.

[0070] FIG. 3 shows a timing diagram 300 illustrating the operation of the boost converter circuit 104 at a later time, when the battery 102 has partially discharged. As a result of the discharging, the internal resistance R.sub.int has increased, i.e., the condition of the battery 102 has deteriorated.

[0071] At time t.sub.5, the SoC 108 is drawing no or very little load 202. Despite the fact that the battery's condition has deteriorated, the load 202 is small and the boost converter circuit 104 is still able to deliver a stable output voltage V.sub.DD of 3.0 V, with the input voltage V.sub.DDL at 1.1 V. The output voltage V.sub.DD is above V.sub.DDMIN, so the multiplexer 132 provides the first reference input voltage V.sub.DDLMINH to the first comparator 126.

[0072] At time t.sub.6. the load 202 drawn by the SoC 108 increases (e.g. because a transmission cycle begins). As before, the boost converter circuit 104 initially reacts to stop V.sub.DD from dropping significantly by providing the necessary increased current using charge supplied by the battery decoupling capacitor 114. As the charge on the battery decoupling capacitor 114 is used up, the increased current demand on the battery 102 causes V.sub.DDL to drop (due to an increased voltage drop over the internal resistance R.sub.int).

[0073] At t.sub.7, V.sub.DDL drops below the first reference input voltage, V.sub.DDLMINH. This causes the first comparator 126 to output a low signal to the control circuit portion 120. In response, the control circuit portion 120 stops boost converter operation and stops delivering current to the output of the boost converter circuit 104. As before, the boost converter circuit 104 is switched on and off to limited the output current and stabilise the input voltage V.sub.DDL around the first reference input voltage, V.sub.DDLMINH. However, because the internal resistance R.sub.int has increased, the battery 102 provides a smaller input current than before and the boost converter circuit 104 must limit the output current at a corresponding lower level to maintain V.sub.DDL at V.sub.DDLMINH. This causes the output voltage V.sub.DD to drop more quickly. The output voltage V.sub.DD is thus indicative of the condition of the battery 102.

[0074] As indicated by the dotted line in FIG. 3, if the output voltage V.sub.DD continued to drop at this rate it would reach the minimum operational voltage V.sub.DDRESET for the SoC 108 before the end of the load pulse and the SoC 108 would stop working. Therefore the boost converter circuit 104 monitors the output voltage using the output voltage comparator 130 and takes appropriate mitigating action. At time t.sub.8, the output voltage V.sub.DD reaches the output voltage threshold V.sub.DDMIN. This causes the output of the output voltage comparator 130 to go low and the multiplexer 132 to output the second, lower reference input voltage V.sub.DDLMINL. When the output voltage V.sub.DD reaches the output voltage threshold V.sub.DDMIN the boost converter circuit 104 the low output of the output voltage comparator 132 is sent to the SoC 108 as an alert identifying the decline in battery condition indicated by the drop in the output voltage V.sub.DD (e.g. a low battery alert that indicates that the battery may need replacing or recharging soon).

[0075] The second reference input voltage V.sub.DDLMINL is also selected so that the output current of the boost converter circuit 104 is limited at a level below the maximum possible output current.

[0076] Because the multiplexer 132 is now outputting the second, lower reference input voltage V.sub.DDLMINL., at time t.sub.8 the boost converter circuit 104 allows the input voltage V.sub.DDL to drop to V.sub.DDLMINL. This compensates for the increase in R.sub.int and allows the boost converter circuit 104 to maintain the output voltage V.sub.DD at or slightly above the threshold V.sub.DDMIN (see equation (6)). In other words, by relaxing the input voltage requirement the boost converter circuit 104 allows additional energy to be extracted from the battery 102. This allows the boost converter circuit 104 to maintain the output voltage V.sub.DD above V.sub.DDRESET throughout the whole load pulse.

[0077] When the load pulse ends at time t.sub.9, the decoupling capacitors 110, 112 are recharged to 3.0 V and at time t.sub.10 the battery decoupling capacitor 114 re-charges to 1.1 V. The output of the voltage comparator 130 goes high and the multiplexer 132 once again outputs the first reference input voltage V.sub.DDLMINH.

[0078] FIG. 4 illustrates another circuit portion 400 comprising a battery 102, a boost converter circuit 404 and a System-on-Chip (SoC) 108. The battery 102 and the boost converter 404 together power the SoC 108. The battery 102 and the SoC 108 are identical to those described above. The boost converter circuit 404 is the same as the boost converter circuit described above aside from the input voltage control portion 421. As explained above, the boost converter circuit 404 receives an input voltage V.sub.DDL from the battery 102 and provides a higher output voltage V.sub.DD to the SoC 108.

[0079] The normal operation of the boost converter circuit 404 is the same as that described above with reference to FIGS. 1 and 2. However, in this embodiment the input voltage control portion 421 comprises a comparison portion 430 and a multiplexer 432 with a plurality of inputs which receive a plurality of reference input voltages V.sub.DDLMIN0-V.sub.DDLMINX. The comparison portion 430 compares the divided version of the output voltage V.sub.DD/ to a plurality of reference output voltages V.sub.DDMIN0- V.sub.DDMINX, and uses the multiplexer 423 to provide an appropriate reference input voltage V.sub.DDLMIN0-V.sub.DDLMINX to the first comparator 126.

[0080] FIG. 5 shows a timing diagram 500 illustrating the operation of the boost converter circuit 404.

[0081] At time t.sub.11, the SoC 108 is drawing no or very little load 202. The boost converter circuit 404 delivers a stable output voltage V.sub.DD of 3.0 V, with the input voltage V.sub.DDL at 1.1 V. The output voltage V.sub.DD is above V.sub.DDMIN0, so the multiplexer 432 provides the first reference input voltage V.sub.DDLMIN0 to the first comparator 426.

[0082] At time t.sub.12, the SoC 108 begins to draw an increased load 202 (e.g. because a transmission cycle begins). As before, the boost converter circuit 404 initially reacts to stop V.sub.DD from dropping significantly by providing the necessary increased current using charge supplied by the battery decoupling capacitor 114. As the charge on the battery decoupling capacitor 114 is used up, the increased current demand on the battery 102 causes V.sub.DDL to drop (due to an increased voltage drop over the internal resistance R.sub.int).

[0083] At t.sub.13, V.sub.DDL drops below the first reference input voltage, V.sub.DDLMIN0. This causes the first comparator 126 to output a low signal to the control circuit portion 120. In response, the control circuit portion 120 stops boost converter operation and stops delivering current to the output of the boost converter circuit 104.

[0084] As before, the boost converter circuit 404 is switched on and off to limited the output current and stabilise the input voltage V.sub.DDL around the first reference input voltage, V.sub.DDLMIN0. The first reference input voltage V.sub.DDLMIN0 is selected so that the output current of the boost converter circuit 404 is limited at a level below the maximum possible output current. This permitted current is lower than that demanded by the SoC 108. As such the output voltage V.sub.DD continues to drop as the charge on capacitors 110, 112 is used up.

[0085] At time t.sub.14, the output voltage V.sub.DD reaches the first reference output voltage V.sub.DDMIN0. The comparison portion 430 detects this and controls the multiplexer 423 to provide the second reference input voltage V.sub.DDLMIN1 to the first comparator 126. The comparison portion 430 also sends an alert to the SoC 108 identifying the decline in battery condition indicated by the drop in the output voltage V.sub.DD.

[0086] The second reference input voltage V.sub.DDLMIN1 is also selected so that the output current of the boost converter circuit 104 is limited at a level below the maximum possible output current. This current is greater than that available for the first reference input voltage V.sub.DDLMIN0 but is still insufficient to meet the current demands of the SoC 108. The output voltage V.sub.DD continues to drop.

[0087] At time t.sub.15, the output voltage V.sub.DD reaches the second reference output voltage V.sub.DDMIN1. The comparison portion 430 detects this and controls the multiplexer 423 to provide a third reference input voltage V.sub.DDLMIN2 to the first comparator 126. The comparison portion 430 also sends an alert to the SoC 108 identifying the decline in battery condition indicated by the fact that the output voltage V.sub.DD has dropped to the second reference output voltage V.sub.DDMIN1.

[0088] The third reference input voltage V.sub.DDLMIN2 may also be selected so that the output current of the boost converter circuit 104 is limited at a level below the maximum possible output current. This current is greater than that available for the first and second reference input voltages V.sub.DDLMIN0, V.sub.DDLMIN1. This is now sufficient to meet the current demands of the SoC 108. The output voltage V.sub.DD stabilises at V.sub.DDMIN1. However, later in the battery's life further corresponding reductions in the reference input voltage may be necessary to maintain the output voltage above V.sub.DDRESET, i.e., to extract the maximum possible energy from the battery 102.

[0089] The load pulse ends at time t.sub.16. The decoupling capacitors 110, 112 then recharge to 3.0 V and at time t.sub.17 the battery decoupling capacitor 114 re-charges to 1.1 V. The comparison portion 430 detects this and controls the multiplexer 423 to once again provide the first reference input voltage V.sub.DDLMIN02 to the first comparator 126.

[0090] While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.