METHOD FOR PROCESSING AN OPTOELECTRONIC DEVICE AND OPTOELECTRONIC DEVICE

Abstract

A method for processing an optoelectronic device includes providing a growth substrate having one of a [111], [110] or [100] surface with a (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP buffer layer located on the growth substrate having a parameter x between 0.2 and 0.8, inclusive, and a parameter y between 0.3 and 0.7, inclusive, and re-growing a doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer with a parameter x between 0.4 and 0.6, inclusive, and a parameter y between 0.3 and 0.7, inclusive, on exposed surfaces of an AlInP layer deposited on the buffer layer, the exposed surfaces surrounded by a structured hard mask comprising an amorphous material on non-exposed surfaces of the AlInP layer, wherein edges of the hard mask adjacent to at least one exposed portion of the of a surface of the AlInP layer extend along the [111] B lateral surfaces when the substrate has a [111] surface, or extend along the [110] lateral surfaces when the substrate has a [100] surface, or extend along the [100] lateral surfaces when the substrate has a [110] surface.

Claims

1.-21. (canceled)

22. A method for processing an optoelectronic device, the method comprising: providing a growth substrate having one of a [111], [110] or [100] surface with a (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP buffer layer located on the growth substrate having a parameter x between 0.2 and 0.8, inclusive, and a parameter y between 0.3 and 0.7, inclusive; re-growing a doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer with a parameter x between 0.4 and 0.6, inclusive, and a parameter y between 0.3 and 0.7, inclusive, on exposed surfaces of an AlInP layer deposited on the buffer layer, the exposed surfaces surrounded by a structured hard mask comprising an amorphous material on non-exposed surfaces of the AlInP layer, wherein edges of the hard mask adjacent to at least one exposed portion of the of a surface of the AlInP layer extend along the [111] B lateral surfaces when the substrate has a [111] surface, or extend along the [110] lateral surfaces when the substrate has a surface, or extend along the [100] lateral surfaces when the substrate has a surface; re-growing an active layer structure on the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer; re-growing a doped or intrinsic (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer along a top surface and sidewalls of the active layer down to the hard mask, wherein the (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer comprises a bandgap that is larger than a bandgap of the active layer; depositing an unstructured conductive material; and mesa-structuring the optoelectronic device.

23. The method according to claim 22, wherein the edges of the hard mask adjacent to the at least one exposed portion of the surface of the AlInP layer extend along the [111] lateral surfaces when the substrate has a [111] surface.

24. The method according to claim 22, wherein the edges of the hard mask adjacent to the at least one exposed portion of the surface of the AlInP layer form, in top view, a triangle or a hexagonal structure with its side along a [111] lateral surface when the substrate has a [111] surface.

25. The method according to claim 22, wherein re-growing the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer comprises: depositing the intrinsic AlInP layer on the buffer layer; depositing the structured hard mask on the surface of the AlInP layer, the structured hard mask comprising a recess exposing the surface; and depositing the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer on the exposed surface.

26. The method according to claim 22, wherein the re-growing a doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer comprises: depositing the structured hard mask on the buffer layer, the structured hard mask comprising a recess exposing a portion of the buffer layer surface; depositing the intrinsic AlInP layer on the exposed portions of the buffer layer; and depositing the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer on a top surface of the AlInP layer above the exposed portions.

27. The method according to claim 22, wherein re-growing the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer comprises: depositing the intrinsic AlInP layer on the buffer layer; applying a structured photoresist on the AlInP layer; etching the AlInP layer to form a protrusion; applying the amorphous material of the hard mask on top surface portions of the AlInP layer surrounding the protrusion; and depositing the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer on the top surface of the protrusion.

28. The method according to claim 27, wherein etching the AlInP layer forms inclined sidewalls with an increasing area towards the buffer layer.

29. The method according to claim 22, wherein a top surface of the deposited doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer exceeds a top surface of the hard mask; and/or wherein a top surface of the AlInP layer exceeds a top surface of the hard mask.

30. The method according to claim 22, further comprising providing a temperature, while depositing the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP, above 500 C.

31. The method according to claim 22, wherein the buffer layer is n-doped and the AlInP layer is n-doped or substantially intrinsic.

32. The method according to claim 22, wherein the amorphous material comprises at least one of SiO.sub.2, SiN, or Al.sub.2O.sub.3.

33. The method according to claim 22, wherein re-growing the active layer structure comprises: depositing a plurality of alternating layers of (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layers with different Al content forming a multi-quantum well structure; and depositing a quantum well structure.

34. The method according to claim 22, wherein a portion of the re-grown doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer exceeds partially on the top surface of the hard mask.

35. The method according to claim 22, wherein a thickness of the re-grown doped or intrinsic (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer on the sidewalls of the active layer is in a range between 10 nm and 200 nm, inclusive.

36. The method according to claim 22, wherein t re-growing the doped or intrinsic (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer comprises depositing a p-doped contact layer on the top surface of the re-grown doped or intrinsic (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer.

37. The method according to claim 22, wherein the unstructured conductive material comprises one of ITO, Ag, Ti, TiN, or Au.

38. An optoelectronic device comprising: a structured semiconductor layer stack arranged between a first contact area on a light emission surface and a second contact area on a surface opposite the light emission surface, the structured semiconductor layer stack comprising: a hard mask layer including an amorphous material having a recess; a doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer with a parameter x between 0.4 and 0.6, inclusive, and a parameter y between 0.3 and 0.7, inclusive above or within the recess of the hard mask layer with its top surface elevated above a surface of the hard mask; an active layer selectively arranged on the top surface of the (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer, the active layer including a quantum well or multi-quantum well structure based on InGaAlP material with different Al contents between well layers and adjacent barrier layers of the quantum well or the multi-quantum well structure; and a doped or intrinsic (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer arranged on a top surface and sidewalls of the active layer tapering down to the hard mask layer.

39. The optoelectronic device according to claim 38, wherein edges of the hard mask layer adjacent to the recess extend along the lateral surfaces, on which the hard mask layer is arranged; or wherein edges of the hard mask adjacent to the at least one exposed portion of the surface of an underlying layer form, in top view, a triangle or a hexagonal structure with its side along a [111] lateral surface; or wherein edges of the hard mask layer adjacent to the recess extend along the [110] lateral surfaces, on which the hard mask layer is arranged; or wherein edges of the hard mask layer adjacent to the recess extend along the [100] lateral surfaces, on which the hard mask layer is arranged.

40. The optoelectronic device according to claim 38, wherein the structured semiconductor layer stack further comprises an AlInP layer, wherein the AlInP layer at least partially fills the recess, and/or wherein the hard mask layer is arranged on the AlInP layer, and/or wherein the AlInP layer comprises at least partially inclined sidewalls adjacent to the amorphous material of the hard mask layer.

41. The optoelectronic device according to claim 38, further comprising an unstructured conductive material arranged on the doped or intrinsic (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer and a surrounding material of the hard mask layer.

42. The optoelectronic device according to claim 41, wherein the hard mask layer comprises SiO.sub.2, SiN, or Al.sub.2O.sub.3, and wherein the unstructured conductive material comprises ITO, Ag, Ti, TiN, or Au.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings.

[0037] FIGS. 1A to 1H illustrate steps of a method for processing an optoelectronic device in accordance with some aspects of the proposed principle;

[0038] FIG. 2 shows a variation of a processing step of a method for processing an optoelectronic device in accordance with some aspects of the proposed principle;

[0039] FIGS. 3A and 3B illustrate results of some processing steps of a method in accordance with the proposed principle;

[0040] FIGS. 4A to 4C illustrate further steps of another embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principle;

[0041] FIG. 5 shows a variant of an optoelectronic device in accordance with some aspects of the proposed principle; and

[0042] FIG. 6A to 6C illustrate variant of an opening in the hard mask or a protrusion of the underlying material in accordance with several aspects of the proposed principle.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0043] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle. The embodiments and examples are not always to scale. Likewise, different elements can be displayed enlarged or reduced in size to emphasize individual aspects. It goes without saying that the individual aspects of the embodiments and examples shown in the Figures can be combined with each other without further ado, without this contradicting the principle according to the invention. Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without, however, contradicting the inventive idea.

[0044] In addition, the individual Figures and aspects are not necessarily shown in the correct size, nor do the proportions between individual elements have to be essentially correct. Some aspects are highlighted by showing them enlarged. However, terms such as above, over, below, under larger, smaller and the like are correctly represented with regard to the elements in the Figures. So it is possible to deduce such relations between the elements based on the Figures.

[0045] FIGS. 1A to 1H illustrate several steps of a method for processing an optoelectronic device in accordance with the proposed principle.

[0046] The proposed method is based on a bottom-up re-growth process also referred to as selective area growth or SAG to process optoelectronic devices having a very small edge size based on the InGaAlP material system. The proposed bottom-up regrowth process is an alternative to conventional re-growth processes, but avoids etching the sidewall of the active layer, thereby preventing damages and contamination to the active layer's surface. The proposed approach provides an easier fabrication and less risk of contamination due to the reduced number of process steps involved. As a result, a higher quality in crystal growth particularly around the active layer as well as the reduction of dislocations on the different lattice planes is achieved.

[0047] The exemplary shown process requires a {111}-oriented GaAs substrate as a growth substrate to promote a selective growth in the respective crystal directions. For the purpose of this application a {111}-oriented substrate (including all equivalent [111] planes) and [111] direction shall be used synonymous. It means that the orientation as well as the surface of the respective growth substrate facilitates and supports growth of the ternary InAlP material as well as the quaternary InGaAlP material smoothly and at least from an ideal crystallographic perspective only with monoatomic crystal step (in contrast to other direction which require a biatomic step).

[0048] The [111] oriented plane on the GaAs growth substrate 10 enables a deposition of further layers in a monoatomic step with suitable precursors. In such way that no or only a very few dislocations due to crystal step in the usual growth direction occurs and those do not usually continue through the buffer layer (that is they are overgrown easily). As such, the [111] oriented GaAs substrate 10 is utilized to reduce the dislocations in the further crystal growth.

[0049] As illustrated in FIG. 1A the growth substrate 10 with its [111] oriented surface plane is provided and an n-doped (Ga) AlInP layer is epitaxially deposited thereupon. In the present example, a (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP buffer layer material 11 having parameter x between 0.2 and 0.8 and more particularly between 0.3 and 0.7 and more particularly between 0.4 and 0.6 and parameter y between 0.3 and 0.7 and more particularly between 0.4 and 0.6 is deposited on the growth substrate. As it can be seen from parameter x, this can also be zero, thereby creating a pure AlInP layer on the growth substrate.

[0050] In some instances, the n-doped layer 11 also acts as a current injection layer into the subsequent layers and the active layer of the respective optoelectronic device. Consequently, the n-doped buffer layer 11 may comprise a variation in parameters x and y, for example changing the In content to introduce a small variation of strain in order to change the bandgap in the active region later on thereby changing the colour of the emitted light. Furthermore, the doping level may be adjusted to reduce the resistance of the layer.

[0051] On top of buffer layer 11 an intrinsic, that is mainly undoped bottom layer 12 of InAlP material is deposited. It is possible to transform from the buffer layer 11 to layer 12 in a smooth way by reducing the Ga content during the epitaxial growth process. While in the present example, the AlInP layer 12 is substantially undoped, a n-type doping profile can be induced to improve the carrier injection and transport behaviour into the active region.

[0052] An optional layer 13 made of GaAlInP can be applied in accordance with FIG. 1A, which can also act as a further growth material for subsequent processes. However, said layer 13 can also be omitted to simplify the manufacturing process. The GaAlInP comprises a composition of (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP with x between 0.3 and 0.7 and more particular between 0.4 and 0.6. Parameter y is between 0.4 and 0.6 for example.

[0053] Due to the [111]-oriented growth substrate 10, all subsequent layers 11 and 12 are overgrown in such way that the respective top surfaces are also oriented in the same direction.

[0054] Continuing with FIG. 1B, a hard mask layer 14 made of an amorphous dielectric material is deposited on the top of the [111]-oriented surface of layer 12 and subsequently structured as well as etched to provide a recess 140 therein. The resulting recess has a certain structure when viewed from top as outlined with regards to FIG. 6. Its edges mainly follow the 111 direction of the underlaying layer. In the present example the recess comprises a hexagonal shape when viewed form top. The etching step will expose portions of the [111]-oriented top surface 120 of layer 12. In this regard, the structuring of hard mask 14 follows the location and orientation of the LEDs during processing of the optoelectronic devices particularly on wafer level. In other words, the recesses define the optoelectronic devices on a wafer level.

[0055] Following FIG. 1C in a subsequent step, the recess 140 is filled with a (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP material with parameter x between 0 and 0.6 and in particular 0.5 forming layer 13. With X being 0 the material becomes InAlP. Said material follows a selective area growth process using certain growth conditions, which favour a selective deposition of the GaAlInP filler material within the recess but not on the top surface of the amorphous material for the respective hard mask 14. As a possible example, a re-growth condition for layer 13 includes a regrowth temperature in the range of 700 C. to 730 C.

[0056] As a result for such conditions, any material deposited on the top surface of the amorphous dielectric 14 will be resorb again and re-grow in the recess. The selective re-growth process in the [111] direction continues until the filler material of layer 13 slightly elevates above the top surface of the respective hard mask 14. The elevation 130, illustrated in FIG. 1C may lead to a small overall growth 131 as shown in FIG. 1D, on the top surface of the surrounding amorphous material of hard mask 14. However, such overlap may be in the range of a few 10 nm to approximately 100 nm, which is orders of magnitude smaller than the size of the recess. The overlap can be controlled slightly with varying the growth conditions during the growth period.

[0057] In a subsequent step illustrated in FIG. 1D, a plurality of different a quantum well barrier layers material as well as quantum well layer material is re-grown on the surface of GaAlInP layer 13 to form a multi-quantum well structure and active layer 15. Quantum well layer and quantum barrier layer both comprise an GaAlInP material. However, the respective barrier layers comprise an aluminum content which is slightly higher than the respective aluminum content in the quantum well material resulting in a higher bandgap. Each barrier layer as well as each quantum well layer comprise a thickness of a few nanometres. Due to the selected re-growth conditions, the material of the barrier layers as well as the quantum well layers are grown only along the already existing elevated portion of GaAlInP material of layer 13 along its [111]-direction. Due to the re-growth condition and the selected area growth, particularly the edges of the active layer 15 are substantially free from dislocations and further crystal defects.

[0058] After the re-growth of the multi-quantum well structure 15, an anisotropic lateral overgrowth of a wider bandgap material than the bandgap of the active region takes place. This step is also illustrated in FIG. 1D by material layer 16

[0059] Layer 16 comprises a p-doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer with parameter x between 0.3 and 0.7 and more particular between 0.4 and 0.6. Parameter x can also be 0 which corresponds to InAlP, but may comprise values like 0.45, 0.5 and 0.55 or 0.6. Furthermore x may correspond to a varying concentration decreasing from a value like 0.7 or 0.5 to 0. Parameter y is between 0.3 and 0.7 and particularly between 0.4 and 0.6. The p-doped GaAlInP layer 16 also acts as a current injection layer to provide carrier injection into the active layer region 15. The p-doped GaAlInP layer 16 encapsulates the multi-quantum well region 15, covering not only the top surface of the active layer 15, but also the sidewalls 160. Crystal defects or dangling bonds as well as dislocations along the edges of the active layer 16 are prevented or significantly reduced due to the growth conditions and the selective area growth of the p-doped GaAlInP layer 16.

[0060] In particular, no etching of the edges of the respective active region 15 takes place. The passivation and encapsulation of the edges of the multi-quantum well structure and active layer 15 will block charge carriers from diffusing towards the semiconductor surface and recombining therein in a non-radiative manner.

[0061] The thickness along the side wall of layer 16 is adjusted by the respective growth conditions and satisfies the current spreading and passivation of the multi-quantum well structure. Usually, a few nanometres to about 200 nm are sufficient. Furthermore, the p-doped GaAlInP layer 16 extends along the sidewall of the multi-quantum well structure of active layer 15, as well as along the elevated sidewall portions of layer 13 all the way down to the top surface of hard mask layer 14, thereby fully encapsulating layer 13 and 15, respectively.

[0062] Following the next process step depicted in FIG. 1E), selective re-growth on the top surface of p-doped GaAlInP layer 16 is performed by depositing a p-doped contact layer 17 made of p-doped GaP or P-doped GaAs. As an alternative option in this regard, the p-contact layer 17 can also be isotropically overgrown on the side facets of p-doped GaAlInP layer 16. However, such overgrowth, which can be adjusted and controlled by respective growth conditions, provide the risk of leakage beside the active region, thereby reducing the performance of the optoelectronic device.

[0063] However, adjusting the growth conditions and the design accordingly provides the benefit of a simpler fabrication due to the avoidance of additional photoresist layers and their respective structuring thereof.

[0064] Following the next step illustrated in FIG. 1F), a full wafer deposition is conducted to apply conductive contact material 18 onto the layer stack. Said material is a conductive transparent material or a conductive metal and is deposited along the top surface of hard mask 14, the sidewalls of the p-doped layer 16, as well as on the top surface of layer 17. Material on the hard mask layer 14 forms areas 18. Material is also deposited on the sidewalls 181, on top layer 18 thereby encapsulating the optoelectronic device.

[0065] The remaining steps follow a conventional Mesa structuring process, in which the photoresist layer 20 is deposited on top of layer 18 and structured accordingly to open recesses 22 surrounding the optoelectronic device. Then, those areas along the recesses 22 of the layer stack are etched resulting in a Mesa structure 21 as illustrated in FIG. 1H. The inclined sidewalls are a direct result of the structuring process and can be adjusted accordingly. After the etching process, a passivation layer 24, for example, comprising SiO.sub.2 or Al.sub.2O.sub.3 is provided on the exposed sidewalls of the mesa structure 21.

[0066] Finally, the respective optoelectronic device is re-bonded and the previous growth surface 10 processed accordingly. The present example, illustrated in FIG. 1H) utilizes the growth substrate 10 as part of the optoelectronic device. This is possible as the growth substrate may be a conductive semiconductor, which as presented is covered by a thin metal layer to provide a carrier injection into the device. Other process steps like removing the growth substrate 10, buffer layer 11 as well as thinning the layer 12 and further measures can be applied based on the needs, requirements, and design choices.

[0067] As illustrated in the first embodiment according to FIGS. 1A) to 1H), the selective area growth process is enabled without additional structuring, etching or diffusion steps during the growth processes. Particularly, no additional etching is necessary for the active region, thereby avoiding contamination, dislocation, and further crystal defects along the edges of the active layer. The hard mask 14 is used as a self-aligned insulation layer, which might be important for tiny optoelectronic devices where the alignment is critical. Furthermore, the hard mask layer 14 can remain on the final optoelectronic device and is not removed later on.

[0068] The layer design is adjustable by varying the growth conditions of the various layer 13 and 16, which allows a suppression of desired current path particularly along the sidewalls of the optoelectronic device.

[0069] In the present example, the hard mask layer was deposited on top of layer 12 and subsequently structured to expose a respective growth surface in the 111 direction. FIGS. 2 and 3 illustrate a slightly different embodiment, leading to a protrusion area, which is subsequently used as a growth surface for the selective growth of additional layers.

[0070] In FIG. 2, a growth substrate 10 is provided and the p-doped buffer layer 11 applied thereupon. An undoped AlInP layer 12 is deposited on the top surface of layer 11. Then, a structured photoresist layer 20 is deposited thereupon resulting in a portion of the surface of layer 12 covered. The area of the photoresist 20 covering the surface portion of layer 12 comprises a rectangular shape when viewed from the top. The edges of that shape are oriented along the [111] direction of the crystal lattice on the top surface. This will ensure that subsequent etching process removes material along the edge portions, leaving the [111] surface substantially intact.

[0071] Following FIGS. 3A) and 3B), various etches can be applied to remove portions of layer material 12, resulting in a different structure when viewed from the top as well as from of the side.

[0072] FIG. 3A shows inclined surface 122 generated by the etching process leaving a protrusion 121 of the undoped AlInP layer 12 behind. The photoresist layer 20 is covering its top surface. The inclination of the surface 122 is adjusted by the conditions for the etching process. The protrusion height is selected in such way that a top portion of the material of protrusion 121 still elevates the hard mask layer 14 deposited in a subsequent step.

[0073] In FIG. 3B), the etch is performed in such way that a substantially vertical edge of the protrusion 121 is achieved. Likewise, when viewed from the top, the shape of the protrusion 121 forms a hexagonal shape with recessed areas 123 surrounding it.

[0074] Continuing with FIG. 4A), the photoresist layer 20 is removed from the top 111 surface of protrusion 121. A hard mask layer made of for example of the silicon dioxide, SiO.sub.2 is applied to the exposed top surface of the layer stack. However, the top 111 surface of protrusion 121 is kept free from the hard mask material, either by proper protecting the top surface prior to deposition of the hard mask material, or simply removing the hard mask layer from the top surface in a subsequent etching step. The amorphous material of hard mask layer 14 surrounds of the protrusion still leaves an elevated portion of 125 behind.

[0075] Following FIG. 4B), the doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP material of layer 13 is selectively re-grown on the top 111 surface of the protrusion 121. In this regard to the top surface acts as the exposed surface in the previous embodiment (see FIG. 1C). The growth process of the n-doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP material 13 is selected such that no material overlaps the top surface. Consequently the growth condition may slightly vary from previous growth conditions, the temperature range between 650 C. to 850 areas and in particular between 700 C. and 730 C.

[0076] After depositing of the n-doped layer 13, the multi-quantum well structure 15 having various barrier and quantum well layers with different aluminum content are selectively re-grown. As explained previously, the subsequent step of depositing a p-doped layer 16 on the top surface of the multi-quantum well structure 15 and along the sidewalls of layer 13 and 121, respectively is achieved by a selective re-growth process. The material of layer 16 comprises a higher bandgap than the material of the active layer 15, thus causing an electric potential repelling charge carriers from diffusing to the edges of active layer 15. The material of layer 16 exceeds down to layer 14 which is similar as in the previous embodiment.

[0077] The resulting structure shown in FIG. 4C represents the layer stack of an optoelectronic device. Similar to the previous embodiment with the following process steps being repeated.

[0078] The alternative etching result of the layer 12 is illustrated in FIG. 3A) with its inclined surface 122 of the protrusion 121. The selective regrowth processes applied later on result in a slightly different structure depicted in FIG. 5.

[0079] The optoelectronic device comprises an inclined surface 122, which is partially covered by the hard mask layer 14 to about half of its height. On the top surface of protrusion 121, the (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer 13 with parameter in the ranges already mentioned above is deposited with the active region 15 deposited thereupon. As the inclined surface 121 may actually facilitate an undesired growth, the growth conditions in this regard might be a slightly different compared to the growth conditions for processing an optoelectronic device according to FIG. 4C with vertical sidewalls.

[0080] However, the inclined surface does not extend along 111 direction supporting the usual selective growth. Consequently, by selecting and adjusting the growth conditions accordingly, the material of layer 13 or layer 15 is not deposited on the inclined surface.

[0081] After processing the active layer 15, the p-doped (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer 16 with parameter x between 0.3 and 0.7 and more particular between 0.4 and 0.6. Parameter x can also be 0 which corresponds to InAlP, but may comprise values like 0.45, 0.5 and 0.55 or 0.6. Furthermore x may correspond to a varying concentration decreasing from a value like 0.7 or 0.5 to 0. Parameter y is between 0.3 and 0.7 and particularly between 0.4 and 0.6. The (Ga.sub.xAl.sub.1x).sub.yIn.sub.1yP layer 16 is selectively regrown on the top surface and also on the side surface of the active layer 15, layer 13 as well as the exposed inclined surface is 122 of protrusion 121. Thereby, the conductive layer 16 completely encapsulates the protrusion and reaches down to the hard mask layer 14.

[0082] In the exemplary embodiment of FIG. 5, the material of layer 16 on the sidewalls does not cover the hard mask layer 14 but ends short before on the sidewalls of layer 12. However, such structure can be adjusted in accordance with the respective the growth conditions. Nevertheless, the thickness of sidewalls of layer 16 as well as the area covering the inclined surface is 122 should be kept significantly smaller than on the top surface to reduce the current injection directly from the material of p-doped layer 16 into the material of the n-doped protrusion layer 121. This can be achieved by proper selecting the growth conditions and probably the doping concentration such that the resistance value along the sidewalls significantly larger than on top of layer 16.

[0083] The previous etching process illustrated in FIG. 3A) provides a better control of the shape of the optoelectronic device and minimizes any negative effect of the selective area growth at the edge of the optoelectronic device. In particular, it has been observed that different Mesa shapes, like the inclined surface 122 as illustrated provides a simpler regrowth with a larger growth condition windows compared to the vertical sidewall illustrated in FIG. 3B).

[0084] FIG. 6 finally illustrates several potential shapes for the hard mask layer 14 in a top view. FIG. 6A) shows a mask opening forming a hexagonal shape, whereby the side edges of hard mask layer 14 follow mainly the [111] lateral surfaces. In FIG. 6B) a similar hard mask opening is illustrated with the edges of the hard mask oriented along the [111] B lateral surfaces, thereby forming a triangle. In both cases, the orientation of the hard mask edge along the [111] lateral surfaces support and promotes the selective growth of the subsequent layers, thereby reducing the dislocations and crystal defects. Any potential overlap, that is when the material during the selective growth exceeds the level of the top surface of a hard mask is negligible and does not result in an increase of dislocations.

[0085] In comparison, thereto a mask opening as shown in FIG. 6C) is for a substrate with a surface not optimal, as some of the edges of the hard mask are not aligned along the direction. This requires additional restrictions during the growth process to obtain a substantially defect free growth particularly along the edges of the hard mask. However, for a substrate having a [110] or a [100] surface a mask opening with a square shape as shown in FIG. 6C) is beneficial. The edges of the hard mask can thereby be oriented along the [100] or [110] lateral surfaces, thereby forming a square or rectangle.

[0086] The proposed method provides a significantly improvement of the performance of particularly small optoelectronic devices based on the GaAlInP material which is characterized by relatively large diffusion length. The regrowth process with a bandgap material larger than the bandgap of the respective active region causes an electrical field in the proximity of the active layer edges preventing charge carrier from reaching the surface of the active layer and non-radiative recombination centres.

[0087] The proposed principle requires less process steps and may therefore not only improve the overall performance of small optoelectronic devices but also reduce the costs for the manufacturing process.