SEMICONDUCTOR DEVICES

Abstract

A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: forming a channel on a substrate, the channel including a first 2-dimensional material; forming first and second contact patterns on the channel, each of the first and second contact patterns including a second 2-dimensional material having an intercalation material disposed therein; forming first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes including a metal; forming a gate insulating layer on the substrate to cover the channel, the first and second contact patterns, and the first and second source/drain electrodes; and forming a gate electrode on a portion of the gate insulating layer, wherein a lower surface and a sidewall of the gate electrode are covered by the gate insulating layer.

2. The method of claim 1, wherein the first and second contact patterns are formed on first portions, respectively, of the channel, and wherein the gate insulating layer is formed on a second portion of the channel between the first portions of the channel.

3. The method of claim 1, wherein the gate insulating layer contacts sidewalls and upper surfaces of the first and second contact patterns and sidewalls of the first and second source/drain electrodes.

4. The method of claim 1, further comprising forming an insulating layer on the substrate, wherein the channel is formed on an upper surface of the insulating layer.

5. The method of claim 1, further comprising: forming a first contact plug on the gate electrode; and forming second and third contact plugs through the gate insulating layer to contact the first and second source/drain electrodes, respectively.

6. The method of claim 1, wherein forming the first and second contact patterns on the channel includes: forming a preliminary contact layer including the second 2-dimensional material on a second substrate; dipping the second substrate having the preliminary contact layer thereon in a container with a solvent; and transferring the preliminary contact layer onto the channel.

7. The method of claim 6, wherein the solvent includes the intercalation material.

8. The method of claim 7, wherein the solvent includes lithium (Li) or potassium (K).

9. The method of claim 6, wherein the preliminary contact layer has a multi-layered structure in which single layers are stacked in a vertical direction substantially perpendicular to an upper surface of the second substrate, each of the single layers containing atoms having a 2-dimensional crystal structure, and the intercalation material being disposed between the single layers.

10. The method of claim 1, wherein the second 2-dimensional material is substantially the same as the first 2-dimensional material.

11. The method of claim 1, wherein each of the first and second contact patterns includes a transition metal dichalcogenide (TMD) containing a transition metal and a chalcogen element.

12. The method of claim 11, wherein the transition metal includes at least one element selected from molybdenum (Mo), tungsten (W), rhenium (Re), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr) hafnium (Hf) or technetium (Tc).

13. The method of claim 11, wherein the chalcogen element includes at least one element selected from sulfur (S), selenium (Se), or tellurium (Te).

14. A method of manufacturing a semiconductor device, the method comprising: forming a channel on a substrate, the channel including a transition metal dichalcogenide (TMD) containing a transition metal and a chalcogen element; forming first and second contact patterns on the channel; forming first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes including a metal; forming a gate insulating layer on the substrate to cover the channel, the first and second contact patterns, and the first and second source/drain electrodes; and forming a gate electrode on a portion of the gate insulating layer, wherein each of the first and second contact patterns has a multi-layered structure including single layers stacked in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the single layers including a transition metal dichalcogenide (TMD), and an intercalation material being disposed between the single layers.

15. The method of claim 14, wherein the first and second contact patterns are formed on first portions, respectively, of the channel, and wherein the gate insulating layer is formed on a second portion of the channel between the first portions of the channel.

16. The method of claim 14, wherein the gate insulating layer contacts sidewalls and upper surfaces of the first and second contact patterns and sidewalls of the first and second source/drain electrodes.

17. The method of claim 14, further comprising forming an insulating layer on the substrate, wherein the channel is formed on an upper surface of the insulating layer.

18. A method of manufacturing a semiconductor device, the method comprising: forming an insulating layer on a substrate; forming a channel on the insulating layer, the channel including a first 2-dimensional material; forming first and second contact patterns on upper edge surfaces, respectively, of the channel, each of the first and second contact patterns including a second 2-dimensional material having an intercalation material disposed therein; forming first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes including a metal; forming a gate insulating layer on an upper central surface and sidewalls of the channel, sidewalls of the first and second contact patterns, and sidewalls and upper surfaces of the first and second source/drain electrodes; forming a gate electrode on a portion of the gate insulating layer on the upper central surface of the channel, wherein a lower surface and a sidewall of the gate electrode are covered by the gate insulating layer; forming a first contact plug on an upper surface of the gate electrode; and forming second and third contact plugs extending through the gate insulating layer to contact upper surfaces of the first and second source/drain electrodes, respectively.

19. The method of claim 18, wherein each of the first and second contact patterns has a multi-layered structure including single layers stacked in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the single layers including a transition metal dichalcogenide (TMD), and the intercalation material being disposed between the single layers.

20. The method of claim 18, wherein the second 2-dimensional material is substantially the same as the first 2-dimensional material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present disclosure.

[0010] FIG. 2 is a graph illustrating a total resistance of a 2-dimensional material and a total resistance of a 2-dimensional material including lithium (Li) as an intercalation material.

[0011] FIG. 3 is a graph illustrating contact resistances of a 2-dimensional material and a 2-dimensional material including lithium (Li) as an intercalation material.

[0012] FIGS. 4 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0013] FIGS. 7 and 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0014] FIG. 9 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

[0015] Example embodiments will be described in detail with reference to the accompanying drawings.

[0016] It will be understood that, although the terms first, second, and/or third may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structure and/or processes, these various materials, layers, regions, pads, electrodes, patterns, structure and/or processes should not be limited by these terms. These terms are only used to distinguish one material, layer, region, pad, electrode, pattern, structure or process from another material, layer, region, pad, electrode, pattern, structure or process. Thus, first, second and/or third may be used selectively or interchangeably for each material, layer, region, electrode, pad, pattern, structure or process respectively.

[0017] FIG. 1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present disclosure.

[0018] Referring to FIG. 1, the semiconductor device may include an insulating layer 20 on a first substrate 10, a channel 30, first and second contact patterns 42 and 44, first and second source/drain electrodes 52 and 54, a gate insulating layer 60, a gate electrode 70, an insulating interlayer 80, and first to third contact plugs 90, 92, and 94, and the gate electrode 70, the gate insulating layer 60, the channel 30, the first and second contact patterns 42 and 44, and the first and second source/drain electrodes 52 and 54 may form a transistor.

[0019] In an embodiment, the first substrate 10 may include, for example, a semiconductor material such as silicon, germanium, or silicon-germanium. The insulating layer 20 may include, for example, an insulating material such as an oxide or a nitride. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment the semiconductor device may include only an insulating substrate including an insulating material without the first substrate 10.

[0020] The channel 30 may be disposed on the insulating layer 20. In an embodiment, the channel 30 may include a 2-dimensional material, and the channel 30 may include a single layer containing atoms having a 2-dimensional crystal structure, or may have a multi-layered structure in which a plurality of single layers is stacked in a vertical direction substantially perpendicular to an upper surface of the first substrate 10.

[0021] In an embodiment, the 2-dimensional material may include a transition metal dichalcogenide (TMD) containing a transition metal and a chalcogen element, and may be represented by a chemical formula MX.sub.2 (M: transition metal, X: chalcogen element). In an embodiment, the transition metal may include, for example, at least one element selected from molybdenum (Mo), tungsten (W), renium (Re), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), and the like, and the calcogen element may include, for example, at least one element selected from sulfur (S), selenium (Se), tellurium (Te), and the like. The transition metal dichalcogenide (TMD) may include, for example, molybdenum sulfide (MoS.sub.2), tungsten sulfide (WS.sub.2), molybdenum diselenide (MoSe.sub.2), tungsten diselenide (WSe.sub.2), or the like.

[0022] The first and second contact patterns 42 and 44 may be disposed on upper edge surfaces, respectively, of the channel 30. For example, the first and second contact patterns 42, 44 may be disposed on lateral edges of the upper surface of the channel 30.

[0023] In an embodiment, each of the first and second contact patterns 42 and 44 may include a 2-dimensional material having an intercalation material inserted therein (e.g., disposed therein). The 2-dimensional material included in the first and second contact patterns 42 and 44 may be substantially the same as or different from the 2-dimensional material included in the channel 30. In an embodiment, each of the first and second contact patterns 42 and 44 may have a multi-layered structure in which single layers are stacked in the vertical direction. Each of the single layers may include the 2-dimensional material and the intercalation material may be inserted between the single layers. For example, the intercalation material may be disposed between adjacent single layers of the 2-dimensional material.

[0024] The first and second source/drain electrodes 52 and 54 may be disposed on the first and second contact patterns 42 and 44, respectively. In an embodiment, each of the first and second source/drain electrodes 52 and 54 may include, for example, a metal, a metal nitride, or a metal silicide.

[0025] The gate insulating layer 60 may be formed on a portion of the channel 30. For example, in an embodiment the gate insulating layer 60 may be formed on an upper central surface of the channel 30 not covered by the first and second contact patterns 42 and 44 and sidewalls of the channel 30. The gate insulating layer 60 may also be formed on sidewalls of the first and second contact patterns 42 and 44, sidewalls and upper surfaces of the first and second source/drain electrodes 52 and 54, and an upper surface of the insulating layer 20. In an embodiment, the gate insulating layer 60 may include, for example, silicon oxide, a metal oxide, or the like.

[0026] The gate electrode 70 may be disposed on a portion of the gate insulating layer 60 on the upper central surface of the channel 30, and a lower surface and a sidewall of the gate electrode 70 may be covered by the gate insulating layer 60. In an embodiment, the gate electrode 70 may include, for example, a metal, a metal nitride, a metal silicide, polysilicon doped with impurities, or the like.

[0027] The insulating interlayer 80 may be disposed on the insulating layer 20, and may cover the gate insulating layer 60 and the gate electrode 70. In an embodiment, the insulating interlayer 80 may include, for example, an oxide such as silicon oxide, a nitride such as silicon nitride, or a low-dielectric material.

[0028] The first contact plug 90 may extend through the insulating interlayer 80 (e.g., in a vertical direction), and may directly contact an upper surface of the gate electrode 70. The second and third contact plugs 92 and 94 may extend through the insulating interlayer 80 (e.g., in a vertical direction) and the gate insulating layer 60, and may directly contact upper surfaces of the first and second source/drain electrodes 52 and 54, respectively. In an embodiment, the first contact plug 90 may extend below an uppermost surface of the gate electrode 70 and the second and third contact plugs 92 and 94 may extend below an uppermost surface of the first and second source/drain electrodes 52 and 54, respectively. In an embodiment, each of the first to third contact plugs 90, 92, and 94 may include, for example, a metal, a metal nitride, a metal silicide, or the like.

[0029] The semiconductor device may include the first and second contact patterns 42 and 44 between the channel 30 including a 2-dimensional material and the first and second source/drain electrodes 52 and 54, respectively, including a metal, and each of the first and second contact patterns 42 and 44 may include a 2-dimensional material having an intercalation material inserted therein. Generally, the channel 30 including the 2-dimensional material may have a charge mobility that is higher than a charge mobility of a channel including silicon. However, a contact resistance with each of the first and second source/drain electrodes 52 and 54 including the metal may be relatively high.

[0030] In an embodiment, the first and second contacts patterns 42 and 44 may be disposed between the channel 30 and the first and second source/drain electrodes 52 and 54 (e.g., in a vertical direction), respectively, and the first and second contact patterns 42 and 44 may include a 2-dimensional material having an intercalation material inserted therein. Thus, the contact resistance between the channel 30 and each of the first and second source/drain electrodes 52 and 54 may be lowered.

[0031] FIG. 2 is a graph illustrating a total resistance of a 2-dimensional material and a total resistance of a 2-dimensional material including lithium (Li) as an intercalation material, and FIG. 3 is a graph illustrating contact resistances thereof.

[0032] Referring to FIG. 2, the total resistance of the 2-dimensional material including lithium (Li) as the intercalation material is less than the total resistance of the 2-dimensional material not including the intercalation material.

[0033] Accordingly, referring to FIG. 3, the contact resistance of the 2-dimensional material including lithium (Li) as the intercalation material is about of the contact resistance of the 2-dimensional material not including the intercalation material.

[0034] The semiconductor device may include the channel 30 including a 2-dimensional material with a high charge mobility, and the first and second contact patterns 42 and 44, which may include a 2-dimensional material having an intercalation material inserted therein, between the channel 30 and the first and second source/drain electrodes 52 and 54, respectively, and thus the semiconductor device may have increased electrical characteristics.

[0035] FIGS. 4 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present disclosure.

[0036] Referring to FIG. 4, the insulating layer 20 may be formed on the first substrate 10, the channel 30 may be formed on the insulating layer 20, and a contact layer 40 may be formed on the channel 30.

[0037] In an embodiment, the channel 30 may be formed on the insulating layer 20 by a chemical vapor deposition (CVD) process.

[0038] In an embodiment, the contact layer 40 may be formed by forming a preliminary contact layer including a 2-dimensional material on a second substrate and dipping the second substrate on which the preliminary contact layer is formed in a container with a solvent for a predetermined time period, and the contact layer 40 on the second substrate may be transferred to the channel 30 on the first substrate 10.

[0039] In an embodiment, the preliminary contact layer may include a 2-dimensional material substantially the same as or different from the 2-dimensional material included in the channel 30. The preliminary contact layer may have a multi-layered structure in which single layers are stack ed in a vertical direction substantially perpendicular to an upper surface of the second substrate, a nd each of the single layers may contain atoms having a 2-dimensional crystal structure.

[0040] In an embodiment, the solvent may include, for example, an intercalation material such as lithium (Li), potassium (K), or the like. For example, the solvent may include n-butyllithium (n-BuLi), tert-butyllithium (t-BuLi), methyllithium (MeLi), or the like.

[0041] The intercalation material included in the solvent may be doped in the preliminary contact layer by dipping the preliminary contact layer in the solvent for the predetermined time period, and the doped intercalation material may be inserted between the single layers included in the preliminary contact layer to form the contact layer 40.

[0042] Referring to FIG. 5, a source/drain layer may be formed on the contact layer 40, an etch mask may be formed on the source/drain layer, and the source/drain layer and the contact layer 40 may be etched by an etching process using the etch mask to form an opening 55 exposing an upper surface of the channel 30.

[0043] Accordingly, the first and second contact patterns 42 and 44 may be formed on the channel 30, and the first and second source/drain electrodes 52 and 54 may be formed on the first and second contact patterns 42 and 44, respectively.

[0044] Referring to FIG. 6, the gate insulating layer 60 may be formed on the upper surface of the insulating layer 20, the sidewalls of the channel 30, the upper surface of the channel 30 exposed by the opening 55, the sidewalls of the first and second contact patterns 42 and 44, and the sidewalls and upper surfaces of the first and second source/drain electrodes 52 and 54. The gate electrode 70 may be formed on the gate insulating layer 60 filling a remaining portion of the opening 55.

[0045] Referring to FIG. 1 again, the insulating interlayer 80 may be formed on the insulating layer 20 to cover the gate electrode 70 and the gate insulating layer 60, the first contact plug 90 may be formed through the insulating interlayer 80 to directly contact an upper surface of the gate electrode 70, and the second and third contact plugs 92 and 94 may be formed through the insulating interlayer 80 and the gate insulating layer 60 to directly contact upper surfaces of the first and second source/drain electrodes 52 and 54, respectively.

[0046] The manufacturing of the semiconductor device may be completed by the processes described above.

[0047] FIGS. 7 and 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present disclosure. This method may include processes substantially the same as or similar to the processes illustrated with reference to FIGS. 4 to 6 and FIG. 1, and repeated explanations thereof are omitted herein for convenience of explanation.

[0048] Referring to FIG. 7, processes substantially the same as or similar to the processes illustrated with reference to FIG. 4 may be performed to form the insulating layer 20 and the channel 30 on the first substrate 10.

[0049] A mask 35 may be formed on the channel 30. In an embodiment, a spin coating process may be performed to dope an intercalation material into upper portions of the channel 30 so that the first and second contact patterns 42 and 44 may be formed.

[0050] In the spin coating process, the solvent illustrated with reference to FIG. 4 may be used, and lithium or potassium atoms included in the solvent may be inserted between the single layers in the channel 30 including the 2-dimensional material.

[0051] The mask 35 may then be removed.

[0052] Referring to FIG. 8, processes similar to the processes illustrated with reference to FIG. 5 may be performed.

[0053] For example, the source/drain layer may be formed on the channel 30 and the first and second contact patterns 42 and 44, the etch mask may be formed on the source/drain layer, and the source/drain layer and an upper portion of the channel 30 between the first and second contact patterns 42 and 44 may be etched by an etching process using the etch mask to form the opening 55 exposing an upper surface of a lower portion of the channel 30.

[0054] Accordingly, the first and second contact patterns 42 and 44 may be formed on lower portions, respectively, of the remaining channel 30, and the first and second source/drain electrodes 52 and 54 may be formed on the first and second contact patterns 42 and 44, respectively.

[0055] The manufacturing of the semiconductor device may be completed by the processes illustrated with reference to FIGS. 6 and 1.

[0056] FIG. 9 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present inventive concept.

[0057] The semiconductor device may be substantially the same as or similar to the semiconductor device illustrated with reference to FIG. 1, except that the channel and contact patterns include substantially the same material. Accordingly, like reference numerals refer to like elements, and repeated explanations thereof are omitted herein for convenience of explanation.

[0058] Referring to FIG. 9, the channel 30 and the first and second contact patterns 42 and 44 included in the semiconductor device may include substantially the same material, particularly, the 2-dimensional material having the intercalation material inserted therein. Accordingly the channel 30 and the first and second contact patterns 42 and 44 may be integrally formed.

[0059] As the channel 30 includes the 2-dimensional material, the channel 30 may have a charge mobility that is higher than a charge mobility of a channel including silicon. As the first and second contact patterns 42 and 44 are integrally formed with the channel 30 include the 2-dimenstion material having a intercalation material inserted therein, the first and second contact patterns 42 and 44 may have a contact resistance with the first and second source/drain electrodes 52 and 54 that is less than a contact resistance of first and second contact patterns including only a 2-dimensional material.

[0060] The semiconductor device may be formed by dipping the first substrate 10 on which the channel 30 is formed in a solvent for a predetermined time, instead of dipping the second substrate on which the preliminary contact layer is formed, among the processes illustrated with reference to FIG. 4, and thus the intercalation material included in the solvent may be doped into the channel 30 to be inserted between the single layers included in the channel 30. Accordingly, the channel 30 may include substantially the same material as the contact layer 40.

[0061] Like the processes illustrated with reference to FIG. 5, the source/drain layer may be formed on the channel 30, the etch mask may be formed on the source/drain layer, and the source/drain layer and the upper portion of the channel 30 may be etched by an etching process using the etch mask to form the opening 55 exposing the upper surface of the lower portion of the channel 30.

[0062] Upper portions of the channel 30 remaining on the lower portion of the channel 30 may be referred to as the first and second contact patterns 42 and 44, respectively, and the first and second source/drain electrodes 52 and 54 may be formed on the first and second contact patterns 42 and 44, respectively.

[0063] The manufacturing of the semiconductor device may be completed by the processes illustrated with reference to FIGS. 6 and 1.

[0064] While non-limiting embodiments have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the present disclosure.