BACKGROUND DAC ERROR CALIBRATION FOR SAR ADCS

Abstract

An analog-to-digital converter (ADC) includes bit trial circuitry configured to perform ADC bit trials that compare an input signal to states of weighted circuit elements, a dither digital-to-analog converter (DAC) to receive a dither sequence and apply a dither signal to the bit trial circuitry, and calibration circuitry. The calibration circuitry is configured to input a dither sequence into the ADC bit trials as dithered bit trials; determine an effect of the dither sequence on results of the dithered bit trials; and update correction factors used to adjust results of the ADC bit trials using the determined effect of the dither sequence.

Claims

1. An analog-to-digital converter (ADC) comprising: bit trial circuitry configured to perform ADC bit trials that compare an input signal to states of weighted circuit elements; a dither digital-to-analog converter (DAC) to receive a dither sequence and apply a dither signal to the bit trial circuitry; and calibration circuitry configured to: input a dither sequence into the ADC bit trials as dithered bit trials; determine an effect of the dither sequence on results of the dithered bit trials; and update correction factors used to adjust results of the ADC bit trials using the determined effect of the dither sequence.

2. The ADC of claim 1, wherein the calibration circuitry is configured to: compute a midpoint for the dithered bit trials; compare results of the dithered bit trials to the midpoint to measure instantaneous errors in the dithered bit trials; and recurrently initiate dithered bit trials to determine the updated correction factors based on the measured instantaneous errors.

3. The ADC of claim 2, wherein the calibration circuitry includes: a memory to store correction factors for the ADC bit trials; and logic circuitry configured to: map ADC bit trial outputs to the updated correction factors; and adjust results of the ADC bit trials using the updated correction factors.

4. The ADC of claim 3, wherein the logic circuitry includes an accumulator configured to receive the instantaneous errors in the dithered bit trials and produce a value of convergence of the instantaneous errors in the dithered bit trials; and wherein the calibration circuitry is configured to calibrate the ADC by mapping the value of convergence of the instantaneous errors to the updated correction factors.

5. The ADC of claim 2, wherein the calibration circuitry includes logic circuitry configured to: adjust results of the ADC bit trials using the updated correction factors; and recurrently initiate the dithered bit trials to recurrently update the corrections factors toward a calibration corrections factor solution.

6. The ADC of claim 2, wherein the calibration circuitry is configured to: determine one or both of dither bit trial result maximums and minimums for a first dither sequence value; determine one or both of dither bit trial result maximums and minimums for a second dither sequence value; and compute an average of the one or both of dither bit trial result maximums and minimums determined for the first and second dither sequence values as the midpoint for the dithered bit trials.

7. The ADC of claim 2, wherein the calibration circuitry is configured to use pseudo-random noise as the midpoint for the dithered bit trials.

8. The ADC of claim 1, wherein the ADC is a multi-bit successive approximation register ADC (SAR ADC), and the calibration circuitry is configured to perform the dithered bit trials and calibrate the correction factors for the SAR ADC.

9. The ADC of claim 1, wherein the calibration circuitry is configured to perform the dithered bit trials parallel to the ADC bit trials.

10. A method of calibration of an analog-to-digital converter (ADC), the method comprising: performing ADC bit trials for an analog-to-digital (A/D) conversion of an input signal, wherein an ADC bit trial includes comparing the input signal to a state of a weighted circuit element; inputting a dither sequence into the ADC bit trials as dithered bit trials; determining an effect of the dither sequence on results of the dithered bit trials; and updating correction factors for the ADC bit trials using the determined effect of the dither sequence.

11. The method of claim 10, wherein the determining the effect of the dither sequence includes: determining a midpoint for the dithered bit trials; measuring instantaneous errors in the dithered bit trials by comparing results of the dithered bit trials to the midpoint for values of the dither sequence; and determining updated correction factors based on the measured instantaneous errors in the dithered bit trials.

12. The method of claim 11, wherein the updating the correction factors includes: mapping ADC bit trial outputs to the updated correction factors.

13. The method of claim 12, including: determining a value of convergence of the instantaneous errors in the dithered bit trials by accumulating the instantaneous errors in the dithered bit trials; and calibrating the ADC by mapping the value of convergence of the instantaneous errors to the updated correction factors.

14. The method of claim 11, including: adjusting results of the ADC bit trials using the updated correction factors; and repeating the dithered bit trials and reducing the determined error in the ADC bit trials by updating the correction factors.

15. The method of claim 11, wherein the determining the midpoint for the dithered bit trials includes: determining one or both of bit trial result maximums and minimums for a first dither sequence value; determining one or both of bit trial result maximums and minimums for a second dither sequence value; and averaging the determined one or both of bit trial result maximums and minimums for the first and second dither sequence values.

16. The method of claim 11, wherein the determining the midpoint for the dithered bit trials includes using pseudo-random noise as the midpoint for the dithered bit trials.

17. The method of claim 10, including performing the dithered bit trials parallel to the ADC bit trials.

18. A non-transitory computer readable storage medium including instructions, that when performed using a controller for calibration circuitry of an analog-to-digital converter (ADC) cause the calibration circuitry to perform acts comprising: initiating dithered bit trials of the ADC, wherein a dithered bit trial inputs a dither sequence into ADC bit trials that include comparing an input signal to a state of a weighted circuit element of the ADC; determining a midpoint for the dithered bit trials; determining instantaneous errors in the dithered bit trials by comparing results of the dithered bit trials to the midpoint for values of the dither sequence; determining an error in the ADC bit trials using a determined convergence of the instantaneous errors in the dithered bit trials; and updating correction factors for the ADC bit trials according to the determined error in the ADC bit trials.

19. The non-transitory computer readable storage medium of claim 18, further including instructions that when performed by the controller, cause the calibration circuitry to perform acts including: determining bit trial result maximums and minimums for a first dither sequence value; determining bit trial result maximums and minimums for a second dither sequence value; and averaging the determined bit trial result maximums and minimums for the first and second dither sequence values as the midpoint for the dithered bit trials.

20. The non-transitory computer readable storage medium of claim 18, further including instructions that when performed by the controller, cause the calibration circuitry to perform acts including: determining a value of convergence of the instantaneous errors in the dithered bit trials by accumulating the instantaneous errors in the dithered bit trials; and mapping the value of convergence of the instantaneous errors to updated correction factors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

[0005] FIG. 1 is a diagram of an example of a successive approximation register analog-to-digital converter (SAR ADC).

[0006] FIG. 2 is a diagram of an example of operation of a SAR ADC.

[0007] FIGS. 3A and 3B are illustrations of effects of weighting errors in a digital-to-analog converter (DAC) elements of a SAR ADC.

[0008] FIGS. 4 and 5 are diagrams of further example models of a SAR ADC.

[0009] FIG. 6 is a graph of examples of transfer curves for ADCs.

[0010] FIG. 7 is a diagram of another example of a SAR ADC.

[0011] FIGS. 8A and 8B are graphs showing examples of transfer curves for the SAR ADC example of FIG. 7.

[0012] FIG. 9 is a graph illustrating an example of a computation useful for calibrating an ADC.

[0013] FIG. 10 shows graphs showing examples of transfer functions for different types of error in a SAR ADC.

[0014] FIG. 11 is a diagram of an example of a circuit to detect instantaneous error in operation of a SAR ADC.

[0015] FIG. 12 is a diagram of an example of a SAR ADC model and calibration circuitry.

[0016] FIG. 13 is a diagram of another example of a circuit to detect instantaneous error in operation of a SAR ADC.

[0017] FIG. 14 is a diagram of another example of a model of a SAR ADC.

[0018] FIG. 15 is a flow diagram of an example of a method to calibrate a SAR ADC.

DETAILED DESCRIPTION

[0019] FIG. 1 is a diagram of an example of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC 102 includes a digital-to-analog converter (DAC) 104 with L1 DAC elements (where L is a positive integer greater than one and is the number of conversion trials of the SAR ADC), a comparator 106, and logic circuitry that can include a SAR finite state machine (SAR FSM) 108. The input x.sub.n is the analog input signal to be converted and y.sub.n is the digital ADC output. The DAC elements can be weighted DAC elements with weights (.sub.L1, . . . , .sub.1).

[0020] FIG. 2 is a diagram of an example of operation of a 5-bit binary-weighted SAR ADC. As part of the successive approximation routine, bit trials are performed iteratively. In a bit trial, the outputs of the weighted DAC elements are applied to the inputs of the comparator 106. Based on the output of the comparator 106, the bit of the digital value corresponding to a DAC element is assigned a logic value 1 or a logic value 0. Conversion then proceeds to the next trial until all bits of the digital value are determined.

[0021] FIGS. 3A and 3B are graphs illustrating the effects of errors in the weighting of the DAC elements. For instance, in the case of capacitive DAC arrays, there may be inaccuracies in the capacitance values in the weighting of the DAC elements. FIG. 3A shows the input x(t) as an input increasing linearly, and FIG. 3B shows the problem that can occur in the output y.sub.n when there are errors in the weighting. The increase in the output for increasing digital values may not be linear and may cause harmonic distortion in the application. One approach to address errors in the DAC elements is to calibrate the bit trials of the ADC. The calibration changes the decision point of the bit trials to address errors in the weighting of the DAC elements used in the bit trials.

[0022] FIG. 4 is a diagram of another example of a model of a SAR ADC 402. The SAR ADC model 402 is equivalent to the SAR ADC 102 of FIG. 1 except that a portion of bit trial logic 410 is shown isolated from the rest of the SAR ADC 412. The output of the comparator 406 is interpreted as 1 and the bit trial logic 410 adds or subtracts one half the weight of DAC element L1 (.sub.L1) to output y.sub.n according to the output of the comparator q.sub.n and the output of the rest of the SAR ADC 412.

[0023] FIG. 5 is an illustration of an example of DAC element error on the SAR ADC 402. In FIG. 5 all but the most significant bit DAC element .sub.L1 and its associated trial logic is represented by a back-end ADC 412. In the example of FIG. 5, the DAC element .sub.L1 introduces an error e.sub.n in its bit trials due to error in its weighting. The error e.sub.n is e.sub.+1 when the output of comparator q.sub.n is +1, and the error e.sub.n is e.sub.1 when the output of comparator q.sub.n is 1. With error e.sub.n, instead of adjusting the result by +.sub.L1 when the output of the comparator is q.sub.n=+1, the result is ideally adjusted by +.sub.L1+(1/.sub.0)e.sub.+1 (where 1/.sub.0 is a scaling factor), and when the output of the comparator is q.sub.n=1, the result is adjusted by .sub.L1+(1/A.sub.0)e.sub.1 instead of .sub.L1.

[0024] FIG. 6 is graph of a transfer curve of output y.sub.n vs. input x.sub.n showing the ideal transfer curve 614 without the error and the actual transfer curve 616 with the error e.sub.n. The left portion of the graph shows that adjusting the result of bit trials with +(1/.sub.0)e.sub.1 when q.sub.n=1 brings the result back to ideal, and the right portion of the graph shows that adjusting the result of bit trials with +(1/.sub.0)e.sub.+1 when q.sub.n=+1 brings the result back to ideal. The example in FIG. 6 shows that calibrating the bit trials of the DAC elements with a correction factor may bring the performance of the ADC closer to ideal and reduce distortion in the A/D conversions. A challenge is knowing when the error places the actual result greater than ideal or less than ideal.

[0025] FIG. 7 is a diagram of another example of a SAR ADC 702. The ADC of FIG. 7 is the ADC of FIG. 5 modified to include a dither DAC 720. The dither DAC injects a known two-level dither sequence that takes on values +1 and 1 at the input to the ADC. The dither is subtracted out at 722 (e.g., with a lookup table) to prevent corrupting the ADC output. The effect of the dither is leveraged to expose the error canceled by calibration.

[0026] FIG. 8A is a graph showing transfer curves of node z.sub.n of the ADC in FIG. 7 versus the input x.sub.n. The graph shows a plot of the transfer curve 824 for no dither added, the transfer curve 826 for dither d.sub.n set to 1, and the transfer curve 828 for the dither d.sub.n set to +1.

[0027] FIG. 8B is a graph showing the effect on the transfer curve of y.sub.n versus x.sub.n of adding the dither sequence and then canceling the dither sequence. A transfer curve 830 for d.sub.n=1 and a transfer curve 832 for d.sub.n=+1 are shown. The graph shows a region that is a gap at an approximate midpoint between the transfer curves. For the ADC output y.sub.n, there is a higher probability that y.sub.n will be greater than (y.sub.n>) when the dither value d.sub.n=+1, and there is a higher probability that y.sub.n will be less than (y.sub.n<) when the dither value d.sub.n=1. Thus, the dither sequence causes an imbalance in probability of the output of the ADC. Because the dither sequence is known, the effect of errors in the ADC on the imbalance allows for the error to be extracted and corrected by calibration.

[0028] The calibration process includes the following steps. The midpoint is computed, the instantaneous error polarity is determined, and the correction coefficients or correction factors for the calibration are determined. The correction factors are used to correct for the errors e.sub.+1 and e.sup.1 discussed previously herein to reduce the error. The calibration process can be run in the background of the operation of the ADC and the correction factors can be recurrently updated (e.g., periodically according to a schedule).

[0029] FIG. 9 is an illustration of a graphical method of computing the midpoint . The computation is based on the measured minimums and maximums of y.sub.n determined for the comparator decisions q.sub.n and the dither sequence values d.sub.n. The minimum output y.sub.n for q.sub.n=+1 and d.sub.n=1 is measured, the maximum output y.sub.n for q.sub.n=1 and d.sub.n=1 is measured, the minimum y.sub.n for q.sub.n=+1 and d.sub.n=+1 is measured, and the maximum y.sub.n for q.sub.n=1 and d.sub.n=+1 is measured. The midpoint is the average of some or all of the measured minimums and maximums. The minimums and maximums can be determined in the digital domain from monitoring when y.sub.n equals a maximum or minimum over a specified period of time. Once the midpoint is determined, the dither sequence causes an imbalance in y.sub.n, and y.sub.n will have a greater probability of being higher or lower than depending on the value of the dither sequence d.sub.n. This imbalance can be detected to determine the polarity of the error.

[0030] FIG. 10 shows graphs of transfer functions of y.sub.n versus x.sub.n for different error polarities. FIG. 11 is a diagram of a circuit to extract the error polarity. The circuit includes a comparator 1140 and a block accumulator 1142. The negative input to the comparator 1140 is the midpoint and the positive input to the comparator is y.sub.n. The output of the block accumulator 1142 is a number that will tend to be negative or positive depending on the error polarity. The output of the block accumulator 1142 is a measure of the instantaneous error. When the midpoint is computed and the instantaneous error is determined, the correction factors for the calibration can be updated.

[0031] FIG. 12 is a diagram of calibration circuitry to produce correction factors to calibrate the SAR ADC 702. The calibration circuitry can include a microcontroller 1244 (C) or other logic circuitry (e.g., a microprocessor etc.) to perform the functions described. Block 1246 identifies the maximums and minimums of y.sub.n for values of q.sub.n and d.sub.n and block 1248 computes the midpoint . Blocks 1246 and 1248 may be a separate circuit from the microcontroller 1244 or may be included in the microcontroller 1244. Block accumulator 1142 provides the measured instantaneous error to the microcontroller 1244.

[0032] The instantaneous error output from the block accumulator 1142 is input to accumulator 1250. The output of accumulator 1250 goes up or down based on its input. For measurement cycle after cycle the instantaneous error gets smaller and eventually goes to zero on average. The result is the output of the accumulator 1250 converges to a break estimate bp (=e.sub.+1e.sub.1). The converged solution b.sub.p is used to map the error to correction factors (e.g., using a look up table stored in a memory of the microcontroller 1244). At block 1252, the correction factors +(1/.sub.0)e.sub.+1,p and +(1/.sub.0)e.sub.1,p are used to modify the bit trial results +.sub.L1 and .sub.L1, respectively. The correction factors are recurrently updated and used to adjust results of the ADC bit trials.

[0033] FIG. 13 is an alternative circuit used to determine the instantaneous error. The circuit uses pseudo-random noise as the midpoint for the dithered bit trials. The Blocks 1246 and 1248 in FIG. 12 are replaced by a multi-bit linear feedback shift register (LFSR) 1354. The result is a noisy zero-mean sequence that is used for the midpoint instead of the averaging of the determined minimum and maximums of y.sub.n.

[0034] FIG. 14 is a diagram of another example of a model of a SAR ADC 402. The example of FIG. 14 is similar to the example of FIG. 4, but FIG. 14 shows the first DAC element .sub.L1 and the second DAC element .sub.L2 isolated from the rest of the system. In the first bit trail, a dither sequence is injected into summing node 1454 as described regarding FIG. 7 to calibrate the first bit trial. In the second bit trial, a dither sequence is injected into summing node 1456 to calibrate the second bit trial. A dither sequence is injected similarly for calibration of the remaining bit trials. Summing node 1454 and summing node 1456 are physically the same summing node, but they can be treated as different summing nodes from an operation point of view.

[0035] For completeness, FIG. 15 is a flow diagram of an example of a method of calibration of a SAR ADC. The method can be performed using the example ADC and calibration circuitry of FIG. 12. At block 1505, ADC bit trials for an analog-to-digital (A/D) conversion of an input signal are performed. An ADC bit trial includes comparing the input signal to a state of a weighted circuit element (e.g., a weighted DAC). At block 1510, a dither sequence is input into the ADC bit trials as dithered bit trials. At block 1515, an effect of the dither sequence on results of the dithered bit trials is determined. Another effect of the dither sequence is removed from the results of the dithered ADC bit trials. At block 1520, correction factors for calibration of the ADC are determined using the determined effect of the dither sequence on the ADC bit trials. The correction factors are used to modify ADC bit trial results to remove the effect of error in the A/D conversions by the ADC.

[0036] The techniques described herein reduce errors associated with ADCs through calibration. The techniques allow calibration to run in the background or parallel with the operation of the ADCs without interrupting normal ADC operation. The impact of the calibration on operation of the ADC is minimal and thus the techniques are suitable for high-speed designs.

ADDITIONAL DESCRIPTION AND ASPECTS

[0037] In a first Aspect (Aspect 1) an ADC comprises bit trial circuitry configured to perform ADC bit trials that compare an input signal to states of weighted circuit elements; a dither digital-to-analog converter (DAC) to receive a dither sequence and apply a dither signal to the bit trial circuitry; and calibration circuitry. The calibration circuitry is configured to input a dither sequence into the ADC bit trials as dithered bit trials; determine an effect of the dither sequence on results of the dithered bit trials; and update correction factors used to adjust results of the ADC bit trials using the determined effect of the dither sequence.

[0038] In Aspect 2, the subject matter of Aspect 1 optionally includes calibration circuitry configured to compute a midpoint for the dithered bit trials, compare results of the dithered bit trials to the midpoint to measure instantaneous errors in the dithered bit trials, and recurrently initiate dithered bit trials to determine the updated correction factors based on the measured instantaneous errors.

[0039] In Aspect 3, the subject matter of Aspect 2 optionally includes calibration circuitry that includes a memory to store correction factors for the ADC bit trials and logic circuitry. The logic circuitry is configured to map ADC bit trial outputs to the updated correction factors and adjust results of the ADC bit trials using the updated correction factors.

[0040] In Aspect 4, the subject matter of Aspect 3 optionally includes logic circuitry that includes an accumulator configured to receive the instantaneous errors in the dithered bit trials and produce a value of convergence of the instantaneous errors in the dithered bit trials. The calibration circuitry is configured to calibrate the ADC by mapping the value of convergence of the instantaneous errors to the updated correction factors.

[0041] In Aspect 5, the subject matter of one or any combination of Aspects 2-4 optionally includes calibration circuitry with logic circuitry configured to adjust results of the ADC bit trials using the updated correction factors, and recurrently initiate the dithered bit trials to recurrently update the corrections factors toward a calibration corrections factor solution.

[0042] In Aspect 6, the subject matter of one or any combination of Aspects 2-5 optionally includes calibration circuitry configured to determine one or both of dither bit trial result maximums and minimums for a first dither sequence value, determine one or both of dither bit trial result maximums and minimums for a second dither sequence value, and compute an average of the one or both of dither bit trial result maximums and minimums determined for the first and second dither sequence values as the midpoint for the dithered bit trials.

[0043] In Aspect 7, the subject matter of one or any combination of Aspects 2-6 optionally includes calibration circuitry configured to use pseudo-random noise as the midpoint for the dithered bit trials.

[0044] In Aspect 8, the subject matter of one or any combination of Aspects 1-7 optionally includes the ADC being a multi-bit successive approximation register ADC (SAR ADC), and the calibration circuitry is configured to perform the dithered bit trials and calibrate the correction factors for the SAR ADC.

[0045] In Aspect 9, the subject matter of one or any combination of Aspects 1-8 optionally includes calibration circuitry configured to perform the dithered bit trials parallel to the ADC bit trials.

[0046] Aspect 10 includes subject matter (such as a method of calibration of an ADC) or can optionally be combined with one or any combination of Aspects 1-9 to include such subject matter, comprising performing ADC bit trials for an analog-to-digital (A/D) conversion of an input signal, wherein an ADC bit trial includes comparing the input signal to a state of a weighted circuit element, inputting a dither sequence into the ADC bit trials as dithered bit trials, determining an effect of the dither sequence on results of the dithered bit trials, and updating correction factors for the ADC bit trials using the determined effect of the dither sequence.

[0047] In Aspect 11, the subject matter of Aspect 10 optionally includes determining a midpoint for the dithered bit trials, measuring instantaneous errors in the dithered bit trials by comparing results of the dithered bit trials to the midpoint for values of the dither sequence, and determining updated correction factors based on the measured instantaneous errors in the dithered bit trials.

[0048] In Aspect 12, the subject matter of Aspect 11 optionally includes mapping ADC bit trial outputs to the updated correction factors.

[0049] In Aspect 13, the subject matter of Aspect 12 optionally includes determining a value of convergence of the instantaneous errors in the dithered bit trials by accumulating the instantaneous errors in the dithered bit trials and calibrating the ADC by mapping the value of convergence of the instantaneous errors to the updated correction factors.

[0050] In Aspect 14, the subject matter of one or any combination of Aspects 11-13 optionally includes adjusting results of the ADC bit trials using the updated correction factors, and repeating the dithered bit trials and reducing the determined error in the ADC bit trials by updating the correction factors.

[0051] In Aspect 15, the subject matter of one or any combination of Aspects 11-14 optionally includes determining one or both of bit trial result maximums and minimums for a first dither sequence value, determining one or both of bit trial result maximums and minimums for a second dither sequence value, and averaging the determined one or both of bit trial result maximums and minimums for the first and second dither sequence values.

[0052] In Aspect 16, the subject matter of one or any combination of Aspects 11-15 optionally includes using pseudo-random noise as the midpoint for the dithered bit trials.

[0053] In Aspect 17, the subject matter of one or any combination of Aspects 11-16 optionally includes performing the dithered bit trials parallel to the ADC bit trials.

[0054] Aspect 18 includes subject matter (or can optionally be combined with one or any combination of Aspects 1-17 to include such subject matter) such as a computer readable storage medium including instructions, that when performed using a controller for calibration circuitry of an analog-to-digital converter (ADC) cause the calibration circuitry to perform acts comprising initiating dithered bit trials of the ADC, wherein a dithered bit trial inputs a dither sequence into ADC bit trials that include comparing an input signal to a state of a weighted circuit element of the ADC; determining a midpoint for the dithered bit trials; determining instantaneous errors in the dithered bit trials by comparing results of the dithered bit trials to the midpoint for values of the dither sequence; determining an error in the ADC bit trials using a determined convergence of the instantaneous errors in the dithered bit trials; removing an effect of the dither sequence from results of the dithered bit trials; and updating correction factors for the ADC bit trials according to the determined error in the ADC bit trials.

[0055] In Aspect 19, the subject matter of Aspect 18 optionally further includes instructions that cause the calibration circuitry to determine bit trial result maximums and minimums for a first dither sequence value, determine bit trial result maximums and minimums for a second dither sequence value, and average the determined bit trial result maximums and minimums for the first and second dither sequence values as the midpoint for the dithered bit trials.

[0056] In Aspect 20, the subject matter of one or both of Aspects 18 and 19 optionally further includes instructions that cause the calibration circuitry to determine a value of convergence of the instantaneous errors in the dithered bit trials by accumulating the instantaneous errors in the dithered bit trials; and map the value of convergence of the instantaneous errors to updated correction factors.

[0057] These non-limiting Aspects can be combined in any permutation or combination. The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as examples. All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0058] In this document, the terms a or an are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of at least one or one or more. In this document, the term or is used to refer to a nonexclusive or, such that A or B includes A but not B, B but not A, and A and B, unless otherwise indicated. In the appended claims, the terms including and in which are used as the plain-English equivalents of the respective terms comprising and wherein. Also, in the following claims, the terms including and comprising are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms first, second, and third, etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Method examples described herein can be machine or computer-implemented at least in part.

[0059] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. 1.72 (b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.