Charger with power pulsation absorption circuit and controller for same

Abstract

A charger includes: a rectifier including input terminals, a cathode terminal and an anode terminal, wherein the input terminals are configured for connection to an AC power supply; a DC/DC converter including a first terminal, a second terminal and output terminals, the first terminal being configured to be connected to the cathode terminal of the rectifier, the second terminal being configured to be connected to the anode terminal of the rectifier, wherein the output terminals are configured for connection to a battery; and a power pulsation absorbing circuit including a first to third diodes, an inductor, a capacitor, a first switch and a second switch, wherein the DC/DC converter, the first and second switch are controlled to obtain a constant sum of a power outputted from the AC power supply and a power outputted from the capacitor during increasing a voltage outputted from the AC power supply.

Claims

1. A charger comprising: a rectifier including two input terminals, a cathode terminal and an anode terminal, wherein the two input terminals are configured for connection to an AC power supply; a DC/DC converter including a first terminal, a second terminal and two output terminals, the first terminal being configured to be connected to the cathode terminal of the rectifier via a first line, the second terminal being configured to be connected to the anode terminal of the rectifier via a second line, wherein the output terminals are configured for connection to a battery; a power pulsation absorbing circuit including a first diode, a second diode, a third diode, an inductor, a capacitor, a first switch and a second switch; and a controller configured to control switching of a switch of the DC/DC converter and switching of the first switch and the second switch; wherein the first diode is connected between the inductor of the power pulsation absorbing circuit and one of the two input terminals of the rectifier, and the second diode is connected between the inductor and another of the two input terminals of the rectifier, wherein the capacitor and the first switch are connected in series between the first line and the second line, wherein the first switch is connected to the first line and the capacitor is arranged between the second line and the first switch, wherein the third diode is connected between the inductor of the power pulsation absorbing circuit and a line which connects the capacitor to the first switch, wherein the second switch is connected between the second line and a line which connects the inductor of the power pulsation absorbing circuit to the third diode, wherein a first formula is defined as (v.sub.recV.sub.dc)i.sub.rec+V.sub.cV.sub.dc)i.sub.c<0, and a second formula is defined as (V.sub.recV.sub.dc)i.sub.rec+(V.sub.c+v.sub.dc)i.sub.c<0, wherein V.sub.rec indicates an output voltage of the rectifier, i.sub.rec indicates a current outputted by the rectifier, V.sub.dc indicates an output voltage of the charger, V.sub.c indicates a voltage applied to the capacitor, and i.sub.c indicates a current outputted by the capacitor, wherein, when neither of the first formula or the second formula is fulfilled during a voltage increase operation of increasing a voltage outputted from the AC power supply, the controller is configured to control the switch of the DC/DC converter, the first switch and the second switch by means of a first control to obtain a constant sum of a power outputted from the AC power supply and a power outputted from the capacitor, wherein, when the first formula is fulfilled and the second formula is not fulfilled during the voltage increase operation of increasing the voltage outputted from the AC power supply, the controller is configured to control the switch of the DC/DC converter, the first switch and the second switch by means of a second control to obtain a constant sum of the power outputted from the AC power supply and the power outputted from the capacitor, the second control being different from the first control, and wherein, when both of the first formula and the second formula are fulfilled during the voltage increase operation of increasing the voltage outputted from the AC power supply, the controller is configured to control the switch of the DC/DC converter, the first switch and the second switch by means of a third control to obtain a constant sum of the power outputted from the AC power supply and the power outputted from the capacitor, the third control being different from both of the first control and the second control.

2. The charger according to claim 1, wherein the controller is configured to control the switch of the DC/DC converter, the first switch and the second switch to obtain a larger voltage applied to the capacitor than an output voltage of the rectifier.

3. The charger according to claim 1, wherein the controller is configured to: control the switch of the DC/DC converter, the first switch and the second switch to charge a portion of the power outputted from the AC power supply into the capacitor during a charging phase, wherein in the charging phase, an instantaneous power outputted from the AC power supply is higher than an average power outputted from the AC power supply, and control the switch of the DC/DC converter, the first switch and the second switch to discharge a power charged in the capacitor during a discharging phase, wherein in the discharging phase, the instantaneous power outputted from the AC power supply is lower than the average power outputted from the AC power supply.

4. The charger according to claim 2, wherein the controller is configured to: control the switch of the DC/DC converter, the first switch and the second switch to charge a portion of the power outputted from the AC power supply into the capacitor during a charging phase, wherein in the charging phase, an instantaneous power outputted from the AC power supply is higher than an average power outputted from the AC power supply, and control the switch of the DC/DC converter, the first switch and the second switch to discharge a power charged in the capacitor during a discharging phase, wherein in the discharging phase, the instantaneous power outputted from the AC power supply is lower than the average power outputted from the AC power supply.

5. The charger according to claim 3, wherein the controller is configured to maintain an off-state of the second switch during the discharging phase.

6. The charger according to claim 4, wherein the controller is configured to maintain an off-state of the second switch during the discharging phase.

7. The charger according to claim 5, wherein the controller is configured to control switching of the switch of the DC/DC converter and the first switch to obtain an operation waveform of the inductor of the DC/DC converter which is approximable by a rectangular waveform.

8. The charger according to claim 6, wherein the controller is configured to control switching of the switch of the DC/DC converter and the first switch to obtain an operation waveform of the inductor of the DC/DC converter which is approximable by a rectangular waveform.

9. The charger according to claim 7, wherein the controller is configured to change switching frequencies of the switch of the DC/DC converter and the first switch during one period of an AC voltage inputted from the AC power supply.

10. The charger according to claim 8, wherein the controller is configured to change switching frequencies of the switch of the DC/DC converter and the first switch during one period of an AC voltage inputted from the AC power supply.

11. The charger according to claim 9, wherein the controller is configured to control values of the switching frequencies of the switch of the DC/DC converter and the first switch such that no period exists in which the switch of the DC/DC converter and the first switch are all switched off.

12. The charger according to claim 10, wherein the controller is configured to control values of the switching frequencies of the switch of the DC/DC converter and the first switch such that no period exists in which the switch of the DC/DC converter and the first switch are all switched off.

13. The charger according to claim 9, wherein the controller is configured to control a set value of a peak value of the rectangular waveform to obtain a minimum value of the switching frequencies which is equal to a predetermined value.

14. The charger according to claim 11, wherein the controller is configured to control a set value of a peak value of the rectangular waveform to obtain a minimum value of the switching frequencies which is equal to a predetermined value.

15. The charger according to claim 1, wherein the DC/DC converter is configured as a DAB (Dual Active Bridge) converter.

16. The charger according to claim 2, wherein the DC/DC converter is configured as a DAB (Dual Active Bridge) converter.

17. The charger according to claim 3, wherein the DC/DC converter is configured as a DAB (Dual Active Bridge) converter.

18. The charger according to claim 5, wherein the DC/DC converter is configured as a DAB (Dual Active Bridge) converter.

19. The charger according to claim 7, wherein the DC/DC converter is configured as a DAB (Dual Active Bridge) converter.

20. The charger according to claim 9, wherein the DC/DC converter is configured as a DAB (Dual Active Bridge) converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a charger 100 according to an embodiment of the present invention;

(2) FIG. 2 shows a relation between an instantaneous power p.sub.s outputted from an AC power supply and an instantaneous power p.sub.c outputted from a buffer capacitor Cbuf;

(3) FIG. 3 shows states of each of switches in various modes;

(4) FIG. 4 shows an operation waveform i.sub.L of an inductor L of a DC/DC converter 120 according to the embodiment and a corresponding equivalent rectangular waveform i.sub.L (voltage decrease sequence);

(5) FIG. 5 shows an example for calculation of duty cycles of various phases according to a conventional control method;

(6) FIG. 6 shows an operation waveform i.sub.L of an inductor L of a DC/DC converter 120 according to the embodiment and a corresponding equivalent rectangular waveform i.sub.L (voltage increase sequence I);

(7) FIG. 7 shows states of each of switches in various modes;

(8) FIG. 8 shows an operation waveform i.sub.L of an inductor L of a DC/DC converter 120 according to the embodiment and a corresponding equivalent rectangular waveform i.sub.L (voltage increase sequence II); and

(9) FIG. 9 shows duty cycles in the case of operating the charger 100 by using three controls, i.e., the voltage decrease sequence, voltage increase sequence I and voltage increase sequence II.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Charger 100

(10) FIG. 1 shows a charger 100 according to an embodiment of the present invention. The charger 100 includes a rectifier 110, a DC/DC converter 120, a power pulsation absorbing circuit 130, and a controller 140. The charger 100 converts the single-phase AC voltage v.sub.S inputted from the single-phase AC power supply 200 to a DC voltage V.sub.dc, and outputs it to a battery 300.

(11) The rectifier 110 includes a cathode terminal 111 and an anode terminal 112 connected to DC/DC converter 120, and two input terminals 113 for connection to the AC power supply 200. For example, the rectifier 110 is configured as a bridge diode rectifier formed by four diodes, receives an AC current applied between the two input terminals 113 connected to the AC power supply, converts the current into a DC current and outputs it from the cathode terminal 111, as shown in FIG. 1. As shown in FIG. 1, the rectifier 110 may be configured to be connected to the AC power supply 200 via a filter F, wherein the filter F includes an inductor Lac and a capacitor Cac.

(12) For example, the DC/DC converter 120 is configured as a DAB (Dual Active Bridge) converter. The DC/DC converter 120 includes a first terminal 121, a second terminal 122, a third terminal 123 and a fourth terminal 124, the first terminal 121 being connected to the cathode terminal 111 of the rectifier 110, the second terminal 122 being connected to the anode terminal 112 of the rectifier 110, wherein the third and fourth terminals 123 and 124 are configured for connection to a positive electrode and a negative electrode of the battery 300, respectively. The DC/DC converter 120 includes a transformer Tr as well as four switches on an input side (primary side), i.e., a first switch S21, a second switch S22, a third switch S23 and a fourth switch S24, and four switches on an output side (secondary side), i.e., a fifth switch S25, a sixth switch S26, a seventh switch S27 and an eighth switch S28, wherein the transformer Tr is arranged between the four switches on the input side and the four switches on the output side. For example, each of the eight switches S21S28 is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, the N-channel power MOSFET may include a snubber capacitor, as shown in FIG. 1.

(13) The DC/DC converter 120 includes an inductor L on the primary side of the transformer Tr. This inductor L is, for example, a leakage inductor of the transformer Tr.

(14) Further, a DC capacitor Cdc is connected between the third terminal 123 and the fourth terminal 124 of DC/DC converter 120. An inductor Ldc may be connected between the third terminal 123 of the DC/DC converter 120 and the positive electrode of the battery 300.

(15) The power pulsation absorbing circuit 130 includes a first diode D31, a second diode D32, a third diode D33, an inductor Lb, a buffer capacitor Cbuf, a first switch S31, and a second switch S32.

(16) The first diode D31 of power pulsation absorbing circuit 130 is connected between the inductor Lb of the power pulsation absorbing circuit 130 and one of the two input terminal 113 of the rectifier 110. The second diode D32 of power pulsation absorbing circuit 130 is connected between the inductor Lb of the power pulsation absorbing circuit 130 and the other of the two input terminal 113 of the rectifier 110. In this case, each of the first diode D31 and second diode D32 of the power pulsation absorbing circuit 130 is connected between the inductor Lb of the power pulsation absorbing circuit 130 and the input terminals 113 of the rectifier 110 so that these diodes have a forward direction extending from the input terminals 113 of the rectifier 110 to the inductor Lb. Therefore, even when the AC power supply 200 is connected to the input terminals 113 of the rectifier 110, a DC current is applied to the inductor Lb of power pulsation absorbing circuit 130.

(17) The buffer capacitor Cbuf of the power pulsation absorbing circuit 130 and the first switch S31 are connected in series between a first line LH and a second line LL, wherein the first line LH connects the cathode terminal 111 of the rectifier 110 to the first terminal 121 of the DC/DC converter 120, and the second line LL connects the anode terminal 112 of the rectifier 110 to the second terminal 122 of the DC/DC converter 120. The buffer capacitor Cbuf is arranged closer to the second line LL, and the first switch 31 is arranged closer to the first line LH. The first switch S31 is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, a source and a drain of the N-channel power MOSFET may be preferably connected to the first line LH and the buffer capacitor, respectively.

(18) The third diode D33 of the power pulsation absorbing circuit 130 is connected between line connecting the buffer capacitor Cbuf of the power pulsation absorbing circuit 130 to the first switch S31 on the one hand and the inductor Lb of the power pulsation absorbing circuit 130 on the other hand so that the third diode D33 has a forward direction along a direction extending from the inductor Lb to this line.

(19) The second switch S32 of the power pulsation absorbing circuit 130 is connected between the second line LL and a line connecting the inductor Lb of the power pulsation absorbing circuit 130 to the third diode D33. The second switch S32 is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, a drain of the N-channel power MOSFET may be preferably connected to the line connecting the inductor Lb of the power pulsation absorbing circuit 130 to the third diode D33, wherein a source of the N-channel power MOSFET may be preferably connected to the second line LL.

(20) The controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120 as well as switching of the switches S31 and S32 of the power pulsation absorbing circuit 130.

(21) Since the power pulsation absorbing circuit 130 includes a first diode D31, a second diode D32, a third diode D33, an inductor Lb, a buffer capacitor Cbuf, a first switch S31, and a second switch S32, the power pulsation absorbing circuit 130 may serve as a power factor correction (PFC) circuit. Therefore, according to the present embodiment, control is possible which provides the following sinusoidal voltage v.sub.S and sinusoidal current is to the charger 100 from the AC power supply 200:
v.sub.S(t)={square root over (2)}V.sub.S sin .sub.St
i.sub.S(t)={square root over (2)}I.sub.S sin .sub.St wherein V.sub.S indicates an effective value of the power supply voltage and I.sub.S indicates an effective value of the power supply current.

(22) In this case, an instantaneous power p.sub.S outputted from the AC power supply 200 is formed by a sum of an average power P (=V.sub.SI.sub.S) and a pulsation component p.sub.rip(t) (=V.sub.SI.sub.S cos 2.sub.St) as shown below, wherein the instantaneous power p.sub.S pulsates around the average power P (dashed line in FIG. 2) with an angular frequency which is twice as high as an angular frequency of the AC, as shown with a solid line in FIG. 2.
p.sub.S(t)=v.sub.Si.sub.S=V.sub.SI.sub.S(1cos 2.sub.St)=P+p.sub.rip(t)

(23) For the above-mentioned reasons, the controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120 as well as switching of the switches S31 and S32 of the power pulsation absorbing circuit 130 to absorb power pulsation due to the AC power supply in the power pulsation absorbing circuit 130 so that a constant power is inputted to the DC/DC converter 120.

(24) In this case, the charger 100 according to the present embodiment is provided such that different controls are applied for the instantaneous power from the AC power supply 200 being higher than the average power (p.sub.S>P) and for the instantaneous power being lower than the average power (p.sub.S<P).

(25) In the case of the instantaneous power p.sub.S from the AC power supply being higher than the average power P (p.sub.S>P), switching of the eight switches S21 to S28 of the DC/DC converter 120 and the two switches S31 and S32 of the power pulsation absorbing circuit 130 are controlled to charge the pulsation component p.sub.rip of the instantaneous power p.sub.S from the AC power supply 200 to the buffer capacitor Cbuf via the inductor Lb of the power pulsation absorbing circuit 130, whereby only the average power P of the power outputted from the AC power supply may be provided to the DC/DC converter 120. This means that according to the present embodiment, the buffer capacitor Cbuf is charged in a phase in which a higher instantaneous power p.sub.S than the average power P is outputted from the AC power supply (charging phase), wherein a negative instantaneous power p.sub.C is outputted from the buffer capacitor Cbuf, as shown with a dashed dotted line in FIG. 2.

(26) On the other hand, in the case of the instantaneous power p.sub.S from the AC power supply 200 being lower than the average power P (p.sub.S<P), switching of the eight switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 are controlled while maintaining the second switch S32 of the power pulsation absorbing circuit 130 in an off-state to actively discharge the buffer capacitor Cbuf via the first switch S31. This compensates the pulsation component p.sub.rip, i.e., a difference between the instantaneous power p.sub.S and the average power P outputted from the AC power supply 200 to input the average power P to the DC/DC converter 120. This means that according to the present embodiment, the buffer capacitor Cbuf is discharged in a phase in which a lower instantaneous power p.sub.S than the average power P is outputted from the AC power supply (discharging phase), wherein a positive instantaneous power p.sub.C is outputted from the buffer capacitor Cbuf, as shown with a dashed dotted line in FIG. 2.

(27) In other words, according to the present embodiment, the controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120, the switches S31 and S32 of the power pulsation absorbing circuit 130 to obtain a constant sum of the instantaneous power p.sub.S outputted from the AC power supply 200 and the instantaneous power p.sub.C outputted from the buffer capacitor Cbuf.

(28) In this manner, the present embodiment is provided such that the buffer capacitor Cbuf is actively discharged during the discharging phase. Consequently, the present embodiment enables an amount of power accumulated in the buffer capacitor Cbuf (i.e., capacitance of the buffer capacitor Cbuf) to be limited, whereby the buffer capacitor Cbuf can be reduced in size.

(29) Further, according to the present embodiment, the second switch S32 is activated only during the charging phase. Consequently, the present embodiment enables an amount of power accumulated in the inductor Lb (i.e., inductance of the inductor Lb) to be limited, whereby the inductor Lb can be reduced in size.

(30) Further, according to the present embodiment, a power without pulsation is inputted to the DC/DC converter 120. Consequently, the present embodiment enables the transformer Tr of the DC/DC converter 120 and/or the DC capacitor Cdc to be reduced in size.

(31) In this manner, the present embodiment enables passive elements to be reduced in size, for example capacitors and inductors. Consequently, the present embodiment enables a compact charger to be provided which can absorb pulsation of power.

Switching Modes and Operation Waveform

(32) The controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 according to seven modes to obtain an operation waveform i.sub.L of the inductor L of the DC/DC converter 120 which is approximable by a rectangular waveform. FIG. 3 shows respective states of each of switches in the seven modes. The seven modes a mode (mode 5) in which the switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 are all switched off.

(33) FIG. 4 shows an operation waveform i.sub.L of an inductor L of a DC/DC converter 120 according to the present embodiment and a corresponding equivalent rectangular waveform i.sub.L. This operation waveform i.sub.L is obtained by switching the seven modes as shown in FIG. 3 to mode 1, mode 2, mode 3, mode 4, mode 5, mode 4, mode 6, mode 7, mode 1 and mode 5 in this order. In this case, a current i.sub.L is obtained in each of the seven modes as follows (see Non-Patent Document 1)

(34) $i_L\left(t\right)=\{\begin{array}{cc}\frac{v_C+V_{\mathrm{dc}}}{L}\left(t-t_{c1}\right)+i_L\left(t_{c1}\right)& \left(\mathrm{Mode}1\right)\\ \frac{v_C+V_{\mathrm{dc}}}{L}\left(t-t_{c2}\right)+i_L\left(t_{c2}\right)& \left(\mathrm{Mode}2\right)\\ \frac{v_{\mathrm{rec}}+V_{\mathrm{dc}}}{L}\left(t-t_{c3}\right)+i_L\left(t_{c3}\right)& \left(\mathrm{Mode}3\right)\\ -\frac{v_C+V_{\mathrm{dc}}}{L}\left(t-t_{c4}\right)+i_L\left(t_{c4}\right)& \left(\mathrm{Mode}4\right)\\ 0& \left(\mathrm{Mode}5\right)\\ -\frac{v_{\mathrm{rec}}+V_{\mathrm{dc}}}{L}\left(t-t_{c6}\right)+i_L\left(t_{c6}\right)& \left(\mathrm{Mode}6\right)\\ -\frac{v_C+V_{\mathrm{dc}}}{L}\left(t-t_{c7}\right)+i_L\left(t_{c7}\right)& \left(\mathrm{Mode}7\right)\end{array}$ wherein t.sub.cn (n=1 to 7) indicates a time at which switching to mode n is performed.

(35) According to the present embodiment, in order to discharge the buffer capacitor Cbuf more actively when the first switch S31 of the power pulsation absorbing circuit 130 is in an on-state, the controller 140 controls a voltage v.sub.C applied to the buffer capacitor Cbuf such that the voltage v.sub.C is always higher than an instantaneous voltage v.sub.rec outputted from the rectifier 110. Therefore, according to the present embodiment, the voltage v.sub.C applied to the buffer capacitor Cbuf has a value which is different from the instantaneous voltage v.sub.rec of the rectifier 110, and modes 2 and 3 have different gradients of the operation waveform i.sub.L. Similarly, modes 6 and 7 have different gradients of the operation waveform i.sub.L. In this manner, the present embodiment enables operation waveforms to be generated which are asymmetrical with respect to i.sub.L=0 in positive and negative waveforms, as shown in FIG. 4.

(36) For the operation waveform i.sub.L as shown in FIG. 4, it is possible to approximate it by an equivalent rectangular waveform i.sub.L if t.sub.0 to t.sub.10 are set such that |t.sub.0t.sub.1|=|t.sub.5t.sub.6|, |t.sub.1t.sub.2|=|t.sub.7t.sub.8|, |t.sub.2t.sub.3|=|t.sub.6t.sub.7|, |t.sub.3t.sub.4|=|t.sub.8t.sub.9|, and if t.sub.S1 and t.sub.S2 are set between t.sub.3 and t.sub.4 and between t.sub.8 and t.sub.9 respectively such that |t.sub.0t.sub.1|=|t.sub.S1t.sub.4|=|t.sub.S2t.sub.9|.

(37) $i_L^{}\left(t\right)=\{\begin{array}{cc}\frac{i_L\left(t_1\right)+i_L\left(t_3\right)}{2}=I_L^{}& \left(t_{1}t{t}_{S1}\right)\\ -I_L^{}& \left(t_{6}t{t}_{S2}\right)\\ 0& \left(t_{0}t<t_1,t_{S1}<t<t_6,t_{S2}<t<t_{10}\right)\end{array}$

(38) If phases from t.sub.0 to t.sub.1, from t.sub.S1 to t.sub.4, from t.sub.5 to t.sub.6, and from t.sub.S2 to t.sub.9 of the equivalent rectangular waveform i.sub.L are defined as reactive current phases T.sub.q, phases from t.sub.1 to t.sub.2 and from t.sub.7 to t.sub.8 are defined as buffer capacitor discharge current phases T.sub.C, phases from t.sub.2 to t.sub.3 and from t.sub.6 to t.sub.1 are defined as power supply current phases T.sub.rec, phases from t.sub.3 to t.sub.S1 and from t.sub.8 to t.sub.S2 are defined as current balance phases T.sub.b, and phases from t.sub.4 to t.sub.5 and from t.sub.9 to t.sub.10 are defined as zero current phases T.sub.0, a duty cycle for each of the phases within a switching period T.sub.SW is as follows:

(39) $\begin{array}{cc}\{\begin{array}{c}{D}_q=\frac{2T_q}{T_{\mathrm{SW}}}=\frac{2I_L^{}L}{\left(v_C+V_{\mathrm{dc}}\right)T_{\mathrm{SW}}}-\frac{D_b}{2}\\ D_C=\frac{2T_C}{T_{\mathrm{SW}}}=\frac{i_C}{I_L^{}}+D_b=\frac{\left(v_{rec}-V_{\mathrm{dc}}\right)i_{rec}+\left(v_C+V_{\mathrm{dc}}\right)i_C}{2V_{\mathrm{dc}}{I}_L^{}}\\ D_{\mathrm{rec}}=\frac{2T_{rec}}{T_{\mathrm{SW}}}=\frac{i_{rec}}{I_L^{}}\\ D_b=\frac{2T_b}{T_{\mathrm{SW}}}=\frac{\left(v_{rec}-V_{\mathrm{dc}}\right)i_{rec}+\left(v_C+V_{\mathrm{dc}}\right)i_C}{2V_{\mathrm{dc}}{I}_L^{}}\\ D_0=\frac{2T_0}{T_{\mathrm{SW}}}=1-\left(2D_q+D_C+D_{rec}+D_b\right)\end{array}& \left(1\right)\end{array}$ The duty cycle of each of the phases can be obtained by giving i.sub.rec, i.sub.C, v.sub.C and V.sub.dc I.sub.L as set values. The obtained duty cycles of phases may be used to determine a control rule for the operation waveform i.sub.L in FIG. 4. Among these set values, set values i.sub.rec* and i.sub.C* for i.sub.rec and i.sub.C are switched as follows for the discharging phase and charging phase, wherein the power pulsation absorbing circuit 130 is operated to function as a PFC circuit and as a circuit for absorbing power pulsation:

(40) $i_{rec}^{*}=\{\begin{array}{cc}\sqrt{2}\frac{P}{V_S}.Math.\sin {}_{S}t.Math.& \left(\mathrm{Discharging}\mathrm{phase}\right)\\ \frac{P}{\sqrt{2}{V}_S.Math.\sin {}_{S}t.Math.}& \left(\mathrm{Charging}\mathrm{phase}\right)\end{array}$$i_C^{*}=\{\begin{array}{cc}\frac{P}{v_C}\cos 2{}_{S}t& \left(\mathrm{Discharging}\mathrm{phase}\right)\\ 0& \left(\mathrm{Charging}\mathrm{phase}\right)\end{array}$

Switching Control during Voltage Increase Operation

(41) In order to operate the charger 100 by performing the above-described control, all the duty cycles in the above formulas (1) should be positive. During voltage decrease operation (i.e., V.sub.SV.sub.dc), all the duty cycles in the formulas (1) are positive. However, during voltage increase operation (i.e., V.sub.S<V.sub.dc), the duty cycle D.sub.b in the current balance phase T.sub.b and the duty cycle D.sub.C in the buffer capacitor discharge current phase T.sub.C may be negative, as shown in FIG. 5. In the example as shown in FIG. 5, both of the duty cycle D.sub.b in the current balance phase T.sub.b and the duty cycle D.sub.C in the buffer capacitor discharge current phase T.sub.C are positive at a phase .sub.St of 0 degree of the AC power supply voltage v.sub.S. However, at the phase .sub.St of approximately 15 degrees of the AC power supply voltage v.sub.S, the duty cycle D.sub.b in the current balance phase T.sub.b is negative, and at the phase .sub.St of approximately 45 degrees of the AC power supply voltage v.sub.S, the duty cycle D.sub.C in the buffer capacitor discharge current phase T.sub.C is negative. When the duty cycle D.sub.b in the current balance phase T.sub.b is negative, the following is obtained according to the formula (1)
(v.sub.recV.sub.dc)i.sub.rec+(v.sub.CV.sub.dc)i.sub.C<0(2) And when the duty cycle D.sub.C in the buffer capacitor discharge current phase T.sub.C is negative, the following is obtained according to the formula (1):
(v.sub.recV.sub.dc)i.sub.rec+(v.sub.CV.sub.dc)i.sub.C<0(3)

(42) Therefore, according to the present embodiment, a different switching control is applied in the case of the duty cycle D.sub.b in the current balance phase T.sub.b being negative (i.e., the above formula (2) is fulfilled), and in the case of the duty cycle D.sub.C in the buffer capacitor discharge current phase T.sub.C being negative (i.e., the above formula (3) is fulfilled), a further different switching control is applied. Hereinafter, the control in the case of both formulas (2) and (3) being not fulfilled, i.e., the control as described above, shall be referred to as voltage decrease sequence, the control in the case where formula (2) is fulfilled and formula (3) is not fulfilled shall be referred to as voltage increase sequence I, and the control in the case of both formulas (2) and (3) being fulfilled shall be referred to as voltage increase sequence II.

Voltage Increase Sequence I

(43) In the operation waveform i.sub.L as shown in FIG. 4, i.sub.L(t.sub.1)i.sub.L(t.sub.3). However, when the duty cycle D.sub.b in the current balance phase T.sub.b is negative (i.e., the above formula (2) is fulfilled), this results in i.sub.L(t.sub.1)i.sub.L(t.sub.3) in the operation waveform i.sub.L, as shown in FIG. 6. Therefore, according to the present embodiment, in the case where formula (2) is fulfilled and formula (3) is not fulfilled, t.sub.0 to t.sub.10 are set such that |t.sub.0t.sub.1|=|t.sub.5t.sub.6|, |t.sub.1t.sub.2|=|t.sub.7t.sub.8|, |t.sub.2t.sub.3|=|t.sub.6t.sub.7|, |t.sub.3t.sub.4|=|t.sub.8t.sub.9|, and t.sub.S1 and t.sub.S2 are set between t.sub.0 and t.sub.1 and between t.sub.5 and t.sub.6 respectively such that |t.sub.0t.sub.S1|=|t.sub.3t.sub.4|=|t.sub.5t.sub.S2|, and the operation waveform i.sub.L is then approximated by the following equivalent rectangular waveform i.sub.L:

(44) $i_L^{}\left(t\right)=\{\begin{array}{cc}\frac{i_L\left(t_1\right)+i_L\left(t_3\right)}{2}=I_L^{}& \left(t_{S1}t{t}_3\right)\\ -I_L^{}& \left(t_{S2}t{t}_8\right)\\ 0& \left(t_{0}t<t_{S1},t_3<t<t_{S2},t_8<t<t_{10}\right)\end{array}$

(45) If phases from t0 to t.sub.S1, from t.sub.3 to t.sub.4, from t.sub.5 to t.sub.S2, and from t.sub.8 to t.sub.9 of the equivalent rectangular waveform i.sub.L are defined as reactive current phases T.sub.q, phases from t.sub.1 to t.sub.2 and from t.sub.7 to t.sub.8 are defined as buffer capacitor discharge current phases T.sub.C, phases from t.sub.2 to t.sub.3 and from t.sub.6 to t.sub.7 are defined as power supply current phases T.sub.rec, phases from t.sub.S1 to t.sub.1 and from t.sub.S2 to t.sub.6 are defined as current balance phases T.sub.b, and phases from t.sub.4 to t.sub.5 and from t.sub.10 to t.sub.10 are defined as zero current phases T.sub.0, a duty cycle for each of the phases within a switching period T.sub.SW is as follows:

(46) $\begin{array}{cc}\{\begin{array}{c}{D}_q=\frac{2I_L^{}L}{\left(v_C+V_{\mathrm{dc}}\right)T_{\mathrm{SW}}}-\frac{D_b}{2}\\ D_C=\frac{i_C}{I_L^{}}-D_b=\frac{\left(v_{rec}-V_{\mathrm{dc}}\right)i_{rec}+\left(v_C+V_{\mathrm{dc}}\right)i_C}{2V_{\mathrm{dc}}{I}_L^{}}\\ D_{\mathrm{rec}}=\frac{i_{rec}}{I_L^{}}\\ D_b=-\frac{\left(v_{rec}-V_{\mathrm{dc}}\right)i_{rec}+\left(v_C+V_{\mathrm{dc}}\right)i_C}{2V_{\mathrm{dc}}{I}_L^{}}\\ D_0=1-\left(2D_q+D_C+D_{rec}+D_b\right)\end{array}& \left(4\right)\end{array}$ Similarly, in the voltage increase sequence I, the duty cycle of each of the phases can be obtained by giving i.sub.rec, i.sub.C, v.sub.C and V.sub.dc I.sub.L as set values. The obtained duty cycles of phases may be used to determine a control rule for the operation waveform i.sub.L in FIG. 6.

Voltage Increase Sequence II

(47) Further, according to the present embodiment, in the case of both formulas (2) and (3) being fulfilled, switching of the switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 is controlled according to nine modes as shown in FIG. 7 which include two modes in addition to the seven modes as shown in FIG. 3. Such control results in an operation waveform i.sub.L as shown in FIG. 8. The operation waveform i.sub.L as shown in FIG. 8 is obtained by switching the nine modes as shown in FIG. 7 to mode 1, mode 8, mode 2, mode 3, mode 4, mode 5, mode 4, mode 9, mode 6, mode 7, mode 1 and mode 5 in this order.

(48) Then, for the operation waveform i.sub.L as shown in FIG. 8, it is possible to approximate it by an equivalent rectangular waveform i.sub.L if t.sub.0 to t.sub.12 are set such that |t.sub.0t.sub.1|=|t.sub.6t.sub.7|=, |t.sub.1t.sub.2|=|t.sub.7t.sub.8|=, |t.sub.2t.sub.3|=|t.sub.9t.sub.10|=, |t.sub.3t.sub.4|=|t.sub.8t.sub.9|=, |t.sub.4t.sub.5|=|t.sub.10t.sub.11| and |t.sub.5t.sub.6|=|t.sub.11t.sub.12|.

(49) $i_L^{}\left(t\right)=\{\begin{array}{cc}\frac{i_L\left(t_1\right)+i_L\left(t_4\right)}{2}=I_L^{}& \left(t_{1}t{t}_4\right)\\ -I_L^{}& \left(t_{7}t{t}_{10}\right)\\ 0& \left(t_{0}t<t_1,t_4<t<t_7,t_{10}<t<t_{12}\right)\end{array}$

(50) If phases from t.sub.0 to t.sub.1, from t.sub.4 to t.sub.5, from t.sub.6 to t.sub.7, and from t.sub.10 to t.sub.11 of the equivalent rectangular waveform i.sub.L are defined as reactive current phases T.sub.q, phases from t.sub.2 to t.sub.3 and from t.sub.9 to t.sub.10 are defined as buffer capacitor discharge current phases T.sub.C, phases from t.sub.3 to t.sub.4 and from t.sub.8 to t.sub.9 are defined as power supply current phases T.sub.rec, phases from t.sub.1 to t.sub.2 and from t.sub.7 to t.sub.8 are defined as current balance phases T.sub.b, and phases from t.sub.5 to t.sub.6 and from t.sub.11 to t.sub.12 are defined as zero current phases T.sub.0, a duty cycle for each of the phases within a switching period T.sub.SW is as follows:

(51) $\begin{array}{cc}\{\begin{array}{c}{D}_q=\frac{2I_L^{}L}{\left(v_C+V_{\mathrm{dc}}\right)T_{\mathrm{SW}}}-\frac{v_{\mathrm{rec}}+V_{\mathrm{dc}}}{v_C+V_{\mathrm{dc}}}\frac{D_b}{2}\\ D_C=\frac{i_C}{I_L^{}}\\ D_{\mathrm{rec}}=\frac{i_{rec}}{I_L^{}}-D_b=\frac{\left(v_{rec}-V_{\mathrm{dc}}\right)i_{rec}+\left(v_C+V_{\mathrm{dc}}\right)i_C}{2V_{\mathrm{dc}}{I}_L^{}}\\ D_b=-\frac{\left(v_{rec}-V_{\mathrm{dc}}\right)i_{rec}+\left(v_C+V_{\mathrm{dc}}\right)i_C}{2V_{\mathrm{dc}}{I}_L^{}}\\ D_0=1-\left(2D_q+D_C+D_{rec}+D_b\right)\end{array}& \left(5\right)\end{array}$ Similarly, in the voltage increase sequence II, the duty cycle of each of the phases can be obtained by giving i.sub.rec, i.sub.C, v.sub.C and V.sub.dc I.sub.L as set values. The obtained duty cycles of phases may be used to determine a control rule for the operation waveform i.sub.L in FIG. 8.

Operation of the Charger 100

(52) FIG. 9 shows duty cycles in the case of operating the charger 100 by using three controls, i.e., the voltage decrease sequence, voltage increase sequence I and voltage increase sequence II. As shown in FIG. 9, it is possible to operate the charger 100 also during the voltage increase operation by changing the switching control into voltage decrease sequence, voltage increase sequence I, voltage increase sequence II, voltage decrease sequence, voltage increase sequence II and voltage increase sequence I in this order.

Control of Switching Frequency f.SUB.SW

(53) The zero current phase T.sub.0 is mode 5, wherein in this phase, all the switches S21 to S28 of DC/DC converter 120 are switched off. However, the switches are practically switched off at times which are offset, wherein this offset causes residual current and thus resonance between the inductor L of the DC/DC converter 120 and parasitic capacitances of the switches S21 to S28. Therefore, switching after the zero current phase T.sub.0 (switching in a changing process from mode 5 to mode 4, switching in a changing process from mode 5 to mode 1) will becomes hard switching, which results in switching loss.

(54) Therefore, a method has been proposed in which switching frequencies f.sub.SW of switching of the switches S21 to S28 of the DC/DC converter 120 and/or of the switch S31 of the power pulsation absorbing circuit 130 are changed within one period of the AC voltage v.sub.S inputted from the AC power supply 200 so that no zero current phase T.sub.0 exists, whereby oscillation of a current i.sub.L and a voltage V.sub.L of the inductor L is removed and hard switching is avoided after the zero current phase T.sub.0 to control the charger 100 more efficiently (Shohei Komeda, Shunsuke Takuma and Yoshiya Ohnuma A Variable Frequency Control Method for a Dual-Active-Bridge AC-DC Converter with an Active Energy Buffer, lecture papers collection of 2021 IEE-Japan Industry Applications Society Conference, Vol. 1, No. 30, pp. 13-18 (2021)).

(55) Similarly in the present embodiment, for example, the controller 140 may control values of switching frequencies f.sub.SW of switching of the switches S21 to S28 of the DC/DC converter 120 and/or of the switch S31 of the power pulsation absorbing circuit 130 so that no zero current phase T.sub.0 exists. By solving the above equations (1), (4) and (5) with D.sub.0=0, the switching frequency f.sub.SW with which no zero current phase T.sub.0 exists is obtained as follows.

(56) $\begin{array}{cc}{f}_{SW}=\frac{v_C+V_{\mathrm{dc}}}{4I_L^{}L}\left(1-D_{rec}-D_C\right)& \left(6\right)\end{array}$$\begin{array}{cc}{f}_{\mathrm{SW}}=\frac{v_C+V_{\mathrm{dc}}}{4I_L^{}L}\left(1-D_{rec}-D_C\frac{v_C-v_{\mathrm{rec}}}{v_C+V_{\mathrm{dc}}}{D}_b\right)& \left(7\right)\end{array}$ Equation (6) as above corresponds to switching frequencies f.sub.SW for the voltage decrease sequence and voltage increase sequence I, while equation (7) as above corresponds to a switching frequency f.sub.SW for the voltage increase sequence II.

Set Value for Peak Value I.SUB.L. of the Equivalent Rectangular Wave i.SUB.L.

(57) In the above-mentioned document (see Shohei Komeda, Shunsuke Takuma and Yoshiya Ohnuma A Variable Frequency Control Method for a Dual-Active-Bridge AC-DC Converter with an Active Energy Buffer, lecture papers collection of 2021 IEE-Japan Industry Applications Society Conference, Vol. 1, No. 30, pp. 13-18 (2021)), a method has been also proposed in which a set value for a peak value I.sub.L of the equivalent rectangular wave i.sub.L in a voltage decrease sequence according to the prior art is optimized to operate the charger 100 more efficiently. In this method, the set value of the peak value I.sub.L of the equivalent rectangular waveform i.sub.L is controlled to obtain a predetermined value f.sub.min of the switching frequency f.sub.SW (equation (6) as mentioned above) at a phase .sub.St of 45 degrees of AC power supply voltage v.sub.S so that the charger 100 is operated more efficiently.

(58) However, during the voltage increase operation, at the phase .sub.St of 45 degrees of AC power supply voltage v.sub.S, the charger 100 may be not operated with the voltage decrease sequence according to the prior art, but with the voltage increase sequence II, as shown in FIG. 9. In this case, it is not possible to use the method proposed in the above document directly. Therefore, in such a case, for example the set value of the peak value I.sub.L of the equivalent rectangular waveform i.sub.L is preferably controlled at the phase .sub.St of 45 degrees of AC power supply voltage v.sub.S to obtain a predetermined value f.sub.min of the switching frequency f.sub.SW in the voltage increase sequence II (equation (7) as mentioned above). In this case, the set value I.sub.L* of the peak value I.sub.L of the equivalent rectangular waveform i.sub.L is as follows:

(59) 0$$\begin{gathered} \begin{array}{cc}{I}_L^{*}=\frac{V_{\mathrm{dc}}+V_{C_{\min }}}{8f_{\min }L}\left[1-\sqrt{1-A^{}}\right] \\ {A}^{}=\frac{8f_{\min }{\mathrm{LI}}_S\left(V_s^2+V_{\mathrm{dc}}^2+2V_{C_{\min }}{V}_{\mathrm{dc}}\right)}{{V_{\mathrm{dc}}\left(V_{\mathrm{dc}}+V_{C_{\min }}\right)}^2} \\ {V}_{C_{\min }}=\sqrt{V_{C_{\max }}^2-\frac{2P}{{}_S{C}_{\mathrm{buf}}}}& \left(8\right)\end{array} \end{gathered}$$

(60) The above formula (8) is effective in the case where the switching frequency f.sub.SW in the voltage increase sequence II (equation (7) as mentioned above) is minimum at the phase .sub.St of 45 degrees of AC power supply voltage v.sub.S. When a maximum value of the voltage v.sub.C applied to the buffer capacitor Cbuf is set to a sufficiently high value, the switching frequency f.sub.SW in the voltage increase sequence II (equation (7) as mentioned above) is minimum at the phase .sub.St of 45 degrees of AC power supply voltage v.sub.S. On the other hand, when the maximum value of the voltage v.sub.C applied to the buffer capacitor Cbuf is reduced, the switching frequency f.sub.SW in the voltage increase sequence II (equation (7) as mentioned above) may be minimum at a phase .sub.St AC power supply voltage v.sub.S which is different from 45 degrees. In such a case, a set value of the peak value I.sub.L of the equivalent rectangular waveform may be preferably determined with which a minimum value of the switching frequency f.sub.SW in the voltage increase sequence II (equation (7) as mentioned above) is adjusted to the predetermined value f.sub.min.

(61) The present invention has been described above by means of the preferable embodiment thereof. Although the invention has been described herein by presenting a specific example, various modifications and changes may be made to such an example without departing from the spirit and scope of the invention as set forth in the claims.

REFERENCE SIGNS LIST

(62) 100 Charger 110 Rectifier 120 DC/DC converter S21-S28 Switches of the DC/DC converter 130 Power pulsation absorbing circuit D31 First diode D32 Second diode D33 Third diode Lb Inductor Cbuf Buffer capacitor S31 First switch S32 Second switch 200 AC power supply 300 Battery