Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a two-dimensional semiconductor layer formed by a two-dimensional semiconductor material having a first formation energy, a two-dimensional metal conductor layer formed by a two-dimensional metal material and covering a surface of the two-dimensional semiconductor layer, and a metal layer covering a surface of the two-dimensional metal conductor layer. The two-dimensional metal material has a second formation energy smaller than the first formation energy. The two-dimensional metal conductor layer is formed by bonding of cations from the metal layer and anions from the two-dimensional semiconductor layer. As such, the contact resistances between the two-dimensional materials and the metals can be effectively reduced, enabling the application of the two-dimensional materials in semiconductor devices such as field-effect transistors.

Claims

1. A semiconductor device, comprising: a two-dimensional semiconductor layer formed by a two-dimensional semiconductor material having a first formation energy; a two-dimensional metal conductor layer formed by a two-dimensional metal material and covering a surface of the two-dimensional semiconductor layer, the two-dimensional metal material having a second formation energy smaller than the first formation energy; and a metal layer covering a surface of the two-dimensional metal conductor layer; wherein the two-dimensional metal conductor layer is formed by bonding of cations from the metal layer and anions from the two-dimensional semiconductor layer.

2. The semiconductor device as claimed in claim 1, wherein the two-dimensional semiconductor material and the two-dimensional metal material are MoS.sub.2 and NbS.sub.2, WS.sub.2 and NbS.sub.2, VS.sub.2 and NbS.sub.2, NiS.sub.2 and NbS.sub.2, PdS.sub.2 and NbS.sub.2, PtS.sub.2 and NbS.sub.2, MoS.sub.2 and TaS.sub.2, WS.sub.2 and TaS.sub.2, VS.sub.2 and TaS.sub.2, NiS.sub.2 and TaS.sub.2, PdS.sub.2 and TaS.sub.2, PtS.sub.2 and TaS.sub.2, WS.sub.2 and VS.sub.2, NiS.sub.2 and VS.sub.2, PdS.sub.2 and VS.sub.2, PtS.sub.2 and VS.sub.2, NiS.sub.2 and FeS.sub.2, PdS.sub.2 and FeS.sub.2, or PtS.sub.2 and FeS.sub.2, respectively.

3. The semiconductor device as claimed in claim 2, wherein the metal layer is formed by niobium, tantalum, vanadium, or iron.

4. The semiconductor device as claimed in claim 1, wherein the two-dimensional semiconductor material and the two-dimensional metal material are MoSe.sub.2 and NbSe.sub.2, WSe.sub.2 and NbSe.sub.2, PdSe.sub.2 and NbSe.sub.2, PtSe.sub.2 and NbSe.sub.2, MoSe.sub.2 and TaSe.sub.2, WSe.sub.2 and TaSe.sub.2, PdSe.sub.2 and TaSe.sub.2, PtSe.sub.2 and TaSe.sub.2, MoSe.sub.2 and VSe.sub.2, WSe.sub.2 and VSe.sub.2, PdSe.sub.2 and VSe.sub.2, PtSe.sub.2 and VSe.sub.2, MoSe.sub.2 and TiSe.sub.2, WSe.sub.2 and TiSe.sub.2, PdSe.sub.2 and TiSe.sub.2, or PtSe.sub.2 and TiSe.sub.2, respectively.

5. The semiconductor device as claimed in claim 4, wherein the metal layer is formed by niobium, tantalum, vanadium, or titanium.

6. The semiconductor device as claimed in claim 1, wherein the two-dimensional semiconductor material and the two-dimensional metal material are MoTe.sub.2 and NbTe.sub.2, MoTe.sub.2 and TiTe.sub.2, MoTe.sub.2 and HfTe.sub.2, or MoTe.sub.2 and ZrTe.sub.2, respectively.

7. The semiconductor device as claimed in claim 6, wherein the metal layer is formed by niobium, titanium, hafnium, or zirconium.

8. The semiconductor device as claimed in claim 1, wherein the two-dimensional semiconductor layer serves as a channel, and the metal layer serves as a source or a drain.

9. A method of manufacturing the semiconductor device of claim 1, comprising the steps of: (A) forming a metal layer on a two-dimensional semiconductor layer; and (B) annealing in a controlled atmosphere at a temperature ranging from 600 C. to 1000 C. to enable that metal cations from the metal layer and anions from the two-dimensional semiconductor layer are bonded to form a two-dimensional metal conductor layer.

10. The method as claimed in claim 9, wherein in the step (B) the controlled atmosphere comprises nitrogen gas and hydrogen gas, which have a nitrogen-to-hydrogen ratio ranging from 80:20 to 90:10.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

(2) FIG. 1 is a schematic view showing partially manufacturing steps of a semiconductor device in accordance with an embodiment of the present invention;

(3) FIG. 2 is a schematic view showing that the semiconductor device of the embodiment of the present invention is applied in a field-effect transistor:

(4) FIG. 3 is a perspective view showing that the semiconductor device of the embodiment of the present invention is applied in a gate-all-around field-effect transistor:

(5) FIG. 4 is a sectional view taken along line A-A of FIG. 3; and

(6) FIG. 5 is a sectional view showing that the semiconductor device of the embodiment of the present invention is applied in another gate-all-around field-effect transistor.

DETAILED DESCRIPTION OF THE INVENTION

(7) Hereunder an embodiment will be detailedly described with accompanying drawings for illustrating technical features and structure of the present invention. As shown in FIG. 1, a method of manufacturing a semiconductor device 1 provided in accordance with a preferred embodiment of the present invention includes the following steps of: (A) forming a two-dimensional semiconductor layer 12 on a substrate 10 by using chemical vapor deposition (CVD), molecular beam epitaxy, or laser epitaxy, and then forming a metal layer 16 on the two-dimensional semiconductor layer 12 by using sputtering, electron beam evaporation, or thermal evaporation; and (B) annealing the semifinished product obtained in the step (A) in a controlled atmosphere at a temperature ranging from 600 to 1000 C., enabling that cations from the metal layer 16 are bonded with anions from the two-dimensional semiconductor layer 12 so as to form a two-dimensional metal conductor layer 14 between the metal layer 16 and the two-dimensional semiconductor layer 12.

(8) For the substrate 10, a three-dimensional material, such as silicon (Si), may be used to make the substrate 10. In another embodiment, sapphire, quartz, silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), silicon for grown silicon dioxide (SiO.sub.2/Si), silicon for grown silicon nitride (SiN.sub.x/Si), or other amorphous insulating materials may be used as the material for making the substrate 10. Alternately, a two-dimensional material, such as mica, may be used to make the substrate 10.

(9) The two-dimensional semiconductor layer 12 is formed by two-dimensional semiconductor materials, such as molybdenum disulfide (MoS.sub.2), exhibiting semiconductor properties. The two-dimensional semiconductor materials have a first formation energy. In this embodiment, the formation energy of MoS.sub.2 is 1.059 eV/atom. The greater the negative value of the formation energy, i.e., the smaller the value, the more stable the synthesis reactants are and the easier they are to form.

(10) The metal layer 16 is a niobium (Nb) layer. The controlled atmosphere includes 85 vol % nitrogen gas and 15 vol % hydrogen gas. During annealing, because the formation energy of niobium disulfide (NbS.sub.2) is 1.207 eV/atom, which is smaller than the formation energy of molybdenum disulfide (MoS.sub.2) at 1.059 eV/atom, the Nb.sup.+ ions in the metal layer 16 can bond with the S.sup.+ ions in the two-dimensional semiconductor layer 12 (i.e., molybdenum disulfide layer), thereby forming a layer of niobium disulfide (NbS.sub.2) between the metal layer 16 and the two-dimensional semiconductor layer 12. Since niobium disulfide is a two-dimensional metal material with metallic conductor properties, this niobium disulfide layer is referred to as the two-dimensional metal conductor laver 14, which structurally covers over the surface of the two-dimensional semiconductor layer 12. The two-dimensional metal material in this embodiment has a second formation energy, which is smaller than the first formation energy. Once the two-dimensional metal conductor layer 14 is formed, the metal layer 16 essentially covers over the surface of the two-dimensional metal conductor layer 14. In other words, the two-dimensional metal conductor layer 14 is formed by the bonding of cations from the metal layer 16 and anions from the two-dimensional semiconductor layer 14.

(11) Since the sulfur atoms in molybdenum disulfide (MoS.sub.2) in the two-dimensional semiconductor layer 12 are taken away by niobium atoms, this results in the phenomenon of surface sulfur vacancies (S vacancy). This can increase the surface carrier concentration without incurring the result of damaging the surface or oxidation. Niobium disulfide, which has metallic conductor properties, plays a role similar to the graphene in the prior arts, thereby significantly reducing the Schottky barrier between the metal layer 16 and the two-dimensional semiconductor layer 12. Moreover, the manufacturing steps of the method of the present invention are compatible with semiconductor CMOS processes. Therefore, the manufacturing method provided by the present invention can successfully achieve ohmic contact between two-dimensional materials and metals, reducing the contact resistance between them. This enables the successful application of two-dimensional materials in semiconductor devices, such as field-effect transistors, thus achieving the objectives of the present invention.

(12) It is to be further mentioned that in step (B), the controlled atmosphere containing nitrogen gas and hydrogen gas can have a nitrogen-to-hydrogen ratio that varies as needed within the range of 80:20 to 90:10, and the annealing temperature can also be adjusted as needed.

(13) In addition to the aforementioned embodiment, other two-dimensional semiconductor materials and two-dimensional metal materials may be used in the present invention as long as they meet the condition that the second formation energy is smaller than the first formation energy. Table 1 lists the values of the first formation energy for various two-dimensional semiconductor materials having semiconductor properties, while Table 2 provides the values of the second formation energy for various two-dimensional metal materials having metallic conductor properties.

(14) TABLE-US-00001 TABLE 1 Two-dimensional semiconductor material Formation energy (eV/atom) Sulfide MoS.sub.2 1.059 WS.sub.2 1.012 TiS.sub.2 1.463 VS.sub.2 1.044 NiS.sub.2 0.449 PdS.sub.2 0.460 PtS.sub.2 0.544 Selenide MoSe.sub.2 0.679 WSe.sub.2 0.563 PdSe.sub.2 0.282 PtSe.sub.2 0.388 Telluride MoTe.sub.2 0.271

(15) TABLE-US-00002 TABLE 2 Two-dimensional metal material Formation energy (eV/atom) Sulfide NbS.sub.2 1.207 TaS.sub.2 1.242 VS.sub.2 1.044 FeS.sub.2 0.701 Selenide NbSe.sub.2 0.849 TaSe.sub.2 0.818 VSe.sub.2 0.699 TiSe.sub.2 1.121 Telluride NbTe.sub.2 0.460 TiTe.sub.2 0.708 HfTe.sub.2 0.827 ZrTe.sub.2 0.880

(16) Since the formation energies in Tables 1 and 2 were obtained under the same equipment and factors, their relative magnitudes provide reference value. Through actual experiments, for sulfides, the combinations of the two-dimensional semiconductor materials and the two-dimensional metal materials may be as follows: molybdenum disulfide (MoS.sub.2) and niobium disulfide (NbS.sub.2); tungsten disulfide (WS.sub.2) and niobium disulfide (NbS.sub.2), vanadium disulfide (VS.sub.2) and niobium disulfide (NbS.sub.2), nickel disulfide (NiS.sub.2) and niobium disulfide (NbS.sub.2); palladium disulfide (PdS.sub.2) and niobium disulfide (NbS.sub.2); platinum disulfide (PtS.sub.2) and niobium disulfide (NbS.sub.2); molybdenum disulfide (MoS.sub.2) and tantalum disulfide (TaS.sub.2) tungsten disulfide (WS.sub.2) and tantalum disulfide (TaS.sub.2); vanadium disulfide (VS.sub.2) and tantalum disulfide (TaS.sub.2); nickel disulfide (NiS.sub.2) and tantalum disulfide (TaS.sub.2); palladium disulfide (PdS.sub.2) and tantalum disulfide (TaS.sub.2); platinum disulfide (PtS.sub.2) and tantalum disulfide (TaS.sub.2); tungsten disulfide (WS.sub.2) and vanadium disulfide (VS.sub.2); nickel disulfide (NiS.sub.2) and vanadium disulfide (VS.sub.2); palladium disulfide (PdS.sub.2) and vanadium disulfide (VS.sub.2); platinum disulfide (PtS.sub.2) and vanadium disulfide (VS.sub.2); nickel disulfide (NiS.sub.2) and iron disulfide (FeS.sub.2); palladium disulfide (PdS.sub.2) and iron disulfide (FeS.sub.2); or platinum disulfide (PtS.sub.2) and iron disulfide (FeS.sub.2). Accordingly, for the metal layer 16, niobium, tantalum, vanadium, or iron may be used to form the metal layer 16.

(17) For selenides, the combinations of the two-dimensional semiconductor materials and the two-dimensional metal materials may be as follows: molybdenum diselenide (MoSe.sub.2) and niobium diselenide (NbSe.sub.2); tungsten diselenide (WSe.sub.2) and niobium diselenide (NbSe.sub.2); palladium diselenide (PdSe.sub.2) and niobium diselenide (NbSe.sub.2); platinum diselenide (PtSe.sub.2) and niobium diselenide (NbSe.sub.2); molybdenum diselenide (MoSe.sub.2) and tantalum diselenide (TaSe.sub.2); tungsten diselenide (WSe.sub.2) and tantalum diselenide (TaSe.sub.2); palladium diselenide (PdSe.sub.2) and tantalum diselenide (TaSe.sub.2); platinum diselenide (PtSe.sub.2) and tantalum diselenide (TaSe.sub.2); molybdenum diselenide (MoSe.sub.2) and vanadium diselenide (VSe.sub.2); tungsten diselenide (WSe.sub.2) and vanadium diselenide (VSe.sub.2); palladium diselenide (PdSe.sub.2) and vanadium diselenide (VSe.sub.2); platinum diselenide (PtSe.sub.2) and vanadium diselenide (VSe.sub.2); molybdenum diselenide (MoSe.sub.2) and titanium diselenide (TiSe.sub.2); tungsten diselenide (WSe.sub.2) and titanium diselenide (TiSe.sub.2); palladium diselenide (PdSe.sub.2) and titanium diselenide (TiSe.sub.2); or platinum diselenide (PtSe.sub.2) and titanium diselenide (TiSe.sub.2). Accordingly; niobium, tantalum, vanadium, or titanium may be used to form the metal layer 16.

(18) For tellurides, the combinations of the two-dimensional semiconductor materials and the two-dimensional metal materials may be as follows: molybdenum ditelluride (MoTe.sub.2) and niobium ditelluride (NbTe.sub.2); molybdenum ditelluride (MoTe.sub.2) and titanium ditelluride (TiTe.sub.2); molybdenum ditelluride (MoTe.sub.2) and hafnium ditelluride (HfTe.sub.2); or molybdenum ditelluride (MoTe.sub.2) and zirconium ditelluride (ZrTe.sub.2). Accordingly, niobium, titanium, hafnium, or zirconium may be used to form the metal layer 16. It is to be understood that the two-dimensional semiconductor materials and the two-dimensional metal materials are not limited to the examples listed above.

(19) The semiconductor device of the present invention can be applied to field-effect transistors, gate-all-around field-effect transistors, or other devices. FIG. 2 is a schematic drawing depicting that the semiconductor device of the present invention is applied to a field-effect transistor 2. The field-effect transistor 2 includes a substrate 20, a channel 21, a source 22, a drain 23, a dielectric layer 24, a gate 25, a source pad 26, and a drain pad 27. In this embodiment, the two-dimensional semiconductor layer 12 serves as the channel 21, and the metal layer 16 serves as the source 22 and drain 23. With this structural feature, the channel 21 made of the above-mentioned two-dimensional semiconductor material and the source 22 and drain 23 made of the above-mentioned metal material will have good ohmic contact due to the presence of the two-dimensional metal conductor layer 14 therebetween. This effectively reduces the contact resistance between the two-dimensional material and the metal in the prior arts, allowing two-dimensional materials to be successfully applied to semiconductor devices, such as field-effect transistors.

(20) Furthermore, FIGS. 3 and 4 are schematic drawings depicting that the semiconductor device of the present invention is applied to a gate-all-around field-effect transistor 3. The gate-all-around field-effect transistor 3 includes a substrate 30, three channels 31, a source 32, a drain 33, a dielectric layer 34, a gate 35, and three insulating layers 36. In this embodiment, the two-dimensional semiconductor layer 12 serves as the channel 31, and the metal layer 16 serves as the source 32 and drain 33. With this structural feature, the channels 31 made of the above-mentioned two-dimensional semiconductor material and the source 32 and drain 33 made of the above-mentioned metal material will have good ohmic contact due to the presence of the two-dimensional metal conductor layers 14 therebetween, thereby achieving the objectives of the present invention.

(21) FIG. 5 is a schematic drawing depicting that the semiconductor device of the present invention is applied to another gate-all-around field-effect transistor 4. The structure of the gate-all-around field-effect transistor 4 is generally similar to that of the aforesaid field-effect transistor 3, with the difference lying in that the two ends of each of the three channels 41 extend into the source 42 and drain 43. The channels 41 made of the above-mentioned two-dimensional semiconductor material and the source 42 and drain 43 made of the above-mentioned metal material in this embodiment will also have good ohmic contact due to the presence of the two-dimensional metal conductor layers 14 therebetween, thereby achieving the objectives of the present invention.