Four-transistor static random access memory cell with enhanced data retention

Abstract

A SRAM cell comprising two PMOS transistors and two NMOS transistors is fabricated with CMOS process technology. The PMOS transistors are coupled to a supply voltage rail, a first storage node and a second storage node. The NMOS transistors are responsive to a word line and coupled to the first and the second storage nodes and a bit line pair. When the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage V.sub.stdf and a difference voltage (V.sub.DDV.sub.stdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period, where 0<V.sub.stdf<V.sub.DD.

Claims

1. A static random access memory (SRAM) cell comprising: a cross-coupled pair of PMOS transistors coupled to a supply voltage rail, a first storage node and a second storage node; and two NMOS transistors coupled to a word line, the first and the second storage nodes and a bit line pair; wherein when the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage V.sub.stdf and a difference voltage (V.sub.DDV.sub.stdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period; and wherein V.sub.DD denotes a supply voltage at the second storage node and 0<V.sub.stdf<V.sub.DD.

2. The SRAM cell according to claim 1, wherein a differential voltage between the bit line pair is related to a capacitance ratio for the bit line pair and the first and the second storage nodes.

3. The SRAM cell according to claim 2, wherein when the capacitance ratio for the bit line pair and the first and the second storage nodes is 10:1, the predefined voltage is 100 millivolts.

4. The SRAM cell according to claim 2, wherein the differential voltage between the bit line pair is fractions of V.sub.DD when the two NMOS transistors are turned on.

5. The SRAM cell according to claim 1, wherein the steady-state voltage V.sub.stdf close to the ground voltage is obtained by at least one of decreasing a pull-up leakage current curve for the cross-coupled pair of PMOS transistors and increasing a pull-down leakage current curve for the two NMOS transistors.

6. The SRAM cell according to claim 5, wherein each of the pull-up leakage current curve and the pull-down leakage current curve is a function of the floating voltage at the first storage node.

7. The SRAM cell according to claim 5, wherein silicon active areas of an N-type well (Nwell) region of the cross-coupled pair of PMOS transistors are implanted with dosages of N-type impurities of 10.sup.12 cm.sup.2 to 10.sup.14 cm.sup.2 to form the cross-coupled pair of PMOS transistors with a high threshold voltage so that the pull-up leakage current curve is decreased.

8. The SRAM cell according to claim 5, wherein the SRAM cell is fabricated from a specific CMOS process technology node with a nominal channel length, and wherein each of the cross-coupled pair of PMOS transistors has a channel length longer than the nominal channel length so that the pull-up leakage current curve is decreased.

9. The SRAM cell according to claim 5, wherein silicon active areas surrounding drain regions of the two NMOS transistors are implanted with dosages of P-type impurities of 10.sup.13 cm.sup.2 to 10.sup.15 cm.sup.2 for a P-type substrate so that the pull-down leakage current curve is increased.

10. The SRAM cell according to claim 5, wherein silicon active areas of drain regions of the two NMOS transistors are implanted with dosages of N-type impurities of 10.sup.13 cm.sup.2 to 10.sup.15 cm.sup.2 for N-type drain regions of the two NMOS transistors so that the pull-down leakage current curve is increased.

11. The SRAM cell according to claim 5, wherein each of the two NMOS transistors has an enlarged drain region located among the word line, an Nwell region and gate regions of the cross-coupled pair of PMOS transistors, where a size of the enlarged drain region is greater than that of an original drain region so that the pull-down leakage current curve is increased, and wherein a width of the original drain region is equal to a channel width of each of the two NMOS transistors.

12. The SRAM cell according to claim 5, wherein when the two NMOS transistors are turned off, a Nwell region of the cross-coupled pair of PMOS transistors is connected to the supply voltage rail and source regions of the cross-coupled pair of PMOS transistors are applied with a first voltage less than the supply voltage so that the pull-up leakage current curve is decreased.

13. The SRAM cell according to claim 12, wherein in the following data read period, the two NMOS transistors are turned on and the source regions of the cross-coupled pair of PMOS transistors are applied with the supply voltage.

14. The SRAM cell according to claim 5, wherein when the two NMOS transistors are turned off, source regions of the cross-coupled pair of PMOS transistors are connected to the supply voltage rail and a Nwell region of the cross-coupled pair of PMOS transistors is applied with a second voltage greater than the supply voltage so that the pull-up leakage current curve is decreased.

15. The SRAM cell according to claim 14, wherein in the following data read period, the two NMOS transistors are turned on and the Nwell region of the cross-coupled pair of PMOS transistors is applied with the supply voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiment of the present invention, in which:

(2) FIG. 1 shows the schematic of the conventional 6T-SRAM.

(3) FIG. 2 shows the schematic of 4T-SRAM.

(4) FIG. 3A illustrates the pull-up leakage current and the pull-down leakage current for the floating storage node N1 of 4T SRAM cell 300 in the data retention period.

(5) FIG. 3B shows the voltage timing sequence diagram for the bit lines BL and BL, storage nodes N1 and N2 and the wordline W for the 4T SRAM cell 300 in a data retention period and a data read period.

(6) FIG. 4 shows the steady-state floating storage node voltage versus the pull-up leakage current from the PMOSFET device channel diffusion current and the pull-down leakage current from the reverse N-drain/P-substrate junction leakage current of the access NMOSFET device in the 4T SRAM cell.

(7) FIG. 5 shows PMOSFET device electrical characteristics of drain current versus the applied gate voltage for high threshold voltage V.sub.thH PMOSFET device (dotted line 503), regular threshold voltage V.sub.thR PMOSFET device (solid line 502), and low threshold voltage V.sub.thL PMOSFET device (dashed line 501) from the CMOS process technology provided by a foundry.

(8) FIG. 6 shows electrical characteristics of drain current versus the applied gate voltage for PMOSFET devices with (1) 90% of the nominal channel (gate) length L.sub.pn (dotted line 601), (2) 100% of the nominal channel (gate) length L.sub.pn (solid line 602), and (3) 110% of the nominal channel (gate) length L.sub.pn (dashed line 603) from the CMOS process technology provided by a foundry.

(9) FIG. 7 shows the PMOSFET device electrical characteristics of drain current versus applied gate voltage with Nwell 310 biased at the high voltage rail V.sub.DD and the source electrode 311/321 applied with (a) V.sub.DD (dashed line 701), (b) V.sub.DD0.1V (solid line 702), and (c) V.sub.DD0.2V (dotted line 703).

(10) FIG. 8 shows the top view of two 4T SRAM cells and the high dosage impurity implant areas 801 for the high threshold storage PMOSFET devices in the two 4T SRAM cells according to one embodiment of the invention.

(11) FIG. 9 shows the top view of two 4T SRAM cells for the storage PMOSFET devices with a channel (gate) length L.sub.p longer than the nominal channel (gate) length L.sub.pn from a CMOS process technology node according to one embodiment of the invention.

(12) FIG. 10 shows the circuit schematic of the back-biased scheme for the PMOSFET devices in a row of 4T SRAM cells according to one embodiment of the invention.

(13) FIG. 11 shows the circuit schematic of the alternative back-biased scheme for the PMOSFET devices in a row of 4T SRAM cells according to another embodiment of the invention.

(14) FIG. 12A shows the top view of two 4T SRAM cells and the high dosage impurity implant areas 1210 for obtaining higher junction leakage current for the drain electrodes of access NMOSFET devices in 4T SRAM according to one embodiment of the invention.

(15) FIG. 12B shows the top view of two 4T SRAM cells in FIG. 12A before the first metals are formed.

(16) FIG. 13A shows the top view of two 4T SRAM cells and the access NMOSFET devices with the enlarged N-drain/P-substrate junction areas 1311 for the increase of pull-down leakage current according to one embodiment of the invention.

(17) FIG. 13B shows the top view of two 4T SRAM cells in FIG. 13A before the first metals are formed.

DETAILED DESCRIPTION OF THE INVENTION

(18) The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and various MOSFET devices such as FinFET devices, and GAA (Gate All Around) devices may be made without departing from the scope of the present invention. Also, it is to be understood that the methods of embodiment are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiment of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiment of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure.

(19) In one embodiment, the high threshold voltage PMOSFET devices with low channel diffusion leakage currents are applied for the storage PMOSFET devices in the 4T SRAM cells for the reduction of pull-up leakage current. FIG. 8 shows the top view of two horizontally mirrored 4T SRAM cells 800 (up/down) according to the topology design rules from a specific CMOS logic process technology node provided by a foundry. In FIG. 8, each 4T SRAM cell 800 includes two PMOSFET devices 831 and 832 and two access NMOSFET devices 833 and 834. To obtain the high threshold voltage storage PFET devices 831 and 832 in the 4T SRAM cells 800, the higher dosages (10.sup.12 cm.sup.210.sup.14 cm.sup.2) of N-type impurities such as arsenic or phosphorous are implanted into the silicon active areas of the Nwell areas 801 in the 4T SRAM cells 800 shown in FIG. 8.

(20) In one embodiment, the PMOSFET devices with channel (gate) lengths L.sub.p longer than the nominal channel (gate) length L.sub.pn from a CMOS process technology node provided by a foundry are applied for the storage PMOSFET devices in the 4T SRAM cells for the reduction of pull-up leakage current. FIG. 9 shows the top view of two horizontally mirrored 4T SRAM cells (up/down) 900 with two storage PMOSFET devices 931 and 932 having channel (gate) length L.sub.p 901 longer than the nominal (gate) length L.sub.pn provided by a specific CMOS process technology node. For example, if a nominal channel (gate) length L.sub.pn=40 nm for the 40 nm CMOS process technology node, the channel (gate) length L.sub.p 901 is greater than or equal to (1.1L.sub.pn), such as 45 nm.

(21) In one embodiment, the 4T SRAM cell arrays are fabricated with a CMOS process technology node. FIG. 10 shows a schematic diagram of a circuit for a row of n 4T SRAM cells 1000 in the configuration of cell array based on the back-biased scheme for reducing the pull-up leakage current (PMOSFET device channel diffusion leakage current). In FIG. 10, with the Nwell 1001 biased at V.sub.DD, the source electrodes 1002 of the storage PMOSFET devices for the row of 4T SRAM cells 1000 is applied with the voltage V.sub.srtn=(V.sub.DDV) in data retention period (such as the data retention period in FIG. 3B), where V is a positive voltage bias less than V.sub.DD. When the row of n 4T SRAM cells 1000 is active for read operations (such as the data read period in FIG. 3B), the voltage potential at the source electrodes 1002 of the storage PMOSFET devices for the row of n 4T SRAM cells 1000 is resumed from the voltage V.sub.srtn to the normal operational voltage V.sub.DD with the Nwell 1001 still biased at V.sub.DD as illustrated on the left side of FIG. 10.

(22) In one embodiment, the 4T SRAM cell arrays are fabricated with a CMOS process technology node. FIG. 11 shows a schematic diagram of a circuit for a row of n 4T SRAM cells 1100 in the configuration of cell array based on the alternative back-biased scheme for reducing the pull-up leakage current (PMOSFET device channel diffusion leakage current). In FIG. 11, the source electrodes 1102 of the storage PMOSFET devices for the row of 4T SRAM cells 1100 are biased at the high voltage rail V.sub.DD and the Nwell voltage potential V.sub.Nwell for the Nwell 1101 is applied with the high voltage V.sub.HNW=(V.sub.DD+V) in data retention period (i.e., two NMOSFET devices are turned off), where V is a positive voltage bias less than V.sub.DD. When the row of n 4T SRAM cells 1100 is active for read operations (i.e., two NMOSFET devices are turned on), the Nwell voltage potential V.sub.Nwell of the Nwell 1101 for the row of n 4T SRAM cells 1100 is then reduced from the high voltage V.sub.HNW to the read operational high voltage V.sub.DD with the source electrodes 1102 still biased at V.sub.DD as illustrates on the left side of FIG. 11.

(23) To increase the pull-down leakage current in 4T SRAM cells for obtaining a low steady-state floating storage node voltage V.sub.stdf close to the ground voltage V.sub.SS is to increase the reverse N-drain/P-substrate junction leakage current for the drain electrodes of the access NMOSFET devices connected to the storage nodes in the 4T SRAM cells, such as, by increasing N/P junction impurity concentrations. In one embodiment, each of the two 4T SRAM cells 120 includes two PMOSFET devices 231 and 232 and two access NMOSFET devices 233 and 234; there are three ways as follows to form the high leakage N-drain/P-substrate junctions (i.e., to increase N/P junction impurity concentrations) for the drain electrodes of the access NFET devices 233 and 234 as shown in FIGS. 12A-12B: (1) the high dosages (10.sup.13 cm.sup.210.sup.15 cm.sup.2) of P-type impurities for the P-type substrate are implanted into the silicon active areas 1210 (surrounding drain electrode areas of two access NFET devices 233 and 234) of the two 4T SRAM cells (top/down cells) 120; (2) the high dosages (10.sup.13 cm.sup.210.sup.15 cm.sup.2) of N-type impurities for the N-type drain electrodes are implanted into the silicon active areas 1210 (i.e., drain electrode areas of two access NFET devices 233 and 234) of the two 4T SRAM cells (top/down cells) 120; (3) both (the above two high dosages of P-type impurities and N-type impurities) are implanted into the silicon active areas 1210 (surrounding and including drain electrode areas of two access NFET devices 233 and 234).

(24) To increase the pull-down leakage current in 4T SRAM cells for obtaining a low steady-state floating storage node voltage V.sub.stdf close to the ground voltage V.sub.SS is to increase the reverse N-drain/P-substrate junction leakage current for the drain electrodes of the two access NMOSFET devices connected to the two storage nodes in 4T SRAM cells, such as, by increasing N/P junction areas. In one embodiment, the drain electrode areas for the access NMOSFET devices in 4T SRAM cells are enlarged to increase the pull-down leakage current for obtaining a low steady-state floating storage node voltage V.sub.stdf. In FIGS. 13A-13B, each 4T SRAM cell 130 includes two PMOSFET devices 131 and 132 and two access NMOSFET devices 133 and 134; a drain width 138 of the enlarged drain electrode areas 1311 (represented by the large dotted lines) of the access NFET devices 133 and 134 in 4T SRAM cells 130 is increased from the minimum device drain width (equal to the channel width) 136 of the original drain electrode area 1310 (represented by the thin solid lines) for increasing the pull-down leakage current, where the drain width 138 is greater than the minimum device drain width 136. The enlarged drain electrode areas 1311 are located among and isolated from the Nwell areas 150, the gates of PFET devices 131 and 132 and the wordlines 1 and 2 of the access NFET devices 133 and 134. Thus, the largest size of the enlarged drain electrode areas 1311 depends on the topology design rule limitation of a specific CMOS process technology node. A size of the enlarged drain electrode areas 1311 are greater than that of the original drain electrode areas 1310. In an embodiment, a size of the enlarged drain electrode areas 1311 are approximately two times greater than that of the original drain electrode areas 1310.

(25) The aforementioned description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiment disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. The embodiment is chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiment and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiment of the invention. It should be appreciated that variations may be made in the embodiment described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.