Charger

Abstract

A charger is configured such that in case where control of switching of a DC/DC converter includes a first mode and a second mode, a dead time is provided between the first mode and the second mode when switching from the first mode to the second mode and a first switch of a power pulsation absorbing circuit is controlled to be in an off-state during a time until expiration of a predetermined time after start of the dead time, wherein in the first mode, at least one switch of switches of the DC/DC converter is switched on, at least one switch of the switches of the DC/DC converter is switched off, and the first switch of the power pulsation absorbing circuit is switched off, and wherein in the second mode, the switch of the DC/DC converter which is switched off in the first mode is switched on, and the first switch of the power pulsation absorbing circuit is switched on.

Claims

1. A charger comprising: a rectifier including two input terminals, a cathode terminal and an anode terminal, wherein the two input terminals are configured for connection to an AC power supply; a DC/DC converter including a first terminal, a second terminal and two output terminals, the first terminal being configured to be connected to the cathode terminal of the rectifier via a first line, the second terminal being configured to be connected to the anode terminal of the rectifier via a second line, wherein the output terminals are configured for connection to a battery; a power pulsation absorbing circuit including a first diode, a second diode, a third diode, an inductor, a capacitor, a first switch and a second switch; and a controller configured to control switching of switches of the DC/DC converter and switching of the first switch and the second switch, wherein the first diode is connected between the inductor of the power pulsation absorbing circuit and one of the two input terminals of the rectifier, and the second diode is connected between the inductor and another of the two input terminals of the rectifier, wherein the capacitor and the first switch are connected in series between the first line and the second line with the capacitor being arranged closer to the second line than the first switch, wherein the third diode is connected between the inductor of the power pulsation absorbing circuit and a line which connects the capacitor to the first switch, wherein the second switch is connected between the second line and a line which connects the inductor of the power pulsation absorbing circuit to the third diode, wherein in case where control of switching of the DC/DC converter by the controller includes a first mode and a second mode, the controller is configured to: provide a dead time between the first mode and the second mode when switching from the first mode to the second mode; and control the first switch of the power pulsation absorbing circuit to be in an off-state during a time until expiration of a predetermined time after start of the dead time, wherein in the first mode, at least one switch of the switches of the DC/DC converter is switched on, at least one switch of the switches of the DC/DC converter is switched off, and the first switch of the power pulsation absorbing circuit is switched off, and wherein in the second mode, the switch of the DC/DC converter which is switched off in the first mode is switched on, and the first switch of the power pulsation absorbing circuit is switched on.

2. The charger according to claim 1, wherein the DC/DC converter includes a leg on a primary side, the leg including a first switch and a second switch, wherein in the first mode, the first switch of the DC/DC converter is switched on, and the second switch of the DC/DC converter and the first switch of the power pulsation absorbing circuit are switched off, and wherein in the second mode, the first switch of the DC/DC converter is switched off, and the second switch of the DC/DC converter and the first switch of the power pulsation absorbing circuit are switched on.

3. The charger according to claim 1, wherein on a primary side, the DC/DC converter includes a leg with a first switch and a second switch and a leg with a third switch and a fourth switch, wherein in the first mode, the first switch and the fourth switch of the DC/DC converter are switched on, and the second switch and the third switch of the DC/DC converter as well as the first switch of the power pulsation absorbing circuit are switched off, and wherein in the second mode, the first switch and the fourth switch of the DC/DC converter are switched off, and the second switch and the third switch of the DC/DC converter as well as the first switch of the power pulsation absorbing circuit are switched on.

4. The charger according to claim 1, wherein the controller is configured to control the switches of the DC/DC converter and the first switch according to a continuous current mode during one entire phase of an AC voltage inputted from the AC power supply.

5. The charger according to claim 4, wherein in the continuous current mode, the controller is configured to change switching frequencies of the switches of the DC/DC converter and the first switch.

6. The charger according to claim 5, wherein the controller is configured to: control switching of the switches of the DC/DC converter and the first switch to obtain an operation waveform of the inductor of the DC/DC converter which is approximable by a rectangular waveform; and control a set value of a peak value of the rectangular waveform in such a manner that a minimum value of the switching frequencies becomes a first frequency value.

7. The charger according to claim 1, wherein the controller is configured to control the switches of the DC/DC converter and the first switch according to a discontinuous current mode during one entire period of an AC voltage inputted from the AC power supply.

8. The charger according to claim 7, wherein in the discontinuous current mode, the controller is configured not to change switching frequencies of the switches of the DC/DC converter and the first switch.

9. The charger according to claim 1, wherein the controller is configured to: control the switches of the DC/DC converter and the first switch according to a continuous current mode during a first phase of one period of an AC voltage inputted by the AC power supply; and control the switches of the DC/DC converter and the first switch according to a discontinuous current mode during a phase of the period of the AC voltage which is different from the first phase.

10. The charger according to claim 1, wherein the DC/DC converter is configured as a DAB (Dual Active Bridge) converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a charger 100 according to an embodiment of the present invention;

(2) FIG. 2 shows a relation between an instantaneous power p.sub.S outputted from an AC power supply and an instantaneous power pc outputted from a buffer capacitor Cbuf;

(3) FIG. 3 shows states of each of switches in various modes;

(4) FIG. 4 shows an operation waveform i.sub.L of an inductor L of a DC/DC converter 120 according to the embodiment and a corresponding equivalent rectangular waveform i.sub.L (discontinuous current mode);

(5) FIG. 5 shows an operation waveform i.sub.L of an inductor L of a DC/DC converter 120 according to the embodiment and a corresponding equivalent rectangular waveform i.sub.L (continuous current mode);

(6) FIG. 6 shows an exemplar switching frequency f.sub.SW when a current set value I.sub.L is optimized;

(7) FIG. 7 shows an example of a change of the switching frequency f.sub.SW in the case of mixed operation with continuous and discontinuous current mode;

(8) FIG. 8 shows an example of a change of the switching frequency f.sub.SW in the case of mixed operation with continuous and discontinuous current mode;

(9) FIG. 9 shows an example of changes of gate-source voltages v.sub.gs21, v.sub.gs22 and v.sub.gs31 as well as drain-source voltages v.sub.ds21, v.sub.ds22, and v.sub.ds31 of a first switch and a second switch of the DC/DC converter 120 and a first switch S31 of a power pulsation absorbing circuit 130 during switching from mode 3 to mode 4;

(10) FIG. 10 shows a diagram for explanation of a current flow before time t.sub.30 according to FIG. 9;

(11) FIG. 11 shows an example of changes of gate-source voltages v.sub.gs21, v.sub.gs22 and v.sub.gs31 as well as drain-source voltages v.sub.ds21, v.sub.ds22, and v.sub.ds31 of a first switch and a second switch of the DC/DC converter 120 and a first switch S31 of a power pulsation absorbing circuit 130 during switching from mode 3 to mode 4;

(12) FIG. 12 shows a diagram for explanation of a current flow between time t.sub.32 and time t.sub.34 according to FIG. 11.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(13) <Charger 100>

(14) FIG. 1 shows a charger 100 according to an embodiment of the present invention. The charger 100 includes a rectifier 110, a DC/DC converter 120, a power pulsation absorbing circuit 130, and a controller 140. The charger 100 converts the single-phase AC voltage v.sub.S inputted from the single-phase AC power supply 200 to a DC voltage V.sub.dc, and outputs it to a battery 300.

(15) The rectifier 110 includes a cathode terminal 111 and an anode terminal 112 connected to DC/DC converter 120, and two input terminals 113 for connection to the AC power supply 200. For example, the rectifier 110 is configured as a bridge diode rectifier formed by four diodes, receives an AC current applied between the two input terminals 113 connected to the AC power supply, converts the current into a DC current and outputs it from the cathode terminal 111, as shown in FIG. 1. As shown in FIG. 1, the rectifier 110 may be configured to be connected to the AC power supply 200 via a filter F, wherein the filter F includes an inductor Lac and a capacitor Cac.

(16) For example, the DC/DC converter 120 is configured as a DAB (Dual Active Bridge) converter. The DC/DC converter 120 includes a first terminal 121, a second terminal 122, a third terminal 123 and a fourth terminal 124, the first terminal 121 being connected to the cathode terminal 111 of the rectifier 110, the second terminal 122 being connected to the anode terminal 112 of the rectifier 110, wherein the third and fourth terminals 123 and 124 are configured for connection to a positive electrode and a negative electrode of the battery 300, respectively. The DC/DC converter 120 includes a transformer Tr, a full bridge circuit with four switches on an input side (primary side), i.e., a first switch S21, a second switch S22, a third switch S23 and a fourth switch S24, and a full bridge circuit with four switches on an output side (secondary side), i.e., a fifth switch S25, a sixth switch S26, a seventh switch S27 and an eighth switch S28, wherein the transformer Tr is arranged between the full bridge circuit on the input side and the full bridge circuit on the output side. For example, each of the eight switches S21S28 is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, the N-channel power MOSFET may include a snubber capacitor, as shown in FIG. 1.

(17) The full bridge circuit on the primary side of the DC/DC converter 120 includes two legs connected between the first terminal 121 and the second terminal 122 (a leg including a first switch S21 and a second switch S22 and a leg including a third switch S23 and a fourth switch S24), while the full bridge circuit on the secondary side of the DC/DC converter 120 includes two legs between the third terminal 123 and the fourth terminal 124 (a leg including a fifth switch S25 and a sixth switch S26 and a leg including a seventh switch S27 and an eighth switch S28).

(18) The DC/DC converter 120 includes an inductor L on the primary side of the transformer Tr. For example, this inductor L is a leakage inductor of the transformer Tr.

(19) Further, a DC capacitor Cdc is connected between the third terminal 123 and the fourth terminal 124 of DC/DC converter 120. An inductor Ldc may be connected between the third terminal 123 of the DC/DC converter 120 and the positive electrode of the battery 300.

(20) The power pulsation absorbing circuit 130 includes a first diode D31, a second diode D32, a third diode D33, an inductor Lb, a buffer capacitor Cbuf, a first switch S31, and a second switch S32.

(21) The first diode D31 of power pulsation absorbing circuit 130 is connected between the inductor Lb of the power pulsation absorbing circuit 130 and one of the two input terminal 113 of the rectifier 110. The second diode D32 of power pulsation absorbing circuit 130 is connected between the inductor Lb of the power pulsation absorbing circuit 130 and the other of the two input terminal 113 of the rectifier 110. In this case, each of the first diode D31 and second diode D32 of the power pulsation absorbing circuit 130 is connected between the inductor Lb of the power pulsation absorbing circuit 130 and the input terminals 113 of the rectifier 110 so that these diodes have a forward direction extending from the input terminals 113 of the rectifier 110 to the inductor Lb. Therefore, even when the AC power supply 200 is connected to the input terminals 113 of the rectifier 110, a DC current is applied to the inductor Lb of power pulsation absorbing circuit 130.

(22) The buffer capacitor Cbuf of the power pulsation absorbing circuit 130 and the first switch S31 are connected in series between a first line LH and a second line LL, wherein the first line LH connects the cathode terminal 111 of the rectifier 110 to the first terminal 121 of the DC/DC converter 120, and the second line LL connects the anode terminal 112 of the rectifier 110 to the second terminal 122 of the DC/DC converter 120. The buffer capacitor Cbuf is arranged closer to the second line LL, and the first switch 31 is arranged closer to the first line LH. The first switch S31 is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, a source and a drain of the N-channel power MOSFET may be preferably connected to the first line LH and the buffer capacitor, respectively.

(23) The third diode D33 of the power pulsation absorbing circuit 130 is connected between line connecting the buffer capacitor Cbuf of the power pulsation absorbing circuit 130 to the first switch S31 on the one hand and the inductor Lb of the power pulsation absorbing circuit 130 on the other hand so that the third diode D33 has a forward direction along a direction extending from the inductor Lb to this line.

(24) The second switch S32 of the power pulsation absorbing circuit 130 is connected between the second line LL and a line connecting the inductor Lb of the power pulsation absorbing circuit 130 to the third diode D33. The second switch S32 is configured as an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a reverse polarity diode (body diode). In this case, a drain of the N-channel power MOSFET may be preferably connected to the line connecting the inductor Lb of the power pulsation absorbing circuit 130 to the third diode D33, wherein a source of the N-channel power MOSFET may be preferably connected to the second line LL.

(25) The controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120 as well as switching of the switches S31 and S32 of the power pulsation absorbing circuit 130.

(26) Since the power pulsation absorbing circuit 130 includes a first diode D31, a second diode D32, a third diode D33, an inductor Lb, a buffer capacitor Cbuf, a first switch S31, and a second switch S32, the power pulsation absorbing circuit 130 may serve as a power factor correction (PFC) circuit. Therefore, according to the present embodiment, control is possible which provides the following sinusoidal voltage v.sub.S and sinusoidal current is to the charger 100 from the AC power supply 200:

(27) $v_S\left(t\right)=\sqrt{2}{V}_S\sin {}_{S}t$$i_S\left(t\right)=\sqrt{2}{I}_S\sin {}_{S}t$ wherein V.sub.S indicates an effective value of the power supply voltage and I.sub.S indicates an effective value of the power supply current.

(28) In this case, an instantaneous power p.sub.S outputted from the AC power supply 200 is formed by a sum of an average power P (=V.sub.SI.sub.S) and a pulsation component p.sub.rip(t) (=V.sub.SI.sub.S cos 2st) as shown below, wherein the instantaneous power p.sub.S pulsates around the average power P (dashed line in FIG. 2) with an angular frequency which is twice as high as an angular frequency of the AC, as shown with a solid line in FIG. 2.

(29) $p_S\left(t\right)=v_S{i}_S=V_S{I}_S\left(1-\cos 2{}_{S}t\right)=P+p_{\mathrm{rip}}\left(t\right)$

(30) For the above-mentioned reasons, the controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120 as well as switching of the switches S31 and S32 of the power pulsation absorbing circuit 130 to absorb power pulsation due to the AC power supply in the power pulsation absorbing circuit 130 so that a constant power is inputted to the DC/DC converter 120.

(31) In this case, the charger 100 according to the present embodiment is provided such that different controls are applied for the instantaneous power from the AC power supply 200 being higher than the average power (p.sub.S>P) and for the instantaneous power being lower than the average power (p.sub.S<P).

(32) In the case of the instantaneous power p.sub.S from the AC power supply being higher than the average power P (p.sub.S>P), switching of the eight switches S21 to S28 of the DC/DC converter 120 and the two switches S31 and S32 of the power pulsation absorbing circuit 130 are controlled to charge the pulsation component p.sub.rip of the instantaneous power p.sub.S from the AC power supply 200 to the buffer capacitor Cbuf via the inductor Lb of the power pulsation absorbing circuit 130, whereby only the average power P of the power outputted from the AC power supply may be provided to the DC/DC converter 120. This means that according to the present embodiment, the buffer capacitor Cbuf is charged in a phase in which a higher instantaneous power p.sub.S than the average power P is outputted from the AC power supply (charging phase), wherein a negative instantaneous power p.sub.C is outputted from the buffer capacitor Cbuf, as shown with a dashed dotted line in FIG. 2.

(33) On the other hand, in the case of the instantaneous power p.sub.S from the AC power supply 200 being lower than the average power P (p.sub.S<P), switching of the eight switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 are controlled while maintaining the second switch S32 of the power pulsation absorbing circuit 130 in an off-state to actively discharge the buffer capacitor Cbuf via the first switch S31. This compensates the pulsation component p.sub.rip, i.e., a difference between the instantaneous power p.sub.S and the average power P outputted from the AC power supply 200 to input the average power P to the DC/DC converter 120. This means that according to the present embodiment, the buffer capacitor Cbuf is discharged in a phase in which a lower instantaneous power p.sub.S than the average power P is outputted from the AC power supply (discharging phase), wherein a positive instantaneous power p.sub.C is outputted from the buffer capacitor Cbuf, as shown with a dashed dotted line in FIG. 2.

(34) In other words, according to the present embodiment, the controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120, the switches S31 and S32 of the power pulsation absorbing circuit 130 to obtain a constant sum of the instantaneous power p.sub.S outputted from the AC power supply 200 and the instantaneous power pc outputted from the buffer capacitor Cbuf.

(35) In this manner, the present embodiment is provided such that the buffer capacitor Cbuf is actively discharged during the discharging phase. Consequently, the present embodiment enables an amount of power accumulated in the buffer capacitor Cbuf (i.e., capacitance of the buffer capacitor Cbuf) to be limited, whereby the buffer capacitor Cbuf can be reduced in size.

(36) Further, according to the present embodiment, the second switch S32 is activated only during the charging phase. Consequently, the present embodiment enables an amount of power accumulated in the inductor Lb (i.e., inductance of the inductor Lb) to be limited, whereby the inductor Lb can be reduced in size.

(37) Further, according to the present embodiment, a power without pulsation is inputted to the DC/DC converter 120. Consequently, the present embodiment enables the transformer Tr of the DC/DC converter 120 and/or the DC capacitor Cdc to be reduced in size.

(38) In this manner, the present embodiment enables passive elements to be reduced in size, for example capacitors and inductors. Consequently, the present embodiment enables a compact charger to be provided which can absorb pulsation of power.

(39) <Switching Modes and Operation Waveform>

(40) The controller 140 controls switching of the switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 according to seven modes to obtain an operation waveform it of the inductor L of the DC/DC converter 120 which is approximable by a rectangular waveform. FIG. 3 shows respective states of each of switches in the seven modes. The seven modes a mode (mode 5) in which the switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 are all switched off.

(41) FIG. 4 shows an operation waveform i.sub.L of an inductor L of a DC/DC converter 120 according to the present embodiment and a corresponding equivalent rectangular waveform i.sub.L. This operation waveform it is obtained by switching the seven modes as shown in FIG. 3 to mode 1, mode 2, mode 3, mode 4, mode 5, mode 4, mode 6, mode 7, mode 1 and mode 5 in this order. In this case, a current i.sub.L is obtained in each of the seven modes as follows (Patent Document 1 and Non-Patent Document 1):

(42) $\begin{array}{cc}{i}_L\left(t\right)=\{\begin{array}{cc}\frac{v_C+V_{dc}}{L}\left(t-t_{c1}\right)+i_L\left(t_{c1}\right)& \left(\mathrm{Mode}1\right)\\ \frac{v_C-V_{dc}}{L}\left(t-t_{c2}\right)+i_L\left(t_{c2}\right)& \left(\mathrm{Mode}2\right)\\ \frac{v_{\mathrm{rec}}-V_{dc}}{L}\left(t-t_{c3}\right)+i_L\left(t_{c3}\right)& \left(\mathrm{Mode}3\right)\\ -\frac{v_C+V_{dc}}{L}\left(t-t_{c4}\right)+i_L\left(t_{c4}\right)& \left(\mathrm{Mode}4\right)\\ 0& \left(\mathrm{Mode}5\right)\\ -\frac{v_{\mathrm{rec}}-V_{dc}}{L}\left(t-t_{c6}\right)+i_L\left(t_{c6}\right)& \left(\mathrm{Mode}6\right)\\ -\frac{v_C-V_{dc}}{L}\left(t-t_{c7}\right)+i_L\left(t_{c7}\right)& \left(\mathrm{Mode}7\right)\end{array}& \left(1\right)\end{array}$ wherein t.sub.cn (n=1 to 7) indicates a time at which switching to mode n is performed.

(43) According to the present embodiment, in order to discharge the buffer capacitor Cbuf more actively when the first switch S31 of the power pulsation absorbing circuit 130 is in an on-state, the controller 140 controls a voltage v.sub.C applied to the buffer capacitor Cbuf such that the voltage v.sub.C is always higher than an instantaneous voltage v.sub.rec outputted from the rectifier 110. Therefore, according to the present embodiment, the voltage v.sub.C applied to the buffer capacitor Cbuf has a value which is different from the instantaneous voltage v.sub.rec of the rectifier 110, and modes 2 and 3 have different gradients of the operation waveform i.sub.L. Similarly, modes 6 and 7 have different gradients of the operation waveform i.sub.L. In this manner, the present embodiment enables operation waveforms to be generated which are asymmetrical with respect to i.sub.L=0 in positive and negative waveforms, as shown in FIG. 4.

(44) For the operation waveform it as shown in FIG. 4, it is possible to approximate it by an equivalent rectangular waveform i.sub.L if to t.sub.0 t.sub.10 are set such that |t.sub.0-t.sub.1|=|t.sub.5-t.sub.6|, |t.sub.1-t.sub.2|=|t.sub.7-t.sub.8|, |t.sub.2-t.sub.3|=|t.sub.6-t.sub.7|, |t.sub.3-t.sub.4|=|t.sub.8-t.sub.9|, and if t.sub.S1 and t.sub.S2 are set between t.sub.3 and t.sub.4 and between t.sub.8 and t.sub.9 respectively such that |t.sub.0-t.sub.1|=|t.sub.S1-t.sub.4|=|t.sub.S2-t.sub.9|.

(45) $i_L^{}\left(t\right)=\{\begin{array}{cc}\frac{i_L\left(t_1\right)+i_L\left(t_3\right)}{2}=I_L^{}& \left(t_{1}t{t}_{S1}\right)\\ -I_L^{}& \left(t_{6}t{t}_{S2}\right)\\ 0& \left(t_{0}t<t_1,t_{S1}<t<t_6,t_{S2}<t<t_{10}\right)\end{array}$

(46) If phases of to t.sub.0t.sub.1, t.sub.S1t.sub.4, t.sub.5t<t.sub.6, and t.sub.S2t<t.sub.9 of the equivalent rectangular waveform i.sub.L are defined as reactive current phases T.sub.q, phases of t.sub.1t<t.sub.2 and t.sub.7t<t.sub.8 are defined as buffer capacitor discharge current phases T.sub.C, phases of t.sub.2t<t.sub.3 and t.sub.6t<t.sub.7 are defined as power supply current phases T.sub.rec, phases of t.sub.3t<t.sub.S1 and t.sub.8t<t.sub.S2 are defined as current balance phases T.sub.b, and phases of t.sub.4t<t.sub.5 and t.sub.9<t<t.sub.10 are defined as zero current phases T.sub.0, a duty cycle for each of the phases within a switching period T.sub.SW is as follows:

(47) $\begin{array}{cc}\{\begin{array}{c}{D}_q=\frac{2T_q}{T_{\mathrm{SW}}}=\frac{2I_L^{}L}{\left(v_C+V_{dc}\right)T_{\mathrm{SW}}}-\frac{D_b}{2}\\ D_C=\frac{2T_C}{T_{\mathrm{SW}}}=\frac{i_C}{I_L^{}}+D_b=\frac{\left(v_{\mathrm{rec}}-V_{dc}\right)i_{\mathrm{rec}}+(v_C+V_{dc}{\mathrm{\_i}}_C}{2V_{dc}{I}_L^{}}\\ D_{\mathrm{rec}}=\frac{2T_{\mathrm{rec}}}{T_{\mathrm{SW}}}=\frac{i_{\mathrm{rec}}}{I_L^{}}\\ D_b=\frac{2T_b}{T_{\mathrm{SW}}}=\frac{\left(v_{\mathrm{rec}}-V_{dc}\right)i_{\mathrm{rec}}+\left(v_c-v_{dc}\right)i_C}{2V_{dc}{I}_L^{}}\\ D_0=\frac{2T_0}{T_{\mathrm{SW}}}=1-\left(2D_q+D_C+D_{\mathrm{rec}}+D_b\right)\end{array}& \left(2\right)\end{array}$
The duty cycle of each of the phases can be obtained by giving i.sub.rec, i.sub.C, v.sub.C and V.sub.dc. I.sub.L as set values. The obtained duty cycles of phases may be used to determine a control rule for the operation waveform i.sub.L in FIG. 4. Among these set values, set values i.sub.rec* and i.sub.C* for i.sub.rec and i.sub.C are switched as follows for the discharging phase and charging phase, wherein the power pulsation absorbing circuit 130 is operated to function as a PFC circuit and as a circuit for absorbing power pulsation:

(48) $i_{\mathrm{rec}}^{*}=\{\begin{array}{cc}\sqrt{2}\frac{P}{V_S}.Math.\sin {}_{S}t.Math.& \left(\mathrm{Discharging}\mathrm{phase}\right)\\ \frac{P}{\sqrt{2}{V}_S.Math.\sin {}_{S}t.Math.}& \left(\mathrm{Charging}\mathrm{phase}\right)\end{array}$$i_C^{*}=\{\begin{array}{cc}\frac{P}{v_C}\cos 2{}_{s}t& \left(\mathrm{Discharging}\mathrm{phase}\right)\\ 0& \left(\mathrm{Charging}\mathrm{phase}\right)\end{array}$
<Discontinuous Current Mode and Continuous Current Mode>

(49) The operation waveform as shown in FIG. 4 is obtained by switching the switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 at a constant switching frequency f.sub.SW without changing the switching frequency f.sub.SW. The operation waveform as shown in FIG. 4 includes zero current phases T.sub.0 in which the current i.sub.L flowing through the reactor L is zero. An operation by switching to mode 1, mode 2, mode 3, mode 4, mode 5, mode 4, mode 6, mode 7, mode 1 and mode 5 in this order as shown FIG. 4 is a discontinuous current mode (DCM).

(50) The zero current phase T.sub.0 is mode 5, wherein in this phase, all the switches S21 to S28 of DC/DC converter 120 are switched off. However, the switches are practically switched off at times which are offset, wherein this offset causes residual current and thus resonance between the inductor L of the DC/DC converter 120 and parasitic capacitances of the switches S21 to S28. Therefore, in the discontinuous current mode, switching after the zero current phase T.sub.0 (switching in a changing process from mode 5 to mode 4, switching in a changing process from mode 5 to mode 1) will become hard switching, which results in switching loss.

(51) Therefore, the switching frequencies f.sub.SW the switches S21 to S28 of the DC/DC converter 120 and/or of the switch S31 of the power pulsation absorbing circuit 130 may be preferably changed within one period of the AC voltage v.sub.S inputted from the AC power supply 200 so that no zero current phase T.sub.0 exists, namely so that operation in a continuous current mode (CCM) is achieved (Non-Patent Documents 2 and 3). In this manner, it is possible to remove oscillation of a current i.sub.L and a voltage V.sub.L of the inductor L and to avoid hard switching after the zero current phase T.sub.0 to control the charger 100 more efficiently in the continuous current mode.

(52) By solving the formula (2) with D.sub.0=0, the switching frequency f.sub.SW with which no zero current phase T.sub.0 exists, i.e., the switching frequency f.sub.SW in the continuous current mode, is determined as follows:

(53) $\begin{array}{cc}{f}_{\mathrm{SW}}=\frac{v_C+V_{dc}}{4I_L^{}L}\left(1-D_{\mathrm{rec}}-D_C\right)& \left(3\right)\end{array}$

(54) FIG. 5 shows an operation waveform i.sub.L of the inductor L of the DC/DC converter 120 and a corresponding equivalent rectangular waveform i.sub.L in the continuous current mode. Since no operation in the mode 5 is carried out in the continuous current mode, the switches S21 to S28 of the DC/DC converter 120 and the switch S31 of the power pulsation absorbing circuit 130 are switched to mode 1, mode 2, mode 3, mode 4, mode 6, mode 7 and mode 1 in this order.

(55) It is possible to operate the charger 100 more efficiently by optimizing a set value of the peak value I.sub.L of the equivalent rectangular wave i.sub.L (Non-Patent Documents 2 and 3). For example, the set value of the peak value I.sub.L of the equivalent rectangular waveform i.sub.L may be controlled so as to obtain a predetermined value (first frequency value) f.sub.1 of the switching frequency f.sub.SW (the above formula (3)) at a phase st of 45 degrees of the AC power supply voltage v.sub.S as shown in FIG. 6, whereby the charger 100 can be operated more efficiently. In this case, the set value I.sub.L* of the peak value I.sub.L of the equivalent rectangular waveform i.sub.L is determined as follows:

(56) $\begin{array}{cc}{I}_L^{*}=\frac{V_{dc}+V_{C_{min}}}{8f_{1}L}\left[1-\sqrt{1-\frac{8f_1{\mathrm{LI}}_S\left(V_s+V_{dc}\right)}{V_{dc}\left(V_{dc}+V_{c_{min}}\right)}}\right]& \left(4\right)\end{array}$$v_{C_{min}}=\sqrt{V_{C_{\mathrm{ma}x}}^2-\frac{2P}{{}_S{C}_{\mathrm{buf}}}}$ wherein V.sub.Cmin indicates a minimum value of the voltage applied to the buffer capacitor Cbuf. FIG. 6 shows an example of a change of the switching frequency f.sub.SW at output power values Pout of 1 KW, 3 kW and 7 KW of the DC/DC converter 120.

(57) The controller 140 may control the switches S21 to S28 of the DC/DC converter 120 and the switch S31 of the power pulsation absorbing circuit 130 according to the discontinuous current mode during all phases of one period of the AC voltage v.sub.S inputted from the AC power supply 200, or may also control the switches S21 to S28 of the DC/DC converter 120 and the switch S31 of the power pulsation absorbing circuit 130 according to the continuous current mode during all phases of one period of the AC voltage v.sub.S.

(58) In addition, the controller 140 may also control the switches S21 to S28 of the DC/DC converter 120 and the first switch S31 of the power pulsation absorbing circuit 130 by combination of the continuous current mode mixed with the discontinuous current mode. For example, the controller 140 may control the switches S21 to S28 of the DC/DC converter 120 and the switch S31 of the power pulsation absorbing circuit 130 according to the continuous current mode during a first phase T.sub.CCM of one period of the AC voltage v.sub.S, wherein the controller 140 may control the switches S21 to S28 of the DC/DC converter 120 and the switch S31 of the power pulsation absorbing circuit 130 according to the discontinuous current mode during another phase of this one period of the AC voltage v.sub.S (second phase T.sub.DCM) which is different from the first phase TCCM.

(59) In this case, the first frequency value f.sub.1 is selected to be smaller than an upper limit value fc for an operable frequency value of the switching frequency f.sub.SW. Preferably, the controller 140 may further set the first phase T.sub.CCM such that a maximum value of the switching frequency f.sub.SW is equal to or smaller than a second frequency value f.sub.2 which is greater than the first frequency value f.sub.1, as shown in FIG. 7. The second frequency value f.sub.2 is equal to or smaller than the upper limit value fc for the operable frequency value of the switching frequency f.sub.SW, wherein the second frequency value f.sub.2 is selected appropriately:

(60) The switching frequency f.sub.SW for the second phase T.sub.DCM may have the first frequency value f.sub.1 as shown in FIG. 7, or may have the second frequency value f.sub.2 as shown in FIG. 8. In FIG. 8, the maximum value of the switching frequency f.sub.SW is the second frequency value f.sub.2. When the switching frequency f.sub.SW for the second phase T.sub.DCM is the second frequency value f.sub.2, smoother operation can be achieved as compared to operation with the switching frequency f.sub.SW for the second phase T.sub.DCM which is equal to the first frequency value f.sub.1. However, the discontinuous current mode includes hard switching operation. Such hard switching operation causes larger loss as the switching frequency f.sub.SW is higher. For this reason, better efficiency may be obtained with the switching frequency f.sub.SW for the second phase T.sub.DCM which is the first frequency value f.sub.1, as compared to operation with the switching frequency f.sub.SW for the second phase T.sub.DCM which is equal to second frequency value f.sub.2.

(61) <Control of the Switches for Switching from Mode 3 to Mode 4>

(62) The DC/DC converter 120 is a DAB converter and includes full bridge circuits on both of the primary and secondary sides. When switches in a circuit with a full bridge circuit are switched from an off-state to an on-state, a dead time is provided in which all switches of a leg are switched off which includes a switch to be switched, in order to prevent all switches of the same leg from being switched on and thus prevent the circuit from being short-circuited.

(63) In the discontinuous current mode (waveform as shown in FIG. 4)/continuous current mode (waveform as shown in FIG. 5), dead times are provided for switching from mode 1 to mode 2, for switching from mode 3 to mode 4, for switching from mode 4 to mode 6, and for switching from mode 7 to mode 1. It is to be noted that in the discontinuous current mode (waveform as shown in FIG. 4), it is not necessary to provide a dead time for switching from mode 5 to mode 1 and for switching from mode 5 to mode 4, since all switches S21 to S28 of the DC/DC converter 120 are switched off in the mode 5 of the discontinuous current mode (waveform as shown in FIG. 4).

(64) In the discontinuous current mode (waveform as shown in FIG. 4), the first switch S31 of the power pulsation absorbing circuit 130 is switched from the off-state to the on-state when switching from mode 3 to mode 4, when switching from mode 5 to mode 4, and when switching from mode 6 to mode 7. In the continuous current mode (waveform as shown in FIG. 5), the first switch S31 of the power pulsation absorbing circuit 130 is switched from the off-state to the on-state when switching from mode 3 to mode 4 and when switching from mode 6 to mode 7. Therefore, in the discontinuous current mode (waveform as shown in FIG. 4) and the continuous current mode (waveform as shown in FIG. 5), the time of the dead time is overlapped with the time of switching the first switch S31 of the power pulsation absorbing circuit 130 from the off-state to the on-state only when switching from mode 3 to mode 4.

(65) FIG. 9 shows an example of changes of gate-source voltages v.sub.gs21, v.sub.gs22 and v.sub.gs31 as well as drain-source voltages v.sub.ds21, v.sub.ds22, and v.sub.ds31 of a first switch S21 and a second switch S2 of the DC/DC converter 120 and a first switch S31 of a power pulsation absorbing circuit 130 during switching from mode 3 to mode 4.

(66) As shown in FIG. 9, for switching from mode 3 to mode 4, the dead time Ta is provided between time t.sub.30 and time t.sub.33, wherein at time t.sub.30, a gate signal applied to the first switch S21 of the DC/DC converter 120 is from an on signal (High-signal) to an off signal (Low-signal) (the gate-source voltage v.sub.gs21 begins to be reduced), wherein at time t.sub.33, a gate signal applied to the second switch S22 of the DC/DC converter 120 is switched from an off signal to an on signal (the gate-source voltage v.sub.gs22 begins to be increased).

(67) Before time t.sub.30, a current as shown in FIG. 10 flows and an output capacitance of the first switch S31 of the power pulsation absorbing circuit 130 is charged with a power with a voltage v.sub.c-v.sub.rec. If a time for switching the gate signal applied to the first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal (the gate-source voltage v.sub.gs31 begins to be increased) is selected to coincide with the time t.sub.30 of switching the gate signal applied to the first switch S21 of the DC/DC converter 120 from the on-state to the off-state, this first switch S31 of the power pulsation absorbing circuit 130 is switched on before the output capacitance of the first switch S31 of the power pulsation absorbing circuit 130 which has been charged is discharged (before the drain-source voltage v.sub.ds31 becomes zero), as shown in FIG. 9. This means that switching of the first switch S31 of the power pulsation absorbing circuit 130 from the off-state to the on-state becomes hard switching. Therefore, if the time for switching the gate signal applied to the first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal is selected to coincide with the time t.sub.30 of switching the gate signal applied to the first switch S21 of the DC/DC converter 120 from the on signal to the off signal, the above-mentioned hard switching may cause switching loss.

(68) In the example shown in FIG. 9, the time t.sub.31 at which the gate-source voltage v.sub.gs31 of the first switch S31 of the power pulsation absorbing circuit 130 exceeds a threshold voltage V.sub.th and the first switch S31 of the power pulsation absorbing circuit 130 is thus switched on is earlier than the time t.sub.32 at which the gate-source voltage v.sub.gs31 of the first switch S31 of the power pulsation absorbing circuit 130 is reduced below the threshold voltage V.sub.th and the first switch S21 of the DC/DC converter 120 is switched off. Therefore, at the time t.sub.31, an electrostatic energy w.sub.31 stored in the output capacitance of the first switch S31 of the power pulsation absorbing circuit 130 will be consumed by an on-resistance of the first switch S31 of the power pulsation absorbing circuit 130.

(69) $w_{31}=\frac{1}{2}{C_{\mathrm{OSS}31}\left(v_C-v_{\mathrm{rec}}\right)}^2$ wherein C.sub.OSS31 indicates a capacitance value of the output capacitance of the first switch S31 of the power pulsation absorbing circuit 130.

(70) Furthermore, a current flows into an output capacitance of the second switch S22 of the DC/DC converter 120 from the buffer capacitor Cbuf between the time t.sub.31 and time t.sub.32 and the output capacitance of the second switch S22 of the DC/DC converter 120 is thus charged, wherein a drain-source voltage v.sub.22ds of the second switch S22 of the DC/DC converter 120 is increased by v.sub.ds22 to reach v.sub.rec+v.sub.ds22. At this time, if the drain-source voltage v.sub.ds22 of the second switch S22 of the DC/DC converter 120 were increased to reach v.sub.C, energy w21 for charging the output capacitance of the second switch S22 of the DC/DC converter 120 would be consumed by resistance components within the circuit, such as the on-resistance of the first switch S21 of the DC/DC converter 120.

(71) 0$w_{21}=\frac{1}{2}{C_{\mathrm{OSS}21}\left(v_C-v_{\mathrm{rec}}\right)}^2$ wherein C.sub.OSS22 indicates a capacitance value of the output capacitance of the second switch S22 of the DC/DC converter 120.

(72) Moreover, the current which charges the output capacitance of the second switch S22 of the DC/DC converter 120 is a sort of short-circuit current. Therefore, between time t.sub.31 and time t.sub.32, the drain-source voltage v.sub.ds21 of the first switch S21 of the DC/DC converter 120 is increased by v.sub.ds21 due to the on-resistance of the first switch S21 of the DC/DC converter 120. Therefore, conduction loss may be caused due to the inductor current i.sub.L and the increased amount v.sub.ds21 by which the drain-source voltage v.sub.ds21 of the first switch S21 of the DC/DC converter 120.

(73) Therefore, in the present embodiment, the controller 140 delays the time of switching the gate signal applied to first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal later than the time t.sub.30 of switching the gate signal applied to the first switch S21 of the DC/DC converter 120 from the on signal to the off signal (that is, time of beginning the dead time T.sub.d), as shown in FIG. 11. This means that a time of expiration of a predetermined time after beginning the dead time Ta is selected as the time of switching the gate signal applied to the first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal. In this case, the predetermined time may preferably have a length equal to or smaller than the dead time Ta, wherein the time of switching the gate signal applied to the first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal may be preferably set after the power stored in the output capacitance of the first switch S31 of the power pulsation absorbing circuit 130 is discharged (i.e., after the drain-source voltage v.sub.ds31 becomes zero), as shown in FIG. 11. This means that during the time until expiration of the predetermined time after beginning the dead time T.sub.d, the controller 140 provides the gate signal for controlling the first switch S31 of the power pulsation absorbing circuit 130 to be off, wherein at the time at which the predetermined time elapses after beginning the dead time T.sub.d, the controller 140 switches the gate signal for controlling the first switch S31 of the power pulsation absorbing circuit 130 from the off-state to the on-state.

(74) In the example as shown in FIG. 11, the time of switching the gate signal applied to the first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal is delayed by the dead time Ta as compared to the time t.sub.30 of switching the gate signal applied to the first switch S21 of the DC/DC converter 120 from the on signal to the off signal, whereby the time of switching the gate signal applied to the first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal is set to coincide with the time t.sub.33 of switching the gate signal applied to the second switch S22 of the DC/DC converter 120 from the off signal to the on signal. Namely, in the example as shown in FIG. 11, the controller 140 provides the gate signal for controlling the first switch S31 of the power pulsation absorbing circuit 130 to be off during the dead time Ta which is provided between mode 3 and mode 4.

(75) Namely, according to the present embodiment, in case where control of switching of the DC/DC converter 120 by the controller 140 includes a first mode (mode 3 in the above example of control) and a second mode (mode 4 in the above example of control), the controller 140 is configured to provide a dead time between the first mode and the second mode when switching from the first mode to the second mode, and control the first switch S31 of the power pulsation absorbing circuit 130 to be in an off-state during a time until expiration of a predetermined time after start of the dead time, wherein in the first mode, at least one switch of the switches S21 to S28 of the DC/DC converter 120 (the first switch S21 of the DC/DC converter 120 in the above example of control) is switched on, at least one switch of the switches S21 to S28 of the DC/DC converter 120 (the second switch S22 of the DC/DC converter 120 in the above example of control) is switched off, and the first switch S31 of the power pulsation absorbing circuit 130 is switched off, and wherein in the second mode, the switch of the DC/DC converter 120 which is switched off in the first mode (the second switch S22 of the DC/DC converter 120 in the above example of control) is switched on, and the first switch S31 of the power pulsation absorbing circuit 130 is switched on.

(76) If a time for switching the gate signal applied to the first switch S31 of the power pulsation absorbing circuit 130 from the off signal to the on signal is selected to coincide with the time t.sub.33 of switching the gate signal applied to the second switch S22 of the DC/DC converter 120 from the off signal to the on signal, the first switch S31 of the power pulsation absorbing circuit 130 is switched on after the power stored in the output capacitance of the first switch S31 of the power pulsation absorbing circuit 130 is discharged (after the drain-source voltage v.sub.ds31 has become zero), as shown in FIG. 11. According to the present embodiment, switching of the first switch S31 of the power pulsation absorbing circuit 130 thus becomes zero voltage switching (ZVS), i.e., soft switching. Therefore, the present embodiment enables the efficiency to be prevented from being reduced. As a result, the present embodiment enables a compact and efficient charger to be provided which allows pulsation of power to be absorbed.

(77) In the example shown in FIG. 11, the time t.sub.34 at which the gate-source voltage v.sub.gs31 of the first switch S31 of the power pulsation absorbing circuit 130 exceeds a threshold voltage V.sub.th and the first switch S31 of the power pulsation absorbing circuit 130 is thus switched on is later than the time t.sub.32 at which the gate-source voltage v.sub.gs31 of the first switch S31 of the power pulsation absorbing circuit 130 is reduced below the threshold voltage V.sub.th and the first switch S21 of the DC/DC converter 120 is switched off. Thus, the output capacitance of the first switch S31 of the power pulsation absorbing circuit 130 with a voltage of v.sub.C-v.sub.rec which has been charged is discharged as shown in FIG. 11 by a current flow during a time from time t.sub.32 to time t.sub.34 as shown in FIG. 12.

(78) Although the present invention has been described above with reference to voltage decrease operation by way of example, the charger 100 according to the present embodiment may perform voltage increase operation (S. Komeda, S. Takuma and Y. Ohnuma, Boost Operation of a Dual-Active-Bridge AC-DC Converter with an Active Energy Buffer, 2022 IEEE Energy Conversion Congress and Exposition (ECCE), Detroit, MI, USA, 2022, pp. 1-6, doi: 10.1109/ECCE50734.2022.9948064). The present invention as described above may be applied to the voltage increase operation.

(79) The present invention has been described above by means of the preferable embodiment thereof. Although the invention has been described herein by presenting a specific example, various modifications and changes may be made to such an example without departing from the spirit and scope of the invention as set forth in the claims.

REFERENCE SIGNS LIST

(80) 100 Charger 110 Rectifier 120 DC/DC converter S21-S28 Switches of the DC/DC converter 130 Power pulsation absorbing circuit D31 First diode D32 Second diode D33 Third diode Lb Inductor Cbuf Buffer capacitor S31 First switch S32 Second switch 200 AC power supply 300 Battery