INTEGRATED CIRCUITS FOR LARGE-SCALE TRANSISTOR TENSOR OPERATIONS

Abstract

An integrated circuit includes a plurality of current-mode computation (CMC) branches, each including a plurality of CMC cells and a branch summation line. An individual CMC cell includes at least one computation transistor that produces a CMC output current that is a function of a channel current of the computation transistor. A branch summation line receives CMC cell output currents produced by a plurality of CMC cells, and produces a branch output current that is a current-mode summation of all received CMC cell output currents. A layer-one current summation circuit receives the branch output current produced by at least one branch summation line, and produces a layer-one current summation circuit output current that is a function of the received branch output currents. The layer-one current summation circuit may be field-programmable. In operation, the integrated circuit can perform transistor tensor operations by programming one or more layer-one current summation circuits to combine all branch output currents received by those layer-one current summation circuits. Using embodiments of the present invention, millions, billions, trillions or more of the CMC cells can be field-programmed to execute computations in parallel to support transistor tensor operations.

Claims

1. An integrated circuit comprising: a plurality of current-mode computation (CMC) branches, wherein each of the CMC branches comprises: a plurality of CMC cells, wherein each of the CMC cells comprises at least a computation transistor or a computation resistor, and produces a CMC cell output current that is a function of the channel current of the computation transistor or the electrical current flowing through the computation resistor; and a branch summation line comprising an electrical conductor that is electrically coupled to, and receives the CMC cell output currents produced by, a plurality of the CMC cells in that individual CMC branch, and that produces a branch output current that is a current-mode summation of the CMC cell output currents electrically coupled thereto; and a plurality of layer-one current summation circuits, wherein each of the layer-one current summation circuits is electrically coupled to, and receives the branch output current produced by, at least one branch summation line, and further comprises a current mirror circuit, and produces a layer-one current summation circuit output current that is a function of the branch output currents received thereto.

2. The integrated circuit of claim 1, further comprising: a plurality of layer-two summation lines, wherein each of the layer-two summation lines comprises an electrical conductor that is electrically coupled to, and receives the layer-one current summation circuit output currents produced by, a plurality of layer-one current summation circuits, and that produces a layer-two summation line output current that is a current-mode summation of the received layer-one current summation circuit output currents; and a plurality of layer-two current summation circuits, wherein each of the layer-two current summation circuits is electrically coupled to, and receives the layer-two summation line output current produced by, at least one layer-two summation line, and produces a layer-two current summation circuit output current that is a function of the received layer-two summation line output currents.

3. The integrated circuit of claim 2, further comprising: a plurality of layer-three summation lines, wherein each of the layer-three summation lines comprises an electrical conductor that is electrically coupled to, and receives the layer-two current summation circuit output currents produced by, a plurality of layer-two current summation circuits, and that produces a layer-three summation line output current that is a current-mode summation of the received layer-two current summation circuit output currents; and a plurality of layer-three current summation circuits, wherein each of the layer-three current summation circuit is electrically coupled to, and receives the layer-three summation line output current produced by, at least one layer-three summation line, and produces a layer-three current summation circuit output current that is a function of the received layer-three summation line output currents.

4. The integrated circuit of claim 1, wherein at least one of the CMC cells comprise an inter-layer dielectric (ILD) embedded component, wherein the ILD embedded component is an electrical component that is embedded in the inter-layer dielectric (ILD) layers of the integrated circuit.

5. The integrated circuit of claim 4, wherein at least one of the ILD embedded components in the CMC cells comprises a resistor.

6. The integrated circuit of claim 4, wherein at least one of the ILD embedded components in the CMC cells comprises a variable resistor with field programmable resistance value.

7. The integrated circuit of claim 4, wherein at least one of the ILD embedded components in the CMC cells comprises a transistor.

8. The integrated circuit of claim 1, wherein at least one of the CMC cells comprises a hybrid-analog-digital (HAD) CMC cell, wherein a HAD CMC cell is a CMC cell that is designed to support computations between a digital input and an analog input.

9. The integrated circuit of claim 8, wherein at least one of the HAD CMC cells comprises memory devices that can store binary numbers.

10. The integrated circuit of claim 9, wherein at least one of the HAD CMC cells comprises DRAM memory cells.

11. The integrated circuit of claim 9, wherein at least one of the HAD CMC cells comprises SRAM memory cells.

12. The integrated circuit of claim 9, wherein at least one of the HAD CMC cells comprises floating-gate transistors.

13. The integrated circuit of claim 1, wherein at least one of the layer-one current summation circuits comprises a fixed voltage current sensing (FVCS) circuit, wherein the FVCS circuit is an electrical circuit comprises (1) an FVCS current-mode input terminal that receives a FVCS electrical current as a current input signal to the FVCS circuit, (2) an FVCS feedback circuit that is designed to fix the steady-state voltage of the FVCS current-mode input terminal at a predetermined voltage, and (3) an FVCS output circuit that produces an output signal that is a function of the FVCS electrical input current received at the FVCS current-mode input terminal.

14. The integrated circuit of claim 13, wherein at least one FVCS circuit comprises an upper voltage clipper and/or a lower voltage clipper, wherein an upper voltage clipper is an electrical circuit designed to prevent the voltage of an electrical signal from exceeding a predetermined reference voltage, and a lower voltage clipper is an electrical circuit designed to prevent the voltage of an electrical signal from being lower than a predetermined reference voltage.

15. The integrated circuit of claim 2, wherein at least one of the layer-two current summation circuits comprise FVCS circuits.

16. The integrated circuit of claim 15, wherein at least one of the FVCS circuit comprises an upper voltage clipper and/or a lower voltage clipper.

17. An integrated circuit comprising a plurality of FVCS circuits, wherein the FVCS current-mode input terminal of at least one of the FVCS circuits is coupled to an electrical signal provided by another integrated circuit on a different semiconductor substrate, wherein the FVCS circuit is an electrical circuit comprises (1) an FVCS current-mode input terminal that receives a FVCS electrical current as a current input signal to the FVCS circuit, (2) an FVCS feedback circuit that is designed to fix the steady-state voltage of the FVCS current-mode input terminal at a predetermined voltage, and (3) an FVCS output circuit that produces an output signal that is a function of the FVCS electrical input current received at the FVCS current-mode input terminal.

18. The integrated circuit of claim 17, wherein at least one of the FVCS circuits comprises an upper voltage clipper and/or a lower voltage clipper, wherein an upper voltage clipper is an electrical circuit designed to prevent the voltage of an electrical signal from exceeding a predetermined reference voltage, and a lower voltage clipper is an electrical circuit designed to prevent the voltage of an electrical signal from being lower than a predetermined reference voltage.

19. The integrated circuit of claim 17, wherein at least one of the FVCS current-mode input terminals of the FVCS circuits are coupled to inter-dice connections.

20. The integrated circuit of claim 17, wherein at least one of the FVCS current-mode input terminals of the FVCS circuits are coupled to another integrated circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0056] FIG. 1(a) is a typical schematic symbol of a metal-oxide-semiconductor (MOS) transistor;

[0057] FIG. 1(b) is a typical schematic symbol of a floating-gate transistor;

[0058] FIGS. 1(c-e) show examples of the current vs voltage (I-V) relationship of a typical MOS transistor;

[0059] FIG. 1(f) is a symbolic diagram illustrating the principle of current-mode summation;

[0060] FIGS. 2(a-d) are simplified symbolic diagrams of examples of prior art floating-gate transistor arrays configured to support neural network computations;

[0061] FIG. 3(a) is a simplified symbolic block diagram of one embodiment of a layer-two block of the present invention;

[0062] FIG. 3(b) is a simplified symbolic block diagram of one embodiment of a layer-one block in FIG. 3(a) that uses current-mode computation memory cells;

[0063] FIG. 3(c) is a simplified schematic diagram of one embodiment of a layer-one input circuit (VI1) in FIG. 3(b);

[0064] FIG. 3(d) is a simplified schematic diagram of one embodiment of a layer-one current summation circuit (IS1) in FIG. 3(b);

[0065] FIG. 3(e) is a simplified schematic diagram of one embodiment of a layer-two current summation circuit (IS2);

[0066] FIG. 3(f) is a simplified schematic diagram of one embodiment of an interface output circuit (VOUT) in FIG. 3(e);

[0067] FIG. 3(g) is a simplified schematic diagram of one embodiment of a layer-one gate voltage input circuit (VI1g) in FIG. 3(b);

[0068] FIG. 3(h) is a simplified symbolic block diagram of one embodiment of a layer-one block in FIG. 3(a);

[0069] FIGS. 3(i-s) are simplified schematic diagram of embodiments of current mode computation cells;

[0070] FIG. 3(t) is a simplified schematic diagram of one embodiment of a layer-one current summation circuit (1040) with a voltage clamping circuit;

[0071] FIGS. 3(u-w) are simplified schematic diagram of embodiments of voltage clamping circuits that can be used for the layer-one current summation circuit in FIG. 3(s);

[0072] FIG. 3(x) is a simplified schematic diagram of one embodiment of a layer-two current summation circuit (1060) with a voltage clamping circuit;

[0073] FIG. 4(a) is a simplified symbolic block diagram of one embodiment of a layer-three block of the present invention;

[0074] FIG. 4(b) a simplified schematic diagram of one embodiment of a layer-three current summation circuit (IS3);

[0075] FIG. 4(c) a simplified schematic diagram of one embodiment of a layer-one current summation circuit (IS1) that can be used when the layer-one array is configured at saturation mode;

[0076] FIG. 5(a) is a simplified symbolic block diagram of one embodiment of a multiple-layer current summation configuration of the present invention;

[0077] FIG. 5(b) is a simplified symbolic block diagram of one embodiment of a multiple-layer input configuration of the present invention;

[0078] FIG. 5(c) is a simplified symbolic block diagram of one embodiment of a system configuration of the present invention;

[0079] FIGS. 5(d-e) show simplified embodiments of inter-dice connections;

[0080] FIG. 6(a) is a simplified schematic diagram for a two-transistor CMC cell that can have positive or negative values;

[0081] FIG. 6(b) is a simplified schematic diagram for a current subtraction circuit that allows synapses to have positive or negative values;

[0082] FIG. 6(c) is a simplified schematic diagram for a dual polarity current mirror circuit;

[0083] FIG. 6(d) is a simplified schematic diagram for a four-transistor synapse cell that can have positive or negative values in both inputs and outputs;

[0084] FIG. 6(e) is a simplified flow chart for implementing double-precision parameters; and

[0085] FIG. 7(a-c) are simplified cross-section diagrams for embodiments of CMC cells comprise computation resistors.

DETAILED DESCRIPTION

[0086] As discussed in previous sections, prior art floating-gate transistor arrays cannot support large-scale transistor matrix-vector operations due to the non-ideal effects listed in Table 1. These non-ideal effects increase rapidly with the size of the transistor arrays. Embodiments of the present invention overcome these problems by distribute computation cells into a large number of small units and combine the computations executed in different units to execute full large-scale computations. This architecture also reduces power consumption, solves the current overload problem, and provides configurability.

[0087] FIG. 3(a) is a simplified symbolic block diagram for an embodiment of a layer-two block (B.sup.(2)) of an embodiment of the present invention. This layer-two block (B.sup.(2)) comprises P columns and U rows of layer-one blocks (B.sub.m,n), as shown in FIG. 3(a), where P and U are positive integers, n is an integer greater than or equal to 1 and less than or equal to U, and m is an integer greater than or equal to 1 and less than or equal to P.

[0088] FIG. 3(b) is a simplified schematic diagram for one embodiment of a layer-one block in FIG. 3(a). This layer-one block (B.sub.m,n) comprises a two-dimensional array of N columns and M rows of CMC cells that are configured to support transistor matrix-vector operations, where N and M are positive integers, i is an integer greater than or equal to 1 and less than or equal to N, and j is an integer greater than or equal to 1 and less than or equal to M. In this embodiment, each CMC cell comprises one programmable-threshold voltage transistor (M.sub.i,j), which is a floating-gate transistor that is used as a computation transistor and as a memory device. The drain terminals of a subset of the floating-gate transistors (M.sub.1,j, M.sub.2,j, . . . , M.sub.i1,j, M.sub.i,j, . . . M.sub.N1,j, M.sub.N,j) are connected by a conductor line (Vd.sub.j) to a drain voltage input circuit (VI1)(312), as shown in FIG. 3(b), where j is an integer greater than or equal to 1 and less than or equal to M. A conductor line (e.g. Vd.sub.1, Vd.sub.2, . . . , Vd.sub.j, . . . , Vd.sub.M) that controls the drain voltages of a subset of the computation transistors in the layer-one block (B.sub.m,n) will be called a drain voltage input line in the following discussions. The number (N) of transistors connected to each drain voltage input line is designed to be low enough such that the aforementioned parasitic parameter induced problems are negligible, allowing the drain voltage input line to be considered as an equal-potential electrical conductor line. FIG. 3(c) shows a simplified schematic diagram for an exemplary sample-and-hold (S&H) circuit that can serve the function of the drain voltage input circuit (VI1) that drives a drain voltage input line. In sample mode, when the field-programmable control signal Smp is activated, transistor Me4 is turned on such that the voltage (Vhi) on the storage capacitor (Ch) is substantially equal to the input voltage (Vdp), as shown in FIG. 3(c). A unit gain amplifier (321) senses and drives the voltage on its input node (Vhi) to its output (Vh) at a voltage equal to Vdp during sampling mode. During hold mode, when the field-programmable control signal Smp is deactivated, transistor Me4 is turned off such that the voltage on the storage capacitor (Ch) is held at the previously sampled value even when the input voltage Vdp changes. When the field-programmable enable signal (ENI) is activated, and the field-programmable reset signal (Rst) is deactivated, transistor Me5 is turned on, transistor Mrst is turned off, and the output voltage on the drain voltage input line (Vdj) is driven by the unit gain amplifier (321) to be equal to its output voltage at Vh. When the field-programmable enable signal (ENI) is deactivated, and the field-programmable reset signal (Rst) is activated, transistor Me5 is turned off, transistor Mrst is turned on, and the output voltage on the drain voltage input line (Vdj) is reset to voltage Vs. The number of transistors (N) connected to the drain voltage input line (Vdj) is designed to be low enough such that the R*C delay time caused by the parasitic parameters of the input conductor line (Vdj) is no more than a fraction of the intrinsic delay time of the input circuit (VI1).

[0089] The gate terminals of the same subset of the floating-gate transistors (M.sub.1,j, M.sub.2,j, . . . , M.sub.i1,j, M.sub.i,j, . . . M.sub.N1,j, M.sub.N,j) that share the same drain voltage input line (Vd.sub.j) in the layer-one block (B.sub.m,n) are connected by another conductor line (Vg.sub.j) to another gate voltage input circuit (VI1g) (313), as shown in FIG. 3(g). A conductor line (e.g Vg.sub.1, Vg.sub.2, . . . , Vg.sub.j, . . . , Vg.sub.M) that controls the gate voltages of a subset of the computation transistors in the layer-one block (B.sub.m,n) will be called a gate voltage input line in the following discussions. In this embodiment, the sample-and-hold (S&H) circuit (VI1g) in FIG. 3(g) is nearly identical to the S&H circuit in FIG. 3(c), except that one terminal of its storage capacitor (Ch) is connected to a field-programmable reference voltage (Vsg) instead of a fixed voltage (Vs), as shown in the design in FIG. 3(g). When Vsg=Vs, VI1g is identical to VI1 and serves the same functions of a voltage sample-and-hold circuit based on the same operation principles exhibited by the circuit in FIG. 3(c). In hold mode, a change in Vsg causes a change in output voltage (Vg.sub.i), providing a convenient way to execute training algorithms of an embodiment of the present invention. The number of transistors (N) connected to the gate voltage input line (Vg.sub.j) is designed to be low enough such that the R*C delay time caused by the parasitic parameters of the Vg input conductor line (Vg.sub.j) is no greater than a fraction of the intrinsic delay time of the gate voltage input circuit (VI1g).

[0090] The source terminals of a subset of the floating-gate transistors (M.sub.i,1, M.sub.i,2, . . . , M.sub.i,j1, M.sub.i,j, . . . M.sub.i,M1, M.sub.i,M) in the layer-one block (B.sub.m,n) are connected by a branch summation line (315) to a layer-one current summation circuit (IS1) (311), as shown in FIG. 3(b), where j is an integer greater than or equal to 1 and less than or equal to M. During computation, feedback circuits in the layer-one current summation circuits (IS1) fix the voltages on the branch summation lines to a predefined voltage (Vs). Under this configuration, the channel current (Ids.sub.i,j) of the transistor (M.sub.i,j) at the i'th column and j'th row is a function of the threshold voltage (V.sub.Ti,j), drain voltage (Vd.sub.j), source voltage (Vs), and gate voltage (Vg.sub.j) of the transistor (M.sub.i,j) is Ids.sub.i,j((Vd.sub.jVs), (Vg.sub.jVsV.sub.Ti,j)). The number of transistors (M) connected to each branch summation line (Is.sub.i) is designed to be low enough so that the total parasitic leakage currents on the conductor line is negligible relative to the transistor channel currents. Under these conditions, the branch output current (Is.sub.i) carried by the branch summation line (315) to the layer-one current summation circuit (311) is equal to the current-mode summation of the channel currents (Ids.sub.i,j) of all the transistors ((M.sub.i,1, M.sub.i,2, . . . , M.sub.i,j1, M.sub.i,j, . . . M.sub.i,M1, M.sub.i,M)) connected to the branch summation line:

[00017]${\mathrm{Is}}_i={.Math.}_j^{}{\mathrm{Ids}}_{i,j}\left(\left({\mathrm{Vd}}_j-\mathrm{Vs}\right),\left({\mathrm{Vg}}_j-\mathrm{Vs}-V_{\mathrm{Ti},j}\right)\right).$

In this embodiment, the transistor M.sub.i,j serves the functions of a current mode computation (CMC) cell that executes a scalar function of two scalar inputs, (Vd.sub.jVs) and (Vg.sub.jVsV.sub.Ti,j), to generate a CMC cell output current (Ids.sub.i,j) that is a function of the channel current (Ids.sub.i,j) of the computation transistor (M.sub.i,j). A plurality of CMC cells (M.sub.i,1, M.sub.i,2, . . . , M.sub.i,j1, M.sub.i,j, . . . M.sub.i,M1, M.sub.i,M) are coupled to a branch summation line (315) to form a current mode computation (CMC) branch (CB.sub.i). This CMC branch (CB.sub.i) executes transistor vector-vector operation on two input vectors (Vd.sub.jVs).sup.M and (Vg.sub.jVsV.sub.Ti,j).sup.M, and produces a branch out current (Is.sub.i). The branch summation line (315) is an electrical conductor that is electrically coupled to, and receives the CMC cell output currents (Ids.sub.i,1, Ids.sub.i,2, . . . , Ids.sub.i,j1, Ids.sub.i,j, . . . , Ids.sub.i,M1, Ids.sub.i,M) produced by, a plurality of CMC cells (M.sub.i,1, M.sub.i,2, . . . , M.sub.i,j1, M.sub.i,j, . . . M.sub.i,M1, M.sub.i,M) in the CMC branch (CB.sub.i), and produces a branch output current (Is.sub.i) that is a current-mode summation of all received CMC cell output currents. Under ideal conditions, the current-mode summation of a plurality of electrical currents (Ids.sub.i,1, Ids.sub.i,2, . . . , Ids.sub.i,j1, Ids.sub.i,j, . . . , Ids.sub.i,M1, Ids.sub.i,M) equals to the summation of those currents (.sub.jIds.sub.i,j), while in reality none ideal effects such as parasitic leakage currents or timing delay may introduce inaccuracies. The layer-one current summation circuit (IS1) is electrically coupled to, and receives the branch output current (Is.sub.i) produced by, at least one branch summation line (315), and produces a layer-one current summation circuit output current (Io.sub.i) that is a function of the received branch output currents (Is.sub.i). Combining the functions of a plurality of the CMC branches (CB.sub.1, CB.sub.2, . . . , CB.sub.i, . . . , CB.sub.N), the layer-one block in FIG. 3(b) executes transistor matrix-vector operations. Combining the functions of large number of layer-one blocks (B.sub.m,n) in a multiple layer architecture, millions, a billion, a trillion or more of the CMC cells can be field-programmable to execute computations in parallel using their computation transistors, together with the branch summation lines that are coupled to those CMC cells, and the layer-one current summation circuits that are coupled to those branch summation lines, to execute large scale multiple-level transistor tensor operations that can have millions, billions, trillions or more scalar computations.

[0091] The layer-one block in FIG. 3(b) has two input lines for each row of transistorsone drain voltage input line and one gate voltage input line. This configuration provides the flexibility to field-program the computation mode of each computation transistor, as listed in the following table (Table 2).

TABLE-US-00002 TABLE 2 gate voltage drain voltage Transistor input line input line computation mode Constant input Multiplier input Constant ReLU input input Rectifier input Vs Saturation Vs Don't care Turned off Source also at Vs Vs Turned off
When the voltage on the gate voltage input line is set to a constant voltage and the drain voltage input line is used to provide input signals, the computation transistors on the row operate in multiplier mode. When the voltage on the drain voltage input line is fixed and the gate voltage input line is used to provide input signals, the computation transistors on the row operate in ReLU mode. When both the drain voltage input line and the gate voltage input line are set to provide the same input voltage, the computation transistors on the row operate in rectifier mode. When the gate voltage input line is set to source voltage Vs, the computation transistors on the row are all turned off. When the drain voltage input line is set to source voltage Vs and the branch summation line is also set to voltage Vs, the computation transistors on the row are all turned off. When the drain voltage input line is set to source voltage Vs, and the branch summation lines are coupled to the layer-one saturation mode current summation circuit (IS1) in FIG. 4(c), the floating-gate transistors on the row operate in saturation mode. In other words, this configuration provides the flexibility to program a selection of the scalar functions for computation transistors.

[0092] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. In the above embodiments, while each current-mode computation (CMC) cell comprises one floating-gate transistor, the CMC cell can also use other types of programmable-threshold voltage transistors. For example, instead of trapping electrical charges in an isolated conductor, it is also possible to trap electrical charges in the insulator layer that forms the gate insulator, creating a programmable-threshold voltage transistor. Each CMC cell can have multiple transistors. CMC cells can be arranged in different geometries instead of simple two-dimensional arrays. The layer-one blocks can be arranged in different geometries instead of two-dimensional arrays. The inputs and outputs can be configured in various directions. Instead of having two sets of input lines, the layer-one blocks can have one set of input lines or more than two sets of input lines. The layer-one block in the above embodiment does not have multiplexers at its inputs and outputs, but multiplexers can be used for embodiments of the present invention to improve array efficiency. A branch summation line does not have to be a line, it can be of any shape; it also can be a combination of electrical conductors of different shapes or materials. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0093] FIG. 3(d) is a simplified schematic diagram for one embodiment of the layer-one current summation circuit (IS1) in FIG. 3(b). A high gain amplifier (331) fixes the voltage on the branch summation line (315) to a predefined reference voltage V.sub.s and provides an output (Vgm) that controls the gate voltages of three matched transistors (Mm1, Mm2, Mm3) whose source terminals are connected together to the same voltage at Vss. The voltage Vs also can be field-programmable. When the field-programmable input enable signal (Ens) is activated, select transistor Me1 is turned on and the amplifier (331) adjusts the current flowing through Mm1 to be equal to the branch output current (Is.sub.i) by adjusting the gate voltage (Vgm) of matched transistors. Matched transistor Mm2 has the same gate voltage, source voltage, and properties as transistor Mm1. Therefore, when transistor Me2 is turned on by field-programmable enable signal EN2, the channel current flowing through Mm2 is designed to be equal to (Wm2/Wm1)*Is.sub.i, where Wm2 is the effective channel width of transistor Mm2 and Wm1 is the effective channel width of transistor Mm1. Similarly, when transistor Me3 is turned on by field-programmable enable signal EN3, the channel current flowing through Mm3 is designed to be equal to (Wm3/Wm1)*Is.sub.i, where Wm3 is the effective channel width of transistor Mm3. Matched transistors (Mm1, Mm2, Mm3) are arranged in a configuration known as current mirrors in the art of circuit design. The layer-one current summation circuit output current (Io.sub.i) is therefore proportional to the branch output current (Is.sub.i):

[00018]${\mathrm{Io}}_i=K_i*{\ln }_i$

K.sub.i is a scale factor depending on the design of the circuit IS1 and the status of the field-programmable enable signals (Ens, EN2, EN3). For example, when EN2 is activated and EN3 is deactivated, K.sub.i=(Wm2/Wm1); when EN2 is deactivated and EN3 is activated, K.sub.i=(Wm3/Wm1). Having multiple matched transistors (Mm2, Mm3) allows the scale factor K.sub.i to be field-programmable, and we can use more matched transistors to increase the range of selection for the scale factor. The layer-one current summation circuit output current (Io.sub.i) is coupled to the layer-two summation line. If all the field-programmable enable signals (EN2, EN3) are deactivated, this output is isolated from the layer-two summation line.

[0094] A fixed voltage current sensing (FVCS) circuit is defined as an electrical circuit comprises (1) an FVCS current-mode input terminal that receives a FVCS electrical current as a current input signal to the FVCS circuit, (2) an FVCS feedback circuit that is designed to fix the steady-state voltage of the FVCS current-mode input terminal at a predetermined voltage, and (3) an FVCS output circuit that produces an output signal that is a function of the FVCS electrical input current received at the FVCS current-mode input terminal. The electrical circuit (IS1) illustrated in FIG. 3(d) comprises a current-mode input terminal (315) that receives an electrical current (Is.sub.i) as an input signal to the electrical circuit (IS1). The high gain amplifier (311) and transistor Mm1 form a feedback circuit that can fix the steady-state voltage of the current-mode input terminal (315) at a predetermined voltage (Vs). The current mirrors formed by matched transistors (Mm1, Mm2, Mm3) produce an output signal (Io.sub.i) that is a function of the input current (Is.sub.i) at the current-mode input terminal (315). Therefore, the electrical circuit illustrated in FIG. 3(d) is an embodiment of FVCS circuit. FIG. 3(t) illustrates an electrical circuit (1050) that is almost the same as the circuit in FIG. 3(d) except it has a voltage clipper (1051). There are two types of voltage clipper circuits: an upper voltage clipper that is defined as an electrical circuit designed to prevent the voltage of an electrical signal from exceeding a predetermined reference voltage, and a lower voltage clipper that is defined as an electrical circuit designed to prevent the voltage of an electrical signal from being lower than a predetermined reference voltage. The voltage clipper (1051) in FIG. 3(t) is used to fix the range of transient voltage (SVs) on the input terminal (315) of the FVCS circuit (1050), which is helpful to improve the speed and stability of the FVCS circuit.

[0095] FIG. 3(u-w) are simplified schematic diagram for embodiments of voltage clippers that can be used as the voltage clipper (1051) in FIG. 3(t). FIG. 3(u) shows a voltage clipper that comprise an upper voltage clipper formed by a diode (1052) and a reference voltage (VCPb). This voltage clipper prevents the voltage of SVs from exceeding the voltage level of VCPb plus the forward bias voltage of the diode (1052). FIG. 3(v) shows a voltage clipper that comprise an upper voltage clipper formed by a Zener diode (1054) and a reference voltage (VCPb). This voltage clipper prevents the voltage of SVs from exceeding the voltage level of VCPb plus the breakdown voltage of the Zener diode (1054). FIG. 3(w) shows a voltage clipper that comprise an upper voltage clipper formed by a transistor (1056) configured as a rectifier and a reference voltage (VCPb). This voltage clipper prevents the voltage of SVs from exceeding the voltage level of VCPb plus the threshold voltage of the transistor connected in rectifier mode (1056).

[0096] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. For instance, lower voltage clippers, instead of upper volage clippers (1052, 1054, 1056), or both types of voltage clippers can be used. In addition, there are other ways to implement voltage clippers or current mirrors. P-channel transistors, instead of n-channel transistors, can be used to form current mirror circuits. In the above embodiments, FVCS circuits (IS1, 1050) are used as the layer-one current summation circuits while FVCS circuits can be used for layer-two, layer-three, or other layers. The FVCS current-mode input terminals of the FVCS circuits may be coupled to an electrical signal provided by another integrated circuit on a different semiconductor substrate. FVCS circuits are very useful to support signal transfers between different IC chips or between different IC dice, achieving ultra-high bandwidth current mode signal transfer at low power. For example, FVCS circuits can support the inter-dice signal transfers using the inter-dice connections (537, 547, 548) illustrated in FIG. 5(d), or the signals transfers between different packaged integrated circuits such as those (525, 526, 527) illustrated in FIG. 5(c). It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0097] A small enough layer-one block yields negligible parasitic leakage current on branch summation lines. The CMC cell output currents can be adjusted to be small while meeting the required signal-to-noise ratio. This not only saves operation power, but also mitigates the current overload problem. The layer-one current summation circuit (IS1) is also designed to prevent the current overload problem. Firstly, M is chosen to be low enough such that when all computation memory cells along the branch summation line are turned on at their maximum currents, the layer-one block will still not exhibit current overload. In addition, the output range of the amplifier (331) is designed to work, meaning to output a current proportional to the input summation current (Is.sub.i), only when the branch current (Is.sub.i) is less than a pre-calibrated maximum value (Is.sub.max). When (Is.sub.i) is close to Is.sub.max, the amplifier (331) no longer can hold the voltage of the branch summation line at Vs, reducing the gate-to-source voltage of all transistors connected to the branch summation line and therefore the branch output current. Meanwhile, the current mirror output current (Io.sub.i) is no longer proportional to the input current so that the maximum value of the output current is also limited, which prevents current overload problem at upper layers. In this way, the amplifier (331) and transistor Mm1 form a feedback circuit that can limit the amplitude of the received branch output current (Is.sub.i). Transistor Mm1 and the maximum output voltage of the high gain amplifier (331) defines Is.sub.max. Adjusting the size of transistor Mm1 can adjust Is.sub.max. It may be desirable to make the size of Mm1 field-programmable. Such design effectively prevents the current overload problem, and provides a way to limit operation power. The computation remains accurate as well because when Is.sub.i is close to Is.sub.max, the output current is limited by the output function.

[0098] When the input functions are operating in saturation mode, the polarity of channel currents is changed and the layer-one saturation mode current summation circuit (IS1) shown in the simplified schematic diagram in FIG. 4(c) can be used. IS1 has the same n-channel current mirrors as those in FIG. 3(d). The difference is that its input stage is a p-channel current mirror formed by two matched transistors (Mp7, Mp8) and two enable transistors (Mpe7, Mpe8) as shown in FIG. 4(c). When field-programmable enable signals Enp7 and ENp8 are both activated, the branch output current (Is.sub.i) is duplicated to the input of the n-channel current mirrors, providing a layer-one saturation mode current summation circuit output current (Io.sub.i) that is compatible with the circuit in FIG. 3(d). At saturation mode, the channel currents of MOS transistors are not sensitive to the value of the drain voltage. IS1 therefore does not need a feedback mechanism to fix the voltage of the branch summation line in this case. Because a current mirror is significantly faster than a high gain amplifier (331), saturation mode can achieve better performance than other modes. The circuit in FIG. 4(c) is also able to prevent the current overload problem because current mirror circuits by nature have upper limitations on the amplitudes of output currents.

[0099] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. For instance, in the above embodiments, the output currents produced by the layer-one current summation circuits (IS1) or layer-one saturation mode current summation circuit (IS1) is proportional to the branch output current (Is.sub.i). For more general cases, loi can be other functions of Is.sub.i instead of a simple proportional relationship. IS1, IS1, VI1, VI1g can be designed in multiple ways. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0100] To avoid the non-ideal parasitic parameter induced problems listed in Table 1, the layer-one block (B.sub.m,n) for embodiments of the present invention typically has a small transistor array (for example: 128 rows by 64 columns) that when combined with other blocks can support large-scale transistor tensor operations. FIG. 3(a) is a simplified symbolic block diagram showing an embodiment of a layer-two block (B.sup.(2)) for embodiments of the present invention. The layer-two summation lines (301) are coupled to a plurality of layer-one blocks (B.sub.m,n) as shown in FIG. 3(a). An individual layer-two summation line comprises an electrical conductor that is electrically coupled to, and receives the layer-one current summation circuit output currents produced by, a plurality of layer-one current summation circuits (IS1 or IS1) in the layer-one blocks (B.sub.m,n), and that produces a layer-two summation line output current that is a current-mode summation of all received layer-one current summation circuit output currents. FIG. 3(e) is a simplified schematic diagram for one embodiment of the layer-two current summation circuit (IS2) in FIG. 3(a). In this embodiment, four matched transistors (Mp1, Mp2, Mp3, Mp4) and four enable transistors (Mpe1, Mpe2, Mpe3, Mpe4) are configured as current mirrors, as shown in FIG. 3(e). P-channel transistors are used in IS2 because, in this embodiment, the polarity of the input current (Is.sup.(2)) is opposite to that of the layer-one current summation circuits (IS1). When the field-programmable enable signals Enp1 and Enp2 are activated and Enp3 is deactivated, the layer-two summation circuit output current Io.sup.(2)=(Wp2/Wp1)Is.sup.(2), where Wp2 is the effective channel width of transistor Mp2 and Wp1 is the effective channel width of transistor Mp1. When the field-programmable enable signals Enp1 and Enp3 are activated and Enp2 is deactivated, the layer-two summation circuit output current Io.sup.(2)=(Wp3/Wp1)Is.sup.(2), where Wp3 is the effective channel width of transistor Mp3. When the field-programmable enable signals Enp1 and Enp4 are activated, a layer-two output circuit input current Iso=(Wp4/Wp1)Is.sup.(2) is produced as the input current to the interface output circuit (Vout) illustrated in FIG. 3(f), where Wp4 is the effective channel width of transistor Mp4. IS2 is also able to prevent the current overload problem because current mirror circuits by nature have an upper limit on the output currents. An individual layer-two current summation circuit (IS2) is electrically coupled to, and receives the layer-two summation line output current (Is.sup.(2)) produced by, at least one layer-two summation line (301), and produces a layer-two current summation circuit output current (Io.sup.(2)) that is a function of all received layer-two summation line output currents.

[0101] FIG. 3(f) is a simplified schematic diagram for one embodiment of the interface output circuit (Vout) in FIG. 3(e). The layer-two output circuit input current (Iso) in FIG. 3(e) passes through a variable impedance formed by a diode (D1) and 4 field-programmable variable resistors (VR1, VR2, VR3, VR4) to generate a voltage (Vi4) connected to the input of a programmable gain amplifier (351) which drives a layer-two output voltage (Avo) that is proportional to the voltage (Vi4) at the input of the amplifier (351). The gain of this programmable gain amplifier (351) is designed to be adjustable by a reference transistor (fgTa), as shown in FIG. 3(f). This reference transistor (fgTa) matches the computation transistors used in CMC cells such that it has matched temperature dependence in channel current. Using this reference transistor (fgTa) as a thermometer to adjust the gain of the amplifier (351) can mitigate temperature induced variations. The field-programmable gate voltage (Vga) allows field-programmable gain control of the amplifier (351). Avo can be used as input voltage for the next level of neural network computation; it is also connected to an analog-to-digital converter (ADC) to provide digital outputs (DVo) to digital interfaces. The field-programmable variable resistors (VR1, VR2, VR3, VR4) can typically be implemented by transistors with field-programmable gate voltages. These variable resistors (VR1, VR2, VR3, VR4) allow the interface output circuit (Vout) to support different output functions. For example, when VR2 and VR3 are set to zero, Vi4 is a sigmoid function with minimum level controlled by the field-programmable voltage Vref; when VR1 and VR4 are set to zero, the output is a ReLU function; when VR3 and VR4 are set to zero, the output is a linear function. This design allows field-programmable individual selection of output functions for transistor tensor operations.

[0102] The layer-two summation lines (301) and layer-two current summation circuits (SI2) provide effective ways to expand the number of inputs for transistor tensor operations. For example, if a layer-one block can support 128 inputs, and a layer-two summation line (301) is coupled to 64 layer-one current summation circuits (IS1), then the layer-two block with two-layer current summation architecture can support transistor tensor operations with up to 8192 inputs. If less inputs are needed, unused rows or layer-one blocks are disabled. If more inputs are needed, then more columns of layer-one blocks or layer-three summation lines can be used. Biases can be implemented as one layer-one row with constant inputs.

[0103] Layer-two summation lines (301) also can suffer parasitic parameter induced non-ideal effects similar to those in Table 1. It is important to choose a proper number (U) of layer-one current summation circuits (IS1) coupled to each layer-two summation line to avoid such parasitic induced errors. Because current mirrors are not sensitive to the voltage on input lines, parasitic voltage differences are less important. The width and the length of the layer-two summation line should be designed properly to avoid significant R*C delay. The current amplification factor in the layer-one current summation circuit (IS1) should be chosen properly to have a good signal-to-noise ratio and optimum power consumption.

[0104] The layer-two block in FIG. 3(a) also has layer-two input circuits (VI2) that drive layer-two input lines (303). These layer-two input circuits (VI2) also can be implemented by S&H circuits similar to that (VI1) of FIG. 3(c). The layer-two input lines (303) are coupled to the inputs of layer-one input circuits (VI1, VI1g) in layer-one blocks (B.sub.m,n). Therefore, the voltages on the layer-one input lines (Vd.sub.j, Vg.sub.j) in each layer-one block can be controlled by layer-two input circuits (VI2). This multiple-layer input configuration supports field-programmable input configurations that approach the flexibility of prior art software configurations. Such flexible multiple-layer input configurations can be used to duplicate the same sets of inputs into different layer-one blocks that have different branch summation lines in order to expand the number of outputs. For example, if a layer-one block can support 64 outputs, and each layer-two input line (303) is coupled to 32 sets of layer-one input circuits (VI1, VI1g), then the layer-two block with two-layer input architecture can support transistor tensor operations with up to 2048 outputs. If less outputs are needed, unused columns or layer-one blocks are disabled. If more outputs are needed, more columns of layer-one blocks or layer-three input lines can be used to handle more outputs.

[0105] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. For example, the layer-two, layer-three, and other upper-layer summation lines and input lines can be in different shapes (do not need to be a line) or travel along different directions. These summation lines can be a combination of different layers of metals, vias, contacts, and other components. Blocks in different layers do not need to have the same dimensions or structures, and they can be arranged in different geometries instead of two-dimensional arrays. IS2, IS3, and VOUT can be designed in multiple ways. The input lines of the layer-one block in FIG. 3(b) are always horizontal to the branch summation lines; such configuration can support transistor matrix-vector (TMV) operations, while layer-one blocks for embodiments of the present invention can be configured in other ways to support other tensor operations such as TVV or TMM operations. In the above embodiments, current mirror circuits (IS2) are used as the layer-two current summation circuits, while we also can use FVCSC circuits (1060), such as the embodiment illustrated by the simplified schematic diagram in FIG. 3(x), as the layer-two current summation circuits. The embodiment in FIG. 3(x) is nearly the same as IS2 in FIG. 3(e) except that a high gain amplifier (1061), is used as a feedback circuit to fix the steady state voltage on the input terminal (SVps) to be equal to a reference voltage (VPs), and to provide the gate voltage (Vgmp) of the current mirrors formed by the matched transistors (Mp1, Mp2, Mp3, Mp4). In addition, a voltage clipper (1062) is also used to prevent overshoots of the voltage on SVps. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0106] FIG. 3(h) shows another layer-one block (370) that comprises a plurality of current-mode computation (CMC) branches (CM.sub.1, CM.sub.2, . . . , CM.sub.i1, CM.sub.i, . . . , CM.sub.N), where i is an integer larger or equal to 1 and less than or equal to N. An individual CMC branch (CM.sub.i) comprises (a) a plurality of CMC cells (C.sub.i,1, C.sub.i,2, . . . , C.sub.i,j1, C.sub.i,j, . . . , C.sub.i,M), where an individual CMC cell comprises at least one computation transistor or a computation resistor, and produces a CMC cell output current that is a function of the channel current of the computation transistor or the electrical current flowing through the computation resistor, such as the exemplary CMC cells illustrated in FIG. 3(i-m); and (b) a branch summation line (371) that comprises an electrical conductor that is electrically couples to, and receives the CMC cell output currents produced by, a plurality of the CMC cells (C.sub.i,1, C.sub.i,2, . . . , C.sub.i,j1, C.sub.i,j, . . . , C.sub.i,M) in the CMC branch (CM.sub.i), and that produces a branch output current (Is.sub.i) that is a current-mode summation of all received CMC cell output currents. The branch summation line (371) is coupled to a layer-one current summation circuit (IS1) that receives the branch output current (Is.sub.i) produced by the branch summation line (371), and produces a layer-one current summation circuit output current (Io.sub.i) that is a function of the received branch output current. In this embodiment, each layer-one current summation circuit (IS1) is coupled to one CMC branch (CM.sub.i), while a layer-one current summation circuit can also be coupled to multiple CMC branches. Multiplexers can sometimes be used between the CMC branches and the layer-one current summation circuits. Field-programmable selection circuits can be used to selectively activate a subset of or all of the layer-one and layer-two current summation circuits in order to combine the computation capabilities of different CMC branches to support parts of or all of a large-scale transistor tensor operation.

[0107] The input connections to the CMC branches (CM.sub.1, CM.sub.2, . . . , CM.sub.i1, CM.sub.i, . . . , CM.sub.N) are not shown in FIG. 3(h) because there are many possible configurations to arrange the input connections; different input configurations can support different types of transistor tensor operations. For example, the layer-one block (B.sub.m,n) shown in FIG. 3(b) is a special case when the input lines (Vd.sub.1, Vd.sub.2, . . . , Vd.sub.j, . . . , Vd.sub.M; Vg.sub.1, Vg.sub.2, . . . , Vg.sub.j, . . . , Vg.sub.M) connected to its CMC branches (CB.sub.1, CB.sub.2, . . . , CB.sub.i1, CB.sub.i, . . . , CB.sub.N1, CB.sub.N) all travel in a horizontal direction and are shared by every CMC branch in the layer-one block; such configuration is suitable to support transistor matrix-vector operations.

[0108] FIG. 3(i) shows the schematic symbol for an embodiment of a CMC cell (991) that can be used for the layer-one block (370) illustrated in FIG. 3(h). In this embodiment, the CMC cell (991) comprises one computation transistor (MM.sub.i,j) that is controlled by the gate-to-source voltage (VG.sub.i,j) and drain-to-source voltage (VD.sub.i,j) and outputs its channel current (I.sub.i,j) as the CMC cell output current. The channel current (I.sub.i,j) is a function of VG.sub.i,j and VD.sub.i,j according to the I-V relationship of the computation transistor (MM.sub.i,j). If the computation transistor is operating in triode region, we have

[00019]$I_{i,j}=K_n*{\mathrm{VD}}_{i,j}*\left({\mathrm{VG}}_{i,j}-V_T\right)$

where V.sub.T is the threshold voltage of the computation transistor (MM.sub.i,j). In this embodiment, The branch output current (Is.sub.i) of CMC branch CM.sub.i is the current mode summation of CMC cell output currents (I.sub.i,1, I.sub.i,2, . . . , I.sub.i,j, . . . , I.sub.i,M) of all the CMC cells (C.sub.i,1, C.sub.i,2, . . . , C.sub.i,j, . . . , C.sub.i,M) coupled to the branch summation line (371) as:

[00020]${\mathrm{Is}}_i={.Math.}_j^M{I}_{i,j}={.Math.}_j^M\left[K_n{\mathrm{VD}}_{i,j}*\left({\mathrm{VG}}_{i,j}-V_T\right)\right],$

where we assume the V.sub.T of all computation transistors are the same because they are matched transistors manufactured by IC technology. The above equation shows that the summation current is proportional to the dot product of two input vectors (VD.sub.i,1, . . . , VD.sub.i,j, . . . , VD.sub.i,M) and ((VG.sub.i,1V.sub.T), . . . , (VG.sub.i,jV.sub.T), . . . , (VG.sub.i,MV.sub.T)). In this embodiment, a CMC branch executes transistor vector-vector operation of two input vectors and produces a branch output current to represent the transistor vector-vector computation results. The computation transistor (MM.sub.i,j) can use body effects as a way to reducer parasitic leakage currents. One convenient approach is to use a native transistor as the computation transistor (MM.sub.i,j). A native transistor is an MOS transistor with a threshold voltage close to zero. Native transistors can be manufactured by proper adjustment of threshold voltage implant dosage, by adjusting the storage charge of a field-programmable-threshold voltage transistor, or by other methods. Using native transistors, we have Is.sub.i=.sub.j.sup.M I.sub.i,j=.sub.j.sup.M[K.sub.nVD.sub.i,j*VG.sub.i,j].

[0109] Each CMC branch (CM.sub.i) in FIG. 3(h) with the CMC cells illustrated in FIG. 3(i) is able to execute the transistor vector-vector operation of two vectors of size M. The input vectors of an CMC branch can be a set of various kinds of parameters. For example, the vector can be parts or all of external input vectors, parts of all of internally vectors generated during deep level transistor tensor operation, a set of data stored in CMC memory cells, parts of or all of Hadamard parameters used for transistor convolution operations, parts of signed data, parts of multiple-precision data, or many other types of parameters. If the size of the input vector is larger than M, we can use layer-two summation lines to combine CMC branches in multiple layer-one blocks to execute dot products of large vectors. The number of layers can be increased to meet larger vector size. If vector components have both positive and negative numbers, the methods described in FIGS. 6(a-d) can be used to support negative components. If the computations require greater accuracy, the methods described in FIG. 6(e) can be used. With field-programmable configurations, CMC branches for embodiments of the present invention are able to support a wide variety of dot product computations. Since all tensor operations are based on vector dot products, CMC branches for embodiments of the present invention are therefore able to support vector-vector, matrix-vector, matrix-matrix, and other kinds of tensor operations of various size, level, and rank while achieving unprecedented performance by parallel computations.

[0110] In addition, the CMC cell in FIG. 3(i) not only can operate in the triode region to support multiplier mode, but can also operate in other modes such as ReLU, saturation, or rectifier modes. In other words, CMC branches for embodiments of the present invention can support transistor vector-vector operations using scalar functions other than multiplication, such as ReLU, saturation, or rectifier functions. Since all transistor tensor operations are based on transistor vector-to-vector operations, CMC branches for embodiments of the present invention are therefore able to support transistor vector-vector, transistor matrix-vector, transistor matrix-matrix, and other kinds of transistor tensor operations of various size, depth, and rank while achieving unprecedented performance by parallel computations executed by CMC cells.

[0111] FIG. 3(j) shows the schematic symbol for another embodiment of a CMC cell (992) that can be used in the layer-one block (B.sub.m,n) illustrated in FIG. 3(h). In this embodiment, the CMC cell (992) comprises one field-programmable-threshold voltage transistor (FM.sub.i,j) that is controlled by the gate-to-source voltage (VG.sub.i,j), drain-to-source voltage (VD.sub.i,j), and the storage charge stored in its floating-gate (Q.sub.i,j). Its channel current (I.sub.i,j) is the CMC cell output current. The channel current (I.sub.i,j) is a function of (VG.sub.i,jV.sub.T0C.sub.eQ.sub.i,j) and VD.sub.i,j according to the I-V relationship of the transistor. A CMC branch equipped with such CMC cells (992) is therefore able to support transistor vector-vector operations of two input vectors (VD.sub.i,1, . . . , VD.sub.i,j, . . . , VD.sub.i,M) and ((VG.sub.i,1V.sub.T0C.sub.eQ.sub.i,1), . . . , (VG.sub.i,jV.sub.T0C.sub.eQ.sub.i,j), . . . , (VG.sub.i,MV.sub.T0C.sub.eQ.sub.i,M)). The most common embodiment of field-programmable-threshold voltage transistors are floating-gate MOS transistors. The floating-gate transistor (FM.sub.i,j) not only can execute scalar functions supported by common MOS transistors as a computation transistor, but can also serve as a memory device for storing operation parameters.

[0112] FIG. 3(k) shows the schematic symbol for another embodiment of a CMC cell (993) that can be used in FIG. 3(h). This CMC cell comprises one computation transistor (MD.sub.i,j) that executes scalar computations and provides its channel current (I.sub.i,j) as the cell output current of the CMC cell. One select transistor (MW.sub.i,j) provides the gate voltage (VG.sub.i,j) of the computation transistor from a cell gate voltage input line (BL) when the select transistor is activated by its gate select signal (WL) and isolates the gate terminal of the computation transistor from the cell gate voltage input line (BL) when the select transistor is deactivated by WL. This select transistor (MW.sub.i,j) can be an MOS transistor (including a native transistor), a field effect transistor, or other types of transistors; it also can be a variable resistor controlled by WL. This CMC cell (993) is able to support all transistor tensor operations that the CMC cell (991) in FIG. 3(i) can support. In addition, this CMC cell (993) also functions as a memory device by holding the value of the gate voltage of the computation transistor (MD.sub.i,j). However, it cannot fix the voltage indefinitely due to non-ideal effects such as leakage currents. To maintain the value of the gate voltage, it can refresh the value by rewriting the same value periodically, similar to how memory is updated in dynamic random-access memory (DRAM). This CMC cell (993) is therefore a current-mode computation dynamic memory cell.

[0113] FIG. 3(l) shows the schematic symbol for another embodiment of a CMC cell (994) that is nearly identical to the CMC dynamic memory cell (993) in FIG. 3(k). This cell however has a storage-control capacitor (C.sub.i,j); one terminal of (C.sub.i,j) is coupled to the gate terminal of the computation transistor (MD.sub.i,j) and the other terminal is coupled to a field-programmable CMC cell gate voltage control signal (GC). When the voltage on GC is a constant, the storage-control capacitor (C.sub.i,j) behaves as a storage capacitor that helps to reduce the influence of leakage currents and voltage coupling problems, similar to the functions of the storage capacitors in DRAM memory cells. When GC is controlled as an input signal, then the CMC cell in FIG. 3(l) functions as a floating gate device that can support the functions of the CMC cell in FIG. 3(j), where VG.sub.i,j behaves as the floating gate and GC as the gate of the floating gate device, except that the storage charge of this device may need to be refreshed periodically.

[0114] FIG. 3(m) shows the schematic symbol for an embodiment of a plurality of CMC cells (995, 996, 997) that share one select transistor (MW.sub.s) that provides the gate voltage (VG.sub.s) of the computation transistors in those CMC cells (995, 996, 997) from an cell gate voltage input line (BL) when the select transistor is activated by its gate select signal (WL) and isolates the gate terminals of those computation transistors from the cell gate voltage input line (BL) when the select transistor is deactivated by WL. The CMC cells (995, 996, 997) can be in different CMC branches. The circuit in FIG. 3(m) is also a type of CMC dynamic memory cell because it can store and maintain datum with dynamic refresh procedures. Such design is useful when the same input is shared by multiple CMC cells like when performing transistor convolution tensor operations. For CMC dynamic memory cells of embodiments of the present invention, reduction of transistor leakage currents is more important than transistor performance. Use of body effects by proper selection of substrate voltages can reduce leakage currents.

[0115] FIG. 3(n) shows the schematic symbol for another embodiment of a CMC cell (1011) that can be used in the layer-one block (B.sub.m,n) illustrated in FIG. 3(h). In this embodiment, the CMC cell (1011) comprises one computation resistor (RM.sub.i,j). A computation resistor is a resistor in a CMC cell that is used to support computation function for the CMC cell. One terminal of the computation resistor (RM.sub.i,j) is coupled to an input line at voltage VR.sub.j while the other terminal is connected to a summation line at voltage VRs.sub.i, as shown in FIG. 3(p). The CMC cell output current I.sub.i,j=(VR.sub.jVRs.sub.i)/(RRM.sub.i,j), where RRM.sub.i,j is the resistance value of the computation resistor RM.sub.i,j. The branch output current (Is.sub.i) of CMC branch CM.sub.i is the current mode summation of all the CMC cells coupled to the branch summation line (371) as Is.sub.i=.sub.j.sup.M(VR.sub.jVRs.sub.i)/(RRM.sub.i,j). A CMC branch equipped with such CMC cells (1011) is therefore able to support transistor vector-vector operations of two input vectors (1/RRM.sub.i,1, . . . , 1/RRM.sub.i,j, . . . , 1/RRM.sub.i,M) and ((VR.sub.1VRs.sub.i), . . . , (VR.sub.iVRs.sub.i), . . . , (VR.sub.MVRs.sub.i)). Therefore, this CMC cell (1011) is able to execute tensor computations. The current-voltage relationships of ideal resistors are linear, so that this CMC cell (1011) operates in multiplier mode.

[0116] FIG. 3(o) shows the schematic symbol for another embodiment of a CMC cell (1012) that is almost the same as the CMC cell (1011) in FIG. 3(n) except that it comprises a variable computation resistor (RV.sub.i,j) instead of a resistor with a fixed value. The resistance value of this variable computation resistor (RV.sub.i,j) can be controlled by a variable computation resistor control signal (VRc.sub.j), which also can be used as a field-programmable input signal. Such variable computation resistor can be implemented using MOS transistor, field effect transistor (FET), floating-gate transistor, or other types of devices.

[0117] Resistors built by current art integrated circuit technologies are larger and more difficult to be precise than transistors so that the CMC cells in FIGS. 3(n, o) do not have advantages over the CMC cells in FIG. 3(i-m) if they are built on the active areas used to build transistors. However, resistors can be built without using active areas, as illustrated in FIG. 7(a). In this embodiment, transistors (1071) are built on a semiconductor substrate (1070), while computation resistors (1075) are built on top of those transistors, as shown by the simplified cross-section picture in FIG. 7(a). One terminal of the computation resistor (1075) is coupled to a metal input line (1076), while the other terminal of the computation resistor (1075) is coupled to a piece of metal (1077) which is connected to a current summation line (1074) using a via (1078). This current summation line (1074) is connected to the diffusion area (1072) of a transistor (1071) using a contact (1073). Each computation resistor (1075) and nearby metal structures (1076, 1077) form a CMC cell that does not occupy active semiconductor areas that can be used to build transistors (1071). Such CMC cells are therefore able to achieve higher density at lower cost. FIG. 7(b) shows another example where computation resistors (1079) are built inside via holes between an input line (1078) and a summation line (1074). Current art integrated circuit technologies can have 20 layers of metals so that it is also possible to stack computation resistors in large number of layers as illustrated in FIG. 7(c). In this cross-section diagram, 10 layers of computation resistors (1081) are stacked on top of transistors (1071). Each computation resistor (1081) and nearby metal structures (1082, 1083) form a CMC cell illustrated in FIG. 3(n) or FIG. 3(o). A summation line (1074) is connected to computation resistors in different layers through vias (1084). Tensor operations with billions, trillions or more parameters can be executed by a small semiconductor dice using such structures. We will call electrical components that are embedded in the inter-layer dielectric (ILD) layers of integrated circuits as ILD embedded components. These components can include transistors, resistors, and other electrical components that are embedded in the ILD layers to reduce the overall size of the integrated circuit.

[0118] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. The transistor in the CMC cell shown in FIG. 3(i) is an n-channel MOS transistor, while other types of transistors such as p-channel transistors, field-effect transistors (FET), bipolar transistors, and combinations of other types of electrical devices also can be used in CMC cells. The CMC cell output current does not have to be the drain-to-source current; a source-to-drain current also can be used as the output current. Combinations of channel currents and/or resistor currents from multiple sources also can be used as the CMC cell output current. Current art IC technologies typically manufacture transistors that are optimized for speed. For transistors used in CMC cells of embodiments of the present invention, low leakage and low power are of greater priority. Body effects can be used to reduce leakage currents of the transistors in the CMC cells. The computation resistors shown in FIG. 7(a-c) can be fixed value resistors, variable resistors, poly silicon transistors, or other types of ILD embedded components. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0119] FIG. 3(p) shows a simplified schematic diagram for an embodiment of a hybrid-analog-digital (HAD) CMC cell. A HAD CMC cell is defined as a CMC cell that is designed to support computations between a digital input and an analog input. In this example, the CMC cell (1005) comprises 4 sub-cells (1000-1003), where each sub-cell comprises one binary memory device (MC0.sub.i,j, MC1.sub.i,j, MC2.sub.i,j, MC3.sub.i,j), one enable transistor (ME0.sub.i,j, ME1.sub.i,j, ME2.sub.i,j, MC3.sub.i,j), and one computation resistor (RM0.sub.i,j, RM1.sub.i,j, RM2.sub.i,j, RM3.sub.i,j) of predefined resistor value (RM0, RM1, RM2, RM3). All four sub-cells (1000-1003) are connected to an input line at voltage VR.sub.j, and provide sub-cell output currents (I0.sub.i,j, I1.sub.i,j, I2.sub.i,j, I3.sub.i,j) combined to be a CMC cell (1005) output current (I.sub.i,j), where I.sub.i,j=(I0.sub.i,j+I1.sub.i,j+I2.sub.i,j+I3.sub.i,j), as illustrated in FIG. 3(p). This CMC cell output current (I.sub.i,j) flows into a current summation line at voltage VRs.sub.i, as shown in FIG. 3(p). The binary memory devices (MC0.sub.i,j, MC1.sub.i,j, MC2.sub.i,j, MC3.sub.i,j) are memory devices that stores one binary number (0 or 1). Examples of such binary memory devices are DRAM cells, static-random-access-memory (SRAM) cells, floating-gate transistors, or other types of memory devices. The data stored in these memory devices (MC0.sub.i,j, MC1.sub.i,j, MC2.sub.i,j, MC3.sub.i,j) control gate voltages (Vg0.sub.i,j, Vg1.sub.i,j, Vg2.sub.i,j, Vg3.sub.i,j) of the enable transistors (ME0.sub.i,j, ME1.sub.i,j, ME2.sub.i,j, MC3.sub.i,j) to activate or turn off those transistors. For example, when MC0.sub.i,j stores binary number 1, ME0.sub.i,j is activated, and the output current of the sub-cell (1000) I0.sub.i,j=(VR.sub.jVRs.sub.i)/RM0; when MC0.sub.i,j stores binary number 0, ME0.sub.i,j is turned off, and I0.sub.i,j is approximately zero; when MC1.sub.i,j stores binary number 1, ME1.sub.i,j is activated, and the output current of the sub-cell (1001) I1.sub.i,j=(VR.sub.jVRs.sub.i)/RM1; when MC1.sub.i,j stores binary number 0, ME1.sub.i,j is turned off, and I1.sub.i,j is approximately zero; when MC2.sub.i,j stores binary number 1, ME2.sub.i,j is activated, and the output current of the sub-cell (1002) I2.sub.i,j=(VR.sub.jVRs.sub.i)/RM2; when MC2.sub.i,j stores binary number 0, ME2.sub.i,j is turned off, and I2.sub.i,j is approximately zero; when MC3.sub.i,j stores binary number 1, ME3.sub.i,j is activated, and I3.sub.i,j=(VR.sub.jVRs.sub.i)/RM3; and when MC3.sub.i,j stores binary number 0, I3.sub.i,j is approximately zero. In this example, if we control the values of the computation resistors so that RM3=RM0/8, RM2=RM0/4, and the RM1=RM0/2, then the data stored in the 4 memory devices (MC0.sub.i,j, MC1.sub.i,j, MC2.sub.i,j, MC3.sub.i,j) form a 4-bit binary number, and the CMC cell output current (I.sub.i,j) equals the binary number times (VR.sub.jVRs.sub.i)/RM0. The CMC cell illustrated in FIG. 3(p) is therefore an embodiment of a hybrid-analog-digital (HAD) CMC cell that is designed to support computations between a digital input and an analog input.

[0120] FIG. 3(q) is a simplified schematic diagram of another embodiment of a HAD CMC cell (1025). The structures of this CMC cell (1025) are nearly the same as those of the HAD CMC cell (1005) in FIG. 3(p) except that the computation resistors (RV0.sub.i,j, RV1.sub.i,j, RV2.sub.i,j, RV3.sub.i,j) in the sub-cells (1020-1023) are variable resistors controlled by an HAD cell variable computation resistor control voltage (VVR.sub.j), as illustrated in FIG. 3(q). This HAD CMC cell (1025) is therefore able to execute computations between digital data stored in memory devices (MC0.sub.i,j, MC1.sub.i,j, MC2.sub.i,j, MC3.sub.i,j) and analog inputs represented by (VR.sub.jVRs.sub.i) or represented by WR.sub.j.

[0121] FIG. 3(r) is a simplified schematic diagram of another embodiment of a HAD CMC cell (1035). The structures of this CMC cell (1035) are nearly the same as those of the HAD CMC cell (1025) in FIG. 3(q), except that the variable computation resistors are replaced by transistors (MVR0.sub.i,j, MVR1.sub.i,j, MVR2.sub.i,j, MVR3.sub.i,j) in the sub-cells (1030-1033). The gate terminals of these transistors (MVR0.sub.i,j, MVR1.sub.i,j, MVR2.sub.i,j, MVR3.sub.i,j) are controlled by an HAD cell gate voltage control signal (VVG.sub.j), as illustrated in FIG. 3(r). When those transistors (MVR0.sub.i,j, MVR1.sub.i,j, MVR2.sub.i,j, MVR3.sub.i,j) are operating in triode region, they behave as variable computation resistors so that this CMC cell (1035) can support similar functions as the CMC cell (1025) in FIG. 3(q). In addition, the transistors (MVR0.sub.i,j, MVR1.sub.i,j, MVR2.sub.i,j, MVR3.sub.i,j) can operate in saturation regions to function as current mirrors. This enables execution of computations between digital data stored in memory devices (MC0.sub.i,j, MC1.sub.i,j, MC2.sub.i,j, MC3.sub.i,j) and analog inputs represented by (VR.sub.jVRs.sub.i) or by WG.sub.j.

[0122] FIG. 3(s) is a simplified schematic diagram of another embodiment of a HAD CMC cell (1045). The structures of this CMC cell (1045) are nearly the same as those of the HAD CMC cell (1035) in FIG. 3(r), except that enable transistors (ME0.sub.i,j, ME1.sub.i,j, ME2.sub.i,j, MC3.sub.i,j) and the binary memory devices (MC0.sub.i,j, MC1.sub.i,j, MC2.sub.i,j, MC3.sub.i,j) in FIG. 3(r) are replaced by floating-gate transistors (MCF0.sub.i,j, MCF1.sub.i,j, MCF2.sub.i,j, MCF3.sub.i,j). The gate terminals of these floating-gate transistors (MCF0.sub.i,j, MCF1.sub.i,j, MCF2.sub.i,j, MCF3.sub.i,j) are controlled by an HAD cell floating gate control signal (VVFG.sub.j), as illustrated in FIG. 3(s). These floating-gate transistors (MCF0.sub.i,j, MCF1.sub.i,j, MCF2.sub.i,j, MCF3.sub.i,j) serve both the functions of binary memory device as well as the functions of the enable transistors. If a These floating-gate transistors (MCF0.sub.i,j, MCF1.sub.i,j, MCF2.sub.i,j, MCF3.sub.i,j) is programmed to store binary number 0, the transistor is always off; and if it is programmed to store binary number 1, then the transistor can be activated by WFG.sub.j. This enables execution of computations between digital data stored in memory devices (MCF0.sub.i,j, MCF1.sub.i,j, MCF2.sub.i,j, MCF3.sub.i,j) and analog inputs represented by (VR.sub.jVRs.sub.i) or by WG.sub.j.

[0123] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. For example, the digital data stored in HAD CMC cells do not need to be 4-bit binary datalarger or smaller digital data also can be used as inputs to HAD CMC cells. The analog input signals do not have to be voltagesanalog signals represented by electrical currents or other formats also can be used. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0124] FIG. 4(a) is a simplified symbolic block diagram of an embodiment of a layer-three block (B.sup.(3)) of the present invention. This layer-three block (B.sup.(3)) comprises R columns and T rows of layer-two blocks (B.sup.(2).sub.r,t), where R and T are positive integers, r is an integer greater than or equal to 1 and less than or equal to R, and t is an integer greater than or equal to 1 and less than or equal to T. The layer-three summation lines (401) are coupled to the layer-two current summation circuit (IS2) inside those layer-two blocks (B.sup.(2).sub.r,t). Embodiments of layer-two blocks are illustrated in FIG. 3(a, h), while an embodiment of layer-two current summation circuit (IS2) is illustrated in FIG. 3(e). An individual layer-three summation line (401) comprises an electrical conductor that is electrically coupled to, and receives the layer-two current summation circuit output currents produced by, a plurality of layer-two current summation circuits (IS2), and that produces a layer-three summation line output current (Is.sup.(3)) that is a current-mode summation of the received layer-two current summation circuit output currents (ideally, Is.sup.(3)=.sub.s Io.sup.(2).sub.s). This layer-three block (B.sup.(3)) comprises a plurality of layer-three current summation circuits (IS3), wherein an individual layer-three current summation circuit is electrically coupled to, and receives the layer-three summation line output current (Is.sup.(3)) produced by, at least one layer-three summation line (401), and produces a layer-three current summation circuit output current (Io.sup.(3)) that is a function of all received layer-three summation line output currents (Is.sup.(3)). FIG. 4(b) is a simplified schematic diagram of one embodiment of the layer-three current summation circuit (IS3) in FIG. 4(a). In this embodiment, four matched transistors (Mn1, Mn2, Mn3, Mn4) and four enable transistors (Mne1, Mne2, Mne3, Mne4) are connected as current mirrors, as shown in FIG. 4(b). N-channel transistors are used in IS3 because the polarity of the input current (Is.sup.(3)) is opposite of that of the layer-two current summation circuits (IS2). In addition, two matched p-channel transistors (Mp5, Mp6) and two enable transistors (Mpe5, Mpe6) are connected as a current mirror to duplicate the current amplitude and invert the polarity of the current flows through Mn4, as shown in FIG. 4(b). When the field-programmable enable signals ENn1 and ENn2 are activated and ENn3 is deactivated, the layer-three summation circuit output current Io.sup.(3)=(Wn2/Wn1)Is.sup.(3), where Wn2 is the effective channel width of transistor Mn2 and Wn1 is the effective channel width of transistor Mn1. When the field-programmable enable signals ENn1 and ENn3 are activated and ENn2 is deactivated, the output current Io.sup.(3)=(Wn3/Wn1)Is.sup.(3), where Wn3 is the effective channel width of transistor Mn3. When the field-programmable enable signals ENn1, ENn4, ENp5, and ENp6 are activated, a current Iso3=(Wn4/Wn1)Is.sup.(3) is sent to the interface output circuit (Vout), as illustrated in FIG. 4(b), where Wn4 is the effective channel width of transistor Mn4. The function of the interface output circuit (Vout) in this embodiment can be the same as that in FIG. 3(f). IS3 is also able to prevent current overload because current mirror circuits by nature have an upper limitation on maximum value of output currents.

[0125] The layer-three block (B.sup.(3)) in FIG. 4(a) also has layer-three input circuits (VI3) that drive layer-three input lines (403). These layer-three input circuits (VI3) also can be implemented by S&H circuits similar to that of FIG. 3(c). The layer-three input lines (403) and layer three input circuits (VI3) provide field-programmable controls on the layer-two input circuits (VI2) in all the layer-two blocks (B.sup.(2).sub.r,t). Therefore, the voltages on the layer-one input lines (Vd.sub.j, Vg.sub.j) in all layer-one blocks included in this layer-three block (B.sup.(3)) can be controlled by those layer-three input circuits (VI3). This multiple-layer input configuration supports field-programmable input configurations that approaches the flexibility of prior art software configurations. Such flexible multiple-layer input configurations can be used to duplicate the same sets of inputs into different layer-one blocks that have different branch summation lines in order to expand the number of outputs. If the number of inputs is greater than the capacity of one layer-two block, we can use the layer-three current summation circuits (IS3) to form a three-layer current summation structure to support more inputs without significant increases in delay time. If insufficient, more layers can be added until the requirement is fulfilled. Similarly, layer-three input circuits (VI3) can be used to expand the number of output neurons.

[0126] FIG. 5(a) is a simplified block diagram for an embodiment of a multiple-layer summation line architecture of the present invention described in FIGS. 3(a-h) and in FIG. 4(a-c). A subset of CMC cells (501) represented symbolically by small circles in FIG. 5(a) are coupled to a branch summation line (503). All the cell output currents (502) from those CMC cells (501) flow into the branch summation line (503) that brings current mode summation of all the cell output currents to a layer-one current summation circuit (IS1). This circuit produces a layer-one current summation circuit output current (504) that is a function of the summation of all CMC cell output currents (502) from the CMC cells (501) coupled to the branch summation line (503). All layer-one current summation circuit output currents (504) of the layer-one current summation circuits (IS1) are received by a layer-two summation line (505) and are inputted to a layer-two current summation circuit (IS2) that produces a layer-two summation circuit output current (507) that is a function of the current-mode summation of the layer-one current summation circuit output currents received by the layer-two summation line (505). Similarly, the layer-two current summation circuit output currents (507) are received by a layer-three summation line (508) such that the summation of the IS2 output currents is input to a layer-three current summation circuit (IS3). This multiple layer architecture can be expanded to an arbitrary number of layers. If the number of inputs can be supported in layer-two, IS2 can send the result of current summation to an interface output circuit (506) that produces the inputs for the next level transistor tensor operation or produces digitized outputs to a digital interface. If a third layer is needed, then outputs are produced at the layer-three interface output circuit (509). One can continue to add additional layers as neededoutputs will be produced at the final layer. If one semiconductor dice cannot provide the needed computation memory cells, upper layer summation lines or input lines can be implemented by inter-dice connections to expand parallel transistor computations beyond dice boundaries, as illustrated in FIGS. 5(d, e). The architecture illustrated in FIG. 5(a) provides flexibility to configure CMC cells to support large-scale transistor tensor operations. Prudent designs of the summation lines in each layer can mitigate non-ideal parasitic parameters induced problems such that the delay time introduced by each layer is only the delay time of current mirrors. With this architecture, large-scale transistor tensor operations can be executed within a few gate delays.

[0127] FIG. 5(b) is a simplified block diagram for an embodiment of input control architecture of the present invention described in FIGS. 3(a-h) and in FIG. 4(a-c). Layer-three input circuits (VI3) drive layer-three input lines (513) under field-programmable controls to reach layer-two input circuits (VI2). Layer-two input circuits (VI2) drive layer-two input lines (512) under field-programmable controls to reach layer-one input circuits (VI1, VI1g). Layer-one drain voltage and gate voltage input circuits (VI1, VI1g) drive layer-one input lines inside layer-one blocks (B.sub.i,j) to configure CMC cells. All input circuits (VI3, VI2, VI1, VIg) in various layers only drive a limited number of active devices, mitigating non-ideal parasitic parameter induced problems. If the number of outputs is greater than the number of outputs in layer-one blocks, the inputs are duplicated to other layer-one blocks that have different current summation trees, effectively expanding the overall number of outputs. Careful designs for the input lines in each layer can mitigate non-ideal parasitic parameter induced problems such that the delay time introduced by each layer is the delay time of input circuits (VI3, VI2, VI1, VI1g): one analog gate delay per layer. The architecture illustrated in FIG. 5(b) provides flexibility to configure CMC cells to support transistor tensor operations of various sizes. With this architecture, large-scale transistor tensor operations can be executed in parallel within a few gate delays.

[0128] A transistor tensor operation of embodiments of the present invention comprises many field-programmable options to allow flexibility in configuration. These options are typically selected by register write, scan chain, or memory write operations to memory devices distributed around an integrated circuit (IC) of embodiments of the present invention. The procedures to define those available options require detailed knowledge of actual designs, and such details can differ between IC designs. Therefore, a packaged IC chip of embodiments of the present invention typically comprises integrated circuits of different functions packaged in the same chip, as shown by the symbolic block diagram in FIG. 5(c). In this embodiment, multiple layer current-mode computation integrated circuits of embodiments of the present invention (521) are packaged in the same package with CPU or GPU (522), a flash EPROM (523), a system memory (524) which is typically a dynamic random-access memory (DRAM) IC, and an image sensor or image display IC (528). The multiple layer CMC IC (521) of embodiments of the present invention can have multiple stacked ICs as described in above sections. FIG. 5(d) shows a simplified embodiment of horizontal inter-dice communication lines (537) between different IC dice (531, 532, 533, 534). FIG. 5(e) shows a simplified embodiment of through-die inter-dice communication lines (547) between vertically stacked IC dice (541, 542, 543, 544). The microprocessor (522) executes firmware stored in the flash EPROM (523) to configure CMC IC (521) through a digital interface (525). The system memory (524) is used for temporary storages to achieve better performance. The Flash EPROM (523) also can store information such as which parts in the transistor tensor operation (521) ICs are defective, which blocks are used by which application, and the parameters needed to configure the CMC IC (521). Libraries of firmware circuits are also stored in the flash EPROM (523) to support functions similar to those of an operating system. The CMC ICs (521) also can send data to the microprocessor (522) through a digital interface (525) such that the microprocessor (522) can assist in executing computations that are not built in the ICs computing the transistor tensor operations. This digital interface (525) also provides the capability to communicate with external systems through an external digital interface (526). The CMC ICs (521) can also have a direct communication interface (527) with image sensor and/or image display ICs (528). This direct communication interface (527) can be a digital interface or an analog interface.

[0129] The architectures illustrated in FIGS. 3(a-h), FIG. 4(a-c), and FIG. 5(a-c) provide flexibility to configure CMC cells to support transistor tensor operations of wide varieties of sizes. For example, if a layer-one array comprises 128 inputs and 64 outputs, while each upper layer summation line connects 32 lower layer current summation circuits and each upper layer input line connects 32 lower layer input circuits, then a layer-two block can support a transistor tensor operation of up to 8 million parameters; a layer-three block can support up to 8 billion parameters; a layer-four block would be able to support up to 8 trillion parameters. If all the devices in an integrated circuit are insufficient to support the parameters of the transistor tensor operation being executed, the analog or digital output circuits allow convenient interfaces to other integrated circuits to expand into multiple-dice operations. For smaller computations, the unused layer-one blocks can be configured to support computations at different levels, or computations of other applications. Under this architecture, multi-leveled large-scale transistor tensor operations can be implemented with a flexible field-programmable configuration. Each level of transistor tensor operations can be executed in parallel and finished in a few gate delays, and multiple-level transistor tensor operations can be executed in parallel for a few gate delays in each level. Using the sample-and-hold circuits, one can choose to pipeline multiple-level computations to achieve higher throughputs or disable unused circuits to save power.

[0130] To better understand the performance gains of a multiple-layer summation circuit of embodiments of the present invention, consider a three-layer network of an embodiments of present invention that comprises 10 billion CMC cells. Delay time for each computation is approximately that of one analog gate plus two current mirrors, which is about 2 nanoseconds. When all 10 billion of computation-summations are executed in parallel within 2 nanoseconds, 510.sup.18 computation-summations are executed per second. For a four-layer network of embodiments of the present invention, the performance can reach 510.sup.21 computation-summations per second or higher.

[0131] Under programmable controls, the CMC cells can be configured to operate at multiplier mode such that a deep learning model that comprises a sequence of transistor tensor operations of embodiments of the present invention can be fully compatible with existing digital neural network devices. That means we can port the results of an existing deep learning model into a device of an embodiment of the present invention to support the same functions. In addition, each individual neuron can be configured to operate in its own operation mode, such as multiplier mode, ReLU mode, rectifier mode, or saturation mode to adapt for the nature of individual neurons to potentially achieve better results than prior art digital neural network devices. Similarly, the output functions for each individual output neuron also can be configured to its own specific function to potentially achieve better results.

[0132] Because summations are commutative, if one CMC branch is defective, we can mark and disable that CMC branch and use a different CMC branch to replace its functions; if one layer-one block is defective, we can mark and disable that block and use a different layer-one block to replace its functions; defects at any layer can be handled the same way. The marks for defective parts can be stored in the flash EPROM (523) such that other applications can avoid known defective parts. This flexible redundancy architecture significantly improves yield, and reduces costs.

[0133] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. Skillful circuit designers will be able to design circuits in wide varieties of ways. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0134] In the above embodiments, channel currents of computation transistors always flow in the same direction, meaning all parameters are positive. For some cases, it is desirable to have both positive and negative parameter values. FIG. 6(a) is a simplified schematic diagram for a CMC cell that comprises two computation transistors (fgTp, fgTn) with gate terminals coupled to the same input at voltage Vg. The source terminal of fpTp and the drain terminal of fpTn are coupled to a branch summation line (Is) which is forced at a voltage Vs, as shown in FIG. 6(a). The drain terminal of fpTp is coupled to a constant drain voltage (Vdp) greater than Vs, causing the channel current (Ip) of fpTp to flow into the branch summation line (Is); the source terminal of fpTn is coupled to a constant drain voltage (Vsn) less than Vs, causing the channel current (In) of fpTn to flow away from the branch summation line (Is), as shown in FIG. 6(a). The overall channel current of this two-transistor cell is therefore IpIn, which can be positive when Ip>In or negative when Ip<In. Two transistors configured as the embodiment in FIG. 6(a) to support one computation are therefore able to model both positive and negative parameter values.

[0135] Another embodiment to support both positive and negative values is to use the same layer-one block as discussed in previous embodiments while taking the difference of branch output currents from two nearby columns using the current subtraction circuit (611) illustrated by the simplified symbolic embodiment in FIG. 6(b). In this embodiment, two matched transistors (Mpp, Mpn) and two enable transistors (Mppe, Mpne) are configured as a current mirror. The input of the current mirror is connected to one branch summation line with a branch output current Isp and the other end of the current mirror is connected to another branch summation line with a branch output current Isn, as shown in FIG. 6(b). When field-programmable enable signals ENpp and ENpn are both activated, the output current of this current subtraction circuit (611) is IspIsn. Using such current subtraction circuits (611), each scalar computation in the level-one block is modeled by a CMC cell along one branch summation line and another CMC cell along the other branch summation line that have the same input voltages, resulting in scalar computations that can have positive or negative results.

[0136] In the above embodiment, the current summation circuit needs to support input currents of different polarities. FIG. 6(c) is a simplified schematic diagram for an exemplary dual polarity current mirror (DPCM). In this embodiment, matched p-channel transistors (Mp7, Mp8, Mp9) and enable transistors (Mpe7, Mpe8, Mpe9) are configured as p-channel current mirrors; matched n-channel transistors (Mn7, Mn8, Mn9) and enable transistors (Mne7, Mne8, Mne9) are configured as n-channel current mirrors, as shown in FIG. 6(c). When the input current (Isi) is positive, current flows through diode DN to the n-channel current mirrors while diode DP blocks the current such that the output currents of the p-channel current mirrors are approximately zero. The resulting output current (Ino) is therefore completely generated by the n-channel current mirrors. When the input current (Isi) is negative, current flows through diode DP to the p-channel current mirrors while diode DN blocks the current such that the output currents of the n-channel current mirrors are approximately zero. The resulting output current (Ino) is therefore completely generated by the p-channel current mirrors. Therefore, this dual polarity current mirror (DPCM) works for input currents of both polarities. The diodes DN and DP can be implemented by transistors configured in rectifier modes.

[0137] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. For example, different types of CMC cells can be designed to support both positive and negative parameters. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0138] In the above embodiments, input values are always positive. It is often desirable to have both positive and negative input values. FIG. 6(d) is a simplified schematic for a CMC cell that comprises four matched transistors (Mpp, Mpn, Mnp, Mnn). The source terminals of Mpp and Mpn are connected to the branch summation line (Isp) that is connected to the current subtraction circuit in FIG. 6(b). The drain terminals of Mpp and Mnp are connected to the same input line (Vdip); the drain terminals of Mpn and Mnn are connected to another input line (Vdin); the gate terminals are all connected to the same gate voltage Vg, as shown in FIG. 6(d). The source terminals of Mnp and Mnn are connected to another branch summation line (Isn) that is connected to the input of the current subtraction circuit in FIG. 6(b). The contribution of this CMC cell (631) to the overall summation current is therefore Idpp+IdpnIdnpIdnn, where Idpp is the channel current of computation transistor Mpp, Idpn is the channel current of computation transistor Mpn, Idnp is the channel current of computation transistor Mnp, and Idnn is the channel current of computation transistor Mnn. Computation transistor Mpp and computation transistor Mnn are programmed to have the same storage charges. Therefore, when all inputs are equal, Idpp is equal to Idnn. Similarly, computation transistor Mnp and computation transistor Mpn are programmed to have equal storage charges; when all inputs are the same, Idnp equals Idpn. For a positive input at voltage Vdinp, Vdip is set to voltage Vdinp and Vdin is set to Vs. The contribution of this CMC cell (631) is (IdppIdnp). For a negative input at voltage Vdinp, Vdip is set to voltage Vs and Vdin is set to voltage Vdinp. The contribution of this CMC cell (631) is (IdpnIdnn). Since the input voltages are equivalent under both conditions, we have (IdpnIdnn)=(IdppIdnp), which is equivalent to a negative input.

[0139] While the preferred embodiments have been illustrated and described herein, other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. For example, one can allow drain input voltage to be less than Vs to achieve positive and negative inputs. This works if the amplitudes of the input voltages are small. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.

[0140] While specific embodiments of the invention have been illustrated and described herein, it is realized that other embodiments of the invention may incorporate modifications and changes to the embodiments described herein. It is therefore to be understood that the appended claims are intended to cover all modifications and changes that fall within the true spirit and scope of the invention.