CIRCUIT CAPABLE OF AUTOMATICALLY ADJUSTING IMPEDANCE THEREOF

Abstract

The present invention provides a circuit capable of automatically adjusting impedance thereof having a wide adjustment range and high accuracy by selecting a pull-up code and a pull-down code for obtaining resistances closest to those of a first reference resistor and a second reference resistor, respectively, using a first reference P-code and a second reference P-code, and a first reference N-code and a second reference N-code.

Claims

1. A circuit capable of automatically adjusting impedance thereof, the circuit comprising: a first voltage divider comprising: a first pull-up resistor and a second pull-up resistor connected in parallel and having resistances, respectively, varying according to a reference P-code applied thereto; and a first reference resistor having a constant resistance and connected in series with the first pull-up resistor and the second pull-up resistor connected in parallel, a pull-up code selector sequentially applying: a first reference P-code and the first reference P-code; the first reference P-code and a second reference P-code; and the second reference P-code and the second reference P-code to the first pull-up resistor and the second pull-up resistor, respectively; a first comparator providing a comparison value V.sub.COMP1 to the pull-up code selector wherein the comparison value V.sub.COMP1 is obtained by comparing 0.5V.sub.DD to a voltage V.sub.DIV1 across the first reference resistor when a voltage V.sub.DD is applied to the first voltage divider; a second voltage divider comprising: a second reference resistor having a resistance varying according to a pull-up code applied by the pull-up code selector; and a first pull-down resistor and a second pull-down resistor connected in parallel and having resistances, respectively, varying according to a reference N-code applied thereto wherein the first pull-down resistor and the second pull-down resistor are connected in series with the second reference resistor; a pull-down code selector sequentially applying: a first reference N-code and the first reference N-code; the first reference N-code and a second reference N-code; and the second reference N-code and the second reference N-code to the first pull-down resistor and the second pull-down resistor, respectively; and a second comparator providing a comparison value V.sub.COMP2 to the pull-down code selector wherein the comparison value V.sub.COMP2 is obtained by comparing 0.5V.sub.DD to a voltage V.sub.DIV2 across the first pull-down resistor and the second pull-down resistor when the voltage V.sub.DD is applied to the second voltage divider, wherein the first comparator performs a comparison each time the reference P-code is applied and provides three comparison values V.sub.COMP1 to the pull-up code selector, the pull-up code selector selects one of the first reference P-code and the second reference P-code as a pull-up code based on the three comparison values V.sub.COMP1, the pull-up code minimizing a difference between: a resistance of the first reference resistor; and a resistance of the first pull-up resistor and the second pull-up resistor connected in parallel, the second comparator performs a comparison each time the reference N-code is applied and provides three comparison values V.sub.COMP2 to the pull-down code selector, and the pull-down code selector selects one of the first reference N-code and the second reference N-code as a pull-down code based on the three comparison values V.sub.COMP2, the pull-down code minimizing the difference between: a resistance of the second reference resistor; and a resistance of the first pull-down resistor and the second pull-down resistor connected in parallel (where second reference P-code is equal to first reference P-code+1, and second reference N-code is equal to first reference N-code+1).

2. The circuit of claim 1, wherein the reference P-code comprises binary data of K bits, and each of the first pull-up resistor and the second pull-up resistor comprises K counts of PMOS transistors provided with gates having the binary data of K bits applied thereto, respectively (where K is a natural number).

3. The circuit of claim 1, wherein the three comparison values V.sub.COMP1 comprise a first comparison value, a second comparison value and a third comparison value, and the pull-up code selector selects the first reference P-code as the pull-up code when the first comparison value=1, the second comparison value=0 and the third comparison value=0 are satisfied, and selects the second reference P-code as the pull-up code when the first comparison value=1, the second comparison value=1 and the third comparison value=0 are satisfied.

4. The circuit of claim 3, wherein the pull-up code selector: (i) increases each of the first reference P-code and the second reference P-code by 1 and then sequentially applies increased first reference P-code and increased second reference P-code to the first pull-up resistor and the second pull-up resistor when the first comparison value=1, the second comparison value=1, and the third comparison value=1 are satisfied; and (ii) selects one of the increased first reference P-code and the increased second reference P-code as the pull-up code based on comparison values of the first comparator obtained from the increased first reference P-code and the increased second reference P-code, the pull-up code minimizing the difference between: the resistance of the first reference resistor; and the resistance of the first pull-up resistor and the second pull-up resistor connected in parallel.

5. The circuit of claim 4, wherein the pull-up code selector: (i) decreases each of the first reference P-code and the second reference P-code by 1 and then sequentially applies decreased first reference P-code and decreased second reference P-code to the first pull-up resistor and the second pull-up resistor when the first comparison value=0, the second comparison value=0, and the third comparison value=0 are satisfied; and (ii) selects one of the decreased first reference P-code and the decreased second reference P-code as the pull-up code based on comparison values of the first comparator obtained from the decreased first reference P-code and the decreased second reference P-code, the pull-up code minimizing the difference between: the resistance of the first reference resistor; and the resistance of the first pull-up resistor and the second pull-up resistor connected in parallel.

6. The circuit of claim 1, wherein the reference N-code comprises binary data of K bits, and each of the first pull-down resistor and the second pull-down resistor comprises K counts of NMOS transistors provided with gates having the binary data of K bits applied thereto, respectively (where K is a natural number).

7. The circuit of claim 1, wherein the three comparison values V.sub.COMP2 comprise a first comparison value, a second comparison value and a third comparison value, and the pull-down code selector selects the first reference N-code as the pull-down code when the first comparison value=1, the second comparison value=0 and the third comparison value=0 are satisfied, and selects the second reference N-code as the pull-down code when the first comparison value=1, the second comparison value=1 and the third comparison value=0 are satisfied.

8. The circuit of claim 7, wherein the pull-down code selector: (i) increases each of the first reference N-code and the second reference N-code by 1 and then sequentially applies increased first reference N-code and increased second reference N-code to the first pull-down resistor and the second pull-down resistor when the first comparison value=1, the second comparison value=1, and the third comparison value=1 are satisfied; and (ii) selects one of the increased first reference N-code and the increased second reference N-code as the pull-down code based on comparison values of the second comparator obtained from the increased first reference N-code and the increased second reference N-code, the pull-down code minimizing the difference between: the resistance of the second reference resistor; and the resistance of the first pull-down resistor and the second pull-down resistor connected in parallel.

9. The circuit of claim 8, wherein the pull-down code selector: (i) decreases each of the first reference N-code and the second reference N-code by 1 and then sequentially applies decreased first reference N-code and decreased second reference N-code to the first pull-down resistor and the second pull-down resistor when the first comparison value=0, the second comparison value=0, and the third comparison value=0 are satisfied; and (ii) selects one of the decreased first reference N-code and the decreased second reference N-code as the pull-down code based on comparison values of the second comparator obtained from the decreased first reference N-code and the decreased second reference N-code, the pull-down code minimizing the difference between: the resistance of the second reference resistor; and the resistance of the first pull-down resistor and the second pull-down resistor connected in parallel.

10. A circuit capable of automatically adjusting impedance thereof, the circuit comprising: a first voltage divider comprising: a first pull-down resistor and a second pull-down resistor connected in parallel and having resistances, respectively, varying according to a reference N-code applied thereto; and a first reference resistor having a constant resistance and connected in series with the first pull-down resistor and the second pull-down resistor connected in parallel, a pull-down code selector sequentially applying: a first reference N-code and the first reference N-code; the first reference N-code and a second reference N-code; and the second reference N-code and the second reference N-code to the first pull-down resistor and the second pull-down resistor, respectively; a first comparator providing a comparison value V.sub.COMP1 to the pull-down code selector wherein the comparison value V.sub.COMP1 is obtained by comparing 0.5V.sub.DD to a voltage V.sub.DIV1 across the first pull-down resistor and the second pull-down resistor connected in parallel when a voltage V.sub.DD is applied to the first voltage divider; a second voltage divider comprising: a second reference resistor having a resistance varying according to a pull-down code applied by the pull-down code selector; and a first pull-up resistor and a second pull-up resistor connected in parallel and having resistances, respectively, varying according to a reference P-code applied thereto wherein the first pull-up resistor and the second pull-up resistor are connected in series with the second reference resistor; a pull-up code selector sequentially applying: a first reference P-code and the first reference P-code; the first reference P-code and a second reference P-code; and the second reference P-code and the second reference P-code to the first pull-up resistor and the second pull-up resistor, respectively; and a second comparator providing a comparison value V.sub.COMP2 to the pull-up code selector wherein the comparison value V.sub.COMP2 is obtained by comparing 0.5V.sub.DD to a voltage V.sub.DIV2 across the second reference resistor when the voltage V.sub.DD is applied to the second voltage divider, wherein the first comparator performs a comparison each time the reference N-code is applied and provides three comparison values V.sub.COMP1 to the pull-down code selector, the pull-down code selector selects one of the first reference N-code and the second reference N-code as a pull-down code based on the three comparison values V.sub.COMP1, the pull-down code minimizing a difference between: a resistance of the first reference resistor; and a resistance of the first pull-down resistor and the second pull-down resistor connected in parallel, the second comparator performs a comparison each time the reference P-code is applied and provides three comparison values V.sub.COMP2 to the pull-up code selector, and the pull-up code selector selects one of the first reference P-code and the second reference P-code as a pull-up code based on the three comparison values V.sub.COMP2, the pull-up code minimizing the difference between: a resistance of the second reference resistor; and a resistance of the first pull-up resistor and the second pull-up resistor connected in parallel (where second reference N-code is equal to first reference N-code+1, and second reference P-code is equal to first reference P-code+1).

Description

BRIEF DESCRIPTION OF DRAWINGS

[0030] FIGS. 1A and 1B are circuit diagrams illustrating a conventional analog PMOS resistance adjusting circuit and a conventional analog NMOS resistance adjusting circuit, respectively.

[0031] FIGS. 2A and 2B are circuit diagrams illustrating a conventional digital PMOS resistance adjusting circuit and a conventional digital NMOS resistance adjusting circuit, respectively.

[0032] FIG. 3 is a circuit diagram illustrating a conventional voltage-mode driver.

[0033] FIG. 4 is a circuit diagram illustrating a circuit capable of automatically adjusting impedance thereof according to a first embodiment of the present invention.

[0034] FIG. 5 is a circuit diagram illustrating a first pull-up resistor (or second pull-up resistor) according to the present invention.

[0035] FIG. 6 is a circuit diagram illustrating a second reference resistor according to the present invention.

[0036] FIG. 7 is a circuit diagram illustrating a first pull-down resistor (or second pull-down resistor) according to the present invention.

[0037] FIGS. 8A to 8C are circuit diagrams illustrating a first pull-up resistor and a second pull-up resistor, respectively, when reference P-codes X.sub.1 and X.sub.1+1 are applied according to the present invention.

[0038] FIG. 9 is a graph illustrating resistances when the reference P-codes X.sub.1 and X.sub.1+1 are applied according to the present invention.

[0039] FIGS. 10A to 10C are circuit diagrams illustrating a first pull-up resistor and a second pull-up resistor, respectively, when reference P-codes X.sub.2 and X.sub.2+1 are applied according to the present invention.

[0040] FIG. 11 is a graph illustrating resistances when the reference P-codes X.sub.2 and X.sub.2+1 are applied according to the present invention.

[0041] FIG. 12 is a circuit diagram illustrating a second reference resistor with a pull-up code applied thereto according to the present invention.

[0042] FIG. 13A to 13C are circuit diagrams illustrating a first pull-down resistor and a second pull-down resistor, respectively, when reference N-codes Y.sub.1 and Y.sub.1+1 are applied according to the present invention.

[0043] FIG. 14 is a graph illustrating resistances when the reference N-codes Y.sub.1 and Y.sub.1+1 are applied according to the present invention.

[0044] FIG. 15A to 15C are circuit diagrams illustrating a first pull-down resistor and a second pull-down resistor, respectively, when reference N-codes Y.sub.2 and Y.sub.2+1 are applied according to the present invention.

[0045] FIG. 16 is a graph illustrating resistances when the reference N-code Y.sub.2 and Y.sub.2+1 are applied according to the present invention.

[0046] FIG. 17 is a circuit diagram illustrating a circuit capable of automatically adjusting impedance thereof according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0047] Hereinafter, a circuit capable of automatically adjusting impedance thereof according to the present invention will be described in detail with reference to the accompanying drawings.

[0048] FIG. 4 is a circuit diagram illustrating a circuit capable of automatically adjusting impedance thereof according to a first embodiment of the present invention.

[0049] Referring to FIG. 4, a circuit 1000 capable of automatically adjusting impedance thereof according to the first embodiment of the present invention includes: a first voltage divider 100; a pull-up code selector 200; a first comparator 300; a second voltage divider 400; a pull-down code selector 500; and a second comparator 600.

[0050] The first voltage divider 100 includes: a first pull-up resistor 100a; a second pull-up resistor 100b; and a first reference resistor 100c.

[0051] The resistance of the first pull-up resistor 100a changes according to a reference P-code [K-1:0] of K bits applied thereto (where K is a natural number).

[0052] The resistance of the second pull-up resistor 100b connected in parallel with the first pull-up resistor 100a changes according to the reference P-code [K-1:0] of K bits applied thereto. The configuration of the second pull-up resistor 100b is substantially the same as that of the first pull-up resistor 100a.

[0053] The first reference resistor 100c has a constant resistance (e.g., 50) and is connected in series with the first pull-up resistor 100a and the second pull-up resistor 100b connected in parallel.

[0054] The configuration of the first pull-up resistor 100a (or the second pull-up resistor 100b) will be described in detail with reference to FIG. 5.

[0055] FIG. 5 is a circuit diagram illustrating the first pull-up resistor 100a (or the second pull-up resistor 100b) according to the present invention.

[0056] Referring to FIG. 5, the first pull-up resistor 100a includes: K count of PMOS transistors MP.sub.1 to MP.sub.K connected in parallel; a PMOS transistor MP.sub.0; and a resistor R.sub.P.

[0057] The K count of PMOS transistors MP.sub.1 to MP.sub.K are turned on or turned off according to the reference P-code [K-1:0] (abbreviated as REF. P-CODE in FIGS. 5, 9 and 11) applied thereto. That is, the resistance of the first pull-up resistor 100a changes depending on the sum of the channel width (or area) that varies according to the number of PMOS transistors turned on (or turned off) among the K count of PMOS transistors MP.sub.1 to MP.sub.K.

[0058] For example, when 0111, which is a 4-bit reference P-code [3:0], is applied, H (i.e., reference P-code [0]), H (i.e., reference P-code [1]), H (i.e., reference P-code [2]), and L (i.e., reference P-code [3]) are applied to the PMOS transistors MP.sub.1 to MP.sub.4, respectively. As a result, the PMOS transistors MP.sub.1 to MP.sub.4 are turned off, turned off, turned off, and turned on, respectively.

[0059] The resistance of the first pull-up resistor 100a is (MP.sub.1MP.sub.2 . . . MP.sub.(K-1)MP.sub.K)+MP.sub.0+RP. Therefore, it should be understood that the resistance of the first pull-up=resistor 100a changes based on the sum of the channel width (or area) that varies according to the number of the PMOS transistors MP.sub.1 to MP.sub.K that are turned on (or turned off).

[0060] Since the configuration of the second pull-up resistor 100b is the same as that of the first pull-up resistor 100a, the resistance of the second pull-up resistor 100b changes depending on the sum of the channel width (or area) that varies according to the number of the PMOS transistors MP.sub.1 to MP.sub.K that are turned on (or turned off).

[0061] It is preferable that the median of the range of the resistance of the first pull-up resistor 100a be approximately twice the resistance of the first reference resistor 100c. That is, the resistance of the first pull-up resistor 100a varies around twice the resistance of the first reference resistor 100c. The same applies to the second pull-up resistor 100b. Therefore, when the first pull-up resistor 100a and the second pull-up resistor 100b are connected in parallel, their resistance varies around the resistance of the first reference resistor 100c.

[0062] In addition, the resistance of each transistor may be adjusted by properly designing the size of the channel width (or area) of the transistors constituting the first pull-up resistor 100a and the second pull-up resistor 100b, and accordingly, the resistances of the first pull-up resistor 100a and the second pull-up resistor 100b are adjusted. For example, the resistances of the first pull-up resistor 100a and the second pull-up resistor 100b may be designed to increase as the value of the applied reference P-code increases.

[0063] Referring back to FIG. 4, a voltage V.sub.DD is applied to the first voltage divider 100, and the applied voltage V.sub.DD is divided according to the resistances of the first pull-up resistor 100a, the second pull-up resistor 100b, and the first reference resistor 100c.

[0064] For example, when the resistances of the first pull-up resistor 100a, the second pull-up resistor 100b, and the first reference resistor 100c are R.sub.P1, R.sub.P2, and R.sub.REF1, respectively, the voltage V.sub.DIV1 across the first reference resistor 100c is as shown in Equation 1 below.

[00001]$\begin{array}{cc}{V}_{\mathrm{DIV}1}=\frac{R_{\mathrm{REF}1}}{\left(R_{P1}.Math.R_{P2}\right)+R_{\mathrm{REF}1}}{V}_{\mathrm{DD}}& \left[\mathrm{Equation}1\right]\end{array}$

[0065] That is, the voltage V.sub.DIV1 varies depending on the resistance R.sub.P1R.sub.P2 which is the resistance of the first pull-up resistor 100a and the second pull-up resistor 100b connected in parallel. Here, since each of R.sub.P1 and R.sub.P2 vary around 2R.sub.REF1, R.sub.P1R.sub.P2 varies around R.sub.REF1.

[0066] Still referring to FIG. 4, the pull-up code selector 200 applies the reference P-code [K-1:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively.

[0067] The reference P-code [K-1:0] may include a first reference P-code [K-1:0] and a second reference P-code [K-1:0]. Here, the first reference P-code [K-1:0] and the second reference P-code [K-1:0] satisfy the relationship: second reference P-code [K-1:0]=first reference P-code [K-1:0]+1. That is, the second reference P-code [K-1:0] is binary data of K bits that is greater than the first reference P-code [K-1:0] by 1.

[0068] For example, when 4-bit first reference P-code [3:0] is 1000, a second reference P-code [3:0] is 1001.

[0069] The pull-up code selector 200 sequentially applies: the first reference P-code [K-1:0] and the first reference P-code [K-1:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively; the first reference P-code [K-1:0] and the second reference P-code [K-1:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively; and the second reference P-code [K-1:0] and the second reference P-code [K-1:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively.

[0070] For example, the pull-up code selector 200 may apply: 1000 and 1000 to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively, 1000 and 1001 to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively, and 1001 and 1001 to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively. However, the order of application may be changed.

[0071] The resistances of the first pull-up resistor 100a and the second pull-up resistor 100b varies depending on the first reference P-code [K-1:0] and second reference P-code [K-1:0] applied thereto. Therefore, when 1000 and 1000, 1000 and 1001, 1001 and 1001 are applied for example, three different resistances are generated, resulting in three different voltages V.sub.DIV1.

[0072] The first comparator 300 compares the voltage V.sub.DIV1 to 0.5V.sub.DD and provides the resulting comparison value V.sub.COMP1 to the pull-up code selector 200.

[0073] Specifically, as described above, since three different voltages V.sub.DIV1 are generated when the first reference P-code [K-1:0] and the second reference P-code [K-1:0] are applied to the first pull-up resistor 100a and the second pull-up resistor 100b, the first comparator 300 compares each of the three voltages V.sub.DIV1 to 0.5V.sub.DD and provides the three comparison values V.sub.COMP1 to the pull-up code selector 200.

[0074] For example, the first comparator 300 outputs V.sub.COMP1=1 when V.sub.DIV1>0.5V.sub.DD, and outputs V.sub.COMP1=0 when VDIV10.5V.sub.DD.

[0075] The pull-up code selector 200 selects, based on three comparison values V.sub.COMP1, one of the first reference P-code [K-1:0] and the second reference P-code [K-1:0] as a pull-up code [K-1:0] which minimizes the difference between R.sub.P1R.sub.P2 and R.sub.REF1. This process will be described later.

[0076] The second voltage divider 400 includes: a first pull-down resistor 400a; a second pull-down resistor 400b; and a second reference resistor 400c.

[0077] The resistance of the second reference resistor 400c changes according to the pull-up code [K-1:0] applied by the pull-up code selector 200. The second reference resistor 400c is connected in series with the first pull-down resistor 400a and the second pull-down resistor 400b, which are connected in parallel.

[0078] The configuration of the second reference resistor 400c is described in detail with reference to FIG. 6.

[0079] FIG. 6 is a circuit diagram illustrating the second reference resistor 400c according to the present invention.

[0080] Referring to FIG. 6, the second reference resistor 400c according to the present invention includes: K count of PMOS transistors MP.sub.R1 to MP.sub.RK connected in parallel; a PMOS transistor MP.sub.R0; and a resistor R.sub.RP.

[0081] The configuration of the second reference resistor 400c is substantially the same as that of the first pull-up resistor 100a (or the second pull-up resistor 100b) described above. That is, the K count of PMOS transistors MP.sub.R1 to MP.sub.RK are turned on or off according to the pull-up code [K-1:0] applied thereto, and thus the resistance thereof varies. However, the resistance of the second reference resistor 400c varies around the resistance of the first reference resistor 100c.

[0082] The resistance of the first pull-down resistor 400a changes according to the reference N-code [K-1:0] of K bits applied thereto.

[0083] The resistance of the second pull-down resistor 400b connected in parallel with the first pull-down resistor 400a changes according to the reference N-code [K-1:0] of K bits. The configuration of the second pull-down resistor 400b is substantially the same as that of the first pull-down resistor 400a.

[0084] FIG. 7 is a circuit diagram illustrating the first pull-down resistor 400a (or the second pull-down resistor 400b) according to the present invention.

[0085] Referring to FIG. 7, the first pull-down resistor 400a includes: K count of NMOS transistors MN.sub.1 to MN.sub.K connected in parallel, an NMOS transistor MN.sub.0, and a resistor R.sub.N.

[0086] The K count of NMOS transistors MN.sub.1 to MN.sub.K are turned on or turned off according to the reference N-code [K-1:0] (abbreviated as REF. N-CODE in FIGS. 7, 14 and 16) applied thereto. That is, the resistance of the first pull-down resistor 400a changes depending on the sum of the channel width (or area) that varies according to the number of NMOS transistors turned on (or turned off) among the K count of NMOS transistors MN.sub.1 to MN.sub.K.

[0087] For example, when 0111, which is a 4-bit reference N-code [3:0], is applied, H (i.e., reference N-code [0]), H (i.e., reference N-code [1]), H (i.e., reference N-code [2]), and L (i.e., reference N-code [3]) are applied to the NMOS transistors MN.sub.1 to MN.sub.4, respectively. As a result, the NMOS transistors MN.sub.1 to MN.sub.4 are turned on, turned on, turned on, and turned off, respectively.

[0088] The resistance of the first pull-down resistor 400a is (MN.sub.1MN.sub.2 . . . MN.sub.(K-1)MN.sub.K)+MN.sub.0+R.sub.N. Therefore, it should be understood that the resistance of the first pull-down resistor 400a changes based on the sum of the channel width (or area) that varies according to the number of the NMOS transistors MN.sub.1 to MN.sub.K that are turned on (or turned off).

[0089] Since the configuration of the second pull-down resistor 400b is the same as that of the first pull-down resistor 400a, the resistance of the second pull-down resistor 400b changes depending on the sum of the channel width (or area) that varies according to the number of the NMOS transistors MN.sub.1 to MN.sub.K that are turned on (or turned off).

[0090] It is preferable that the median of the range of the resistance of the first pull-down resistor 400a be approximately twice the resistance of the second reference resistor 400c. That is, the resistance of the first pull-down resistor 400a varies around twice the resistance of the second reference resistor 400c. The same applies to the second pull-down resistor 400b. Therefore, when the first pull-down resistor 400a and the second pull-down resistor 400b are connected in parallel, their resistance varies around the resistance of the second reference resistor 400c.

[0091] In addition, the resistance of each transistor may be adjusted by properly designing the size of the channel width (or area) of the transistors constituting the first pull-down resistor 400a and the second pull-down resistor 400b, and accordingly, the resistances of the first pull-down resistor 400a and the second pull-down resistor 400b are adjusted. For example, the resistances of the first pull-down resistor 400a and the second pull-down resistor 400b may be designed to decrease as the value of the applied reference N-code increases.

[0092] Referring back to FIG. 4, a voltage V.sub.DD is applied to the second voltage divider 400, and the applied voltage V.sub.DD is divided according to the resistances of the second reference resistor 400c, the first pull-down resistor 400a, and the second pull-down resistor 400b.

[0093] For example, when the resistances of the second reference resistor 400c, the first pull-down resistor 400a, and the second pull-down resistor 400b are R.sub.REF2, R.sub.N1, and R.sub.N2, respectively, the voltage V.sub.DIV2 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel is as shown in Equation 2 below.

[00002]$\begin{array}{cc}{V}_{\mathrm{DIV}2}=\frac{\left(R_{N1}.Math.R_{N2}\right)}{\left(R_{N1}.Math.R_{N2}\right)+R_{\mathrm{REF}2}}{V}_{\mathrm{DD}}& \left[\mathrm{Equation}2\right]\end{array}$

[0094] That is, the voltage V.sub.DIV2 varies depending on the resistance R.sub.N1R.sub.N2 which is the resistance of the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel. Here, since each of R.sub.N1 and R.sub.N2 vary around 2R.sub.REF2, R.sub.N1R.sub.N2 varies around R.sub.REF2.

[0095] Still referring to FIG. 4, the pull-down code selector 500 applies the reference N-code [K-1:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively.

[0096] The reference N-code [K-1:0] may include a first reference N-code [K-1:0] and a second reference N-code [K-1:0]. Here, the first reference N-code [K-1:0] and the second reference N-code [K-1:0] satisfy the relationship: second reference N-code [K-1:0]=first reference N-code [K-1:0]+1. That is, the second reference N-code [K-1:0] is binary data of K bits that is greater than the first reference N-code [K-1:0] by 1.

[0097] For example, when 4-bit first reference N-code [3:0] is 0111, a second reference N-code [3:0] is 1000.

[0098] The pull-down code selector 500 sequentially applies: the first reference N-code [K-1:0] and the first reference N-code [K-1:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively; the first reference N-code [K-1:0] and the second reference N-code [K-1:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively; and the second reference N-code [K-1:0] and the second reference N-code [K-1:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively.

[0099] For example, the pull-down code selector 500 may apply: 0111 and 0111 to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively, 0111 and 1000 to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively, and 1000 and 1000 to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively. However, the order of application may be changed.

[0100] The resistances of the first pull-down resistor 400a and the second pull-down resistor 400b varies depending on the first reference N-code [K-1:0] and second reference N-code [K-1:0] applied thereto. Therefore, when 0111 and 0111, 0111 and 1000, 1000 and 1000 are applied for example, three different resistances are generated, resulting in three different voltages V.sub.DIV2.

[0101] The second comparator 600 compares the voltage V.sub.DIV2 to 0.5V.sub.DD and provides the resulting comparison value V.sub.COMP2 to the pull-down code selector 500.

[0102] Specifically, as described above, since three different voltages V.sub.DIV2 are generated when the first reference N-code [K-1:0] and the second reference N-code [K-1:0] are applied to the first pull-down resistor 400a and the second pull-down resistor 400b, the second comparator 600 compares each of the three voltages V.sub.DIV2 to 0.5V.sub.DD and provides the three comparison values V.sub.COMP2 to the pull-down code selector 500.

[0103] For example, the second comparator 600 outputs V.sub.COMP2=1 when V.sub.DIV2>0.5V.sub.DD, and outputs V.sub.COMP2=0 when V.sub.DIV20.5V.sub.DD.

[0104] The pull-down code selector 500 selects, based on three comparison values V.sub.COMP2, one of the first reference N-code [K-1:0] and the second reference N-code [K-1:0] as a pull-down code [K-1:0] which minimizes the difference between R.sub.N1R.sub.N2 and R.sub.REF2. This process will be described later.

[0105] Hereinafter, the operation of the circuit capable of automatically adjusting impedance thereof according to the present invention will be described in detail with reference to FIGS. 8A to 16.

[0106] First, in order to describe the pull-up code selection process of the pull-up code selector 200, it is assumed that K=4, the resistance R.sub.REF1 of the first reference resistor 100c is 50, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 94 when the first reference P-code [3:0] (=X.sub.1) is applied thereto, and the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 102 when the second reference P-code [3:0] (=X.sub.1+1) is applied.

[0107] FIGS. 8A to 8C are circuit diagrams illustrating the first pull-up resistor 100a and the second pull-up resistor 100b, respectively, when the first reference P-code [3:0] (=X.sub.1) and the second reference P-code [3:0] (=X.sub.1+1) are applied according to the present invention.

[0108] First, referring to FIG. 8A, the first reference P-code [3:0] (=X.sub.1) is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b.

[0109] When X.sub.1 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 94. Thus, R.sub.P1R.sub.P2=47.

[0110] Here, the voltage V.sub.DIV11 across the first reference resistor 100c may be calculated from Equation 1 as shown in Equation 3 below.

[00003]$\begin{array}{cc}{V}_{\mathrm{DIV}11}=\frac{R_{\mathrm{REF}1}}{\left(R_{P1}.Math.R_{P2}\right)+R_{\mathrm{REF}1}}{V}_{\mathrm{DD}}=\frac{50}{47+50}{V}_{\mathrm{DD}}0.515V_{\mathrm{DD}}& \left[\mathrm{Equation}3\right]\end{array}$

[0111] Next, referring to FIG. 8B, the first reference P-code [3:0] (=X.sub.1) and the second reference P-code [3:0] (=X.sub.1+1) are applied to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively.

[0112] When X.sub.1 and X.sub.1+1 are applied to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are 94 and 102, respectively. Thus, R.sub.P1R.sub.P249.

[0113] Here, the voltage V.sub.DIV12 across the first reference resistor 100c may be calculated from Equation 1 as shown in Equation 4 below.

[00004]$\begin{array}{cc}{V}_{\mathrm{DIV}12}=\frac{R_{\mathrm{REF}1}}{\left(R_{P1}.Math.R_{P2}\right)+R_{\mathrm{REF}1}}{V}_{\mathrm{DD}}=\frac{50}{49+50}{V}_{\mathrm{DD}}0.505V_{\mathrm{DD}}& \left[\mathrm{Equation}4\right]\end{array}$

[0114] Next, referring to FIG. 8C, the second reference P-code [3:0] (=X.sub.1+1) is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b.

[0115] When X.sub.1+1 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 102. Thus, R.sub.P1R.sub.P2=51.

[0116] Here, the voltage V.sub.DIV13 across the first reference resistor 100c may be calculated from Equation 1 as shown in Equation 5 below.

[00005]$\begin{array}{cc}{V}_{\mathrm{DIV}13}=\frac{R_{\mathrm{REF}1}}{\left(R_{P1}.Math.R_{P2}\right)+R_{\mathrm{REF}1}}{V}_{DD}=\frac{50}{51+50}{V}_{DD}0.495V_{DD}& \left[\mathrm{Equation}5\right]\end{array}$

[0117] The first comparator 300 sequentially compares voltages V.sub.DIV11, V.sub.DIV12 and V.sub.DIV13 to 0.5V.sub.DD and outputs the comparison value V.sub.COMP1 for each of the voltages V.sub.DIV11, V.sub.DIV12 and V.sub.DIV13.

[0118] The comparison values outputted by the first comparator 300 are: V.sub.COMP11=1 (0.515V.sub.DD>0.5V.sub.DD); V.sub.COMP12=1 (0.505V.sub.DD>0.5V.sub.DD); and V.sub.COMP13=0 (0.495V.sub.DD<0.5V.sub.DD) where the first comparison value V.sub.COMP11, the second comparison value V.sub.COMP12 and the third comparison value V.sub.COMP13 represent the comparison results for the voltages V.sub.DIV11, V.sub.DIV12 and V.sub.DIV13, respectively.

[0119] This change (1.fwdarw.1.fwdarw.0) of the first comparison value V.sub.COMP11, the second comparison value V.sub.COMP12 and the third comparison value V.sub.COMP13 represents that R.sub.P1R.sub.P2 increases as the applied reference P-code increases, as shown in FIG. 9, and in particular, when X.sub.1+1 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, R.sub.P1R.sub.P2 is then greater than 50, which is the resistance R.sub.REF1 of the first reference resistor 100c.

[0120] That is, as shown in FIG. 9, when X.sub.1+1 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, the difference D.sub.1 between the resistance R.sub.P1R.sub.P2 and the resistance R.sub.REF1 of the first reference resistor 100c is minimum (D.sub.0<D.sub.1).

[0121] Therefore, the pull-up code selector 200 selects the second reference P-code [3:0] (=X.sub.1+1) as the pull-up code [3:0], and applies the selected pull-up code [3:0] to the second reference resistor 400c shown in FIG. 12.

[0122] Next, to describe the pull-up code selection process of the pull-up code selector 200 for another reference P-code, it is assumed that K=4, the resistance R.sub.REF1 of the first reference resistor 100c is 50, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 98 when the first reference P-code [3:0] (=X.sub.2) is applied thereto, and the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 106 when the second reference P-code [3:0] (=X.sub.2+1) is applied.

[0123] FIGS. 10A to 10C are circuit diagrams illustrating the first pull-up resistor 100a and the second pull-up resistor 100b when the first reference P-code [3:0] (=X.sub.2) and the second reference P-code [3:0] (=X.sub.2+1) are applied according to the present invention.

[0124] First, referring to FIG. 10A, the first reference P-code [3:0] (=X.sub.2) is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b.

[0125] When X.sub.2 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 98. Thus, R.sub.P1RP2=49.

[0126] Here, the voltage V.sub.DIV11 across the first reference resistor 100c may be calculated from Equation 1 as shown in Equation 6 below.

[00006]$\begin{array}{cc}{V}_{\mathrm{DIV}11}=\frac{R_{\mathrm{REF}1}}{\left(R_{P1}.Math.R_{P2}\right)+R_{\mathrm{REF}1}}{V}_{DD}=\frac{50}{49+50}{V}_{DD}0.505V_{DD}& \left[\mathrm{Equation}6\right]\end{array}$

[0127] Next, referring to FIG. 10B, the first reference P-code [3:0] (=X.sub.2) and the second reference P-code [3:0] (=X.sub.2+1) are applied to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively.

[0128] When X.sub.2 and X.sub.2+1 are applied to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are 98 and 106, respectively. Thus, R.sub.P1R.sub.P251.

[0129] Here, the voltage V.sub.DIV12 across the first reference resistor 100c may be calculated from Equation 1 as shown in Equation 7 below.

[00007]$\begin{array}{cc}{V}_{\mathrm{DIV}12}=\frac{R_{\mathrm{REF}1}}{\left(R_{P1}.Math.R_{P2}\right)+R_{\mathrm{REF}1}}{V}_{DD}=\frac{50}{51+50}{V}_{DD}0.495V_{DD}& \left[\mathrm{Equation}7\right]\end{array}$

[0130] Next, referring to FIG. 10C, the second reference P-code [3:0] (=X.sub.2+1) is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b.

[0131] When X.sub.2+1 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, the resistance R.sub.P1 of the first pull-up resistor 100a and the resistance R.sub.P2 of the second pull-up resistor 100b are both 106. Thus, R.sub.P1R.sub.P2=53.

[0132] Here, the voltage V.sub.DIV13 across the first reference resistor 100c may be calculated from Equation 1 as shown in Equation 8 below.

[00008]$\begin{array}{cc}{V}_{\mathrm{DIV}13}=\frac{R_{\mathrm{REF}1}}{\left(R_{P1}.Math.R_{P2}\right)+R_{\mathrm{REF}1}}{V}_{DD}=\frac{50}{53+50}{V}_{DD}0.485V_{DD}& \left[\mathrm{Equation}8\right]\end{array}$

[0133] The first comparator 300 sequentially compares voltages V.sub.DIV11, V.sub.DIV12 and V.sub.DIV13 to 0.5V.sub.DD and outputs the comparison value V.sub.COMP1 for each of the voltages V.sub.DIV11, V.sub.DIV12 and V.sub.DIV13.

[0134] The comparison values outputted by the first comparator 300 are: V.sub.COMP11=1 (0.505V.sub.DD>0.5V.sub.DD); V.sub.COMP12=0 (0.495V.sub.DD<0.5V.sub.DD); and V.sub.COMP13=0 (0.485V.sub.DD<0.5V.sub.DD) where the first comparison value V.sub.COMP11, the second comparison value V.sub.COMP12 and the third comparison value V.sub.COMP13 represent the comparison results for the voltages V.sub.DIV11, V.sub.DIV12 and V.sub.DIV13, respectively.

[0135] This change (1.fwdarw.0.fwdarw.0) of the first comparison value V.sub.COMP11, the second comparison value V.sub.COMP12 and the third comparison value V.sub.COMP13 represents that R.sub.P1R.sub.P2 increases as the applied reference P-code increases, as shown in FIG. 11, and in particular, when X.sub.2 and X.sub.2+1 are applied to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively, R.sub.P1R.sub.P2 is already greater than 50, which is the resistance R.sub.REF1 of the first reference resistor 100c, and when X.sub.2+1 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, R.sub.P1R.sub.P2 is much greater than the resistance R.sub.REF1 of 50 of the first reference resistor 100c.

[0136] That is, as shown in FIG. 11, when X.sub.2 is applied to each of the first pull-up resistor 100a and the second pull-up resistor 100b, the difference Do between the resistance R.sub.P1R.sub.P2 and the resistance R.sub.REF1 of the first reference resistor 100c is minimum (D.sub.0<D.sub.1).

[0137] Therefore, the pull-up code selector 200 selects the first reference P-code [3:0] (=X.sub.2) as the pull-up code [3:0], and applies the selected pull-up code [3:0] to the second reference resistor 400c shown in FIG. 12.

[0138] The pull-up code [3:0] applied to the second reference resistor 400c is a reference P-code which minimizes the difference between the resistance R.sub.REF2 of the second reference resistor 400c and the resistance R.sub.REF1 (=50).

[0139] In the above-described pull-up code selection process, the first comparison value V.sub.COMP11, the second comparison value V.sub.COMP12 and the third comparison value V.sub.COMP13 may have values different from those described above, which will be explained below.

[0140] In the above-described pull-up code selection process, the comparison results may be V.sub.COMP11=1, V.sub.COMP12=1, and V.sub.COMP13=1. This means V.sub.DIV11>0.5V.sub.DD, V.sub.DIV12>0.5V.sub.DD, and V.sub.DIV13>0.5V.sub.DD, respectively. That is, the voltage V.sub.DIV1 across the first reference resistor 100c in each comparison is greater than 0.5V.sub.DD. In such case, it is not possible to determine the pull-up code which minimizes the difference between the resistance R.sub.P1R.sub.P2 and the resistance R.sub.REF1 of the first reference resistor 100c.

[0141] Therefore, the resistance R.sub.P1R.sub.P2 should be increased or decreased by appropriately adjusting the first reference P-code [3:0] and the second reference P-code [3:0]. In order to make any one of the first comparison value V.sub.COMP11, the second comparison value V.sub.COMP12, and the third comparison value V.sub.COMP13 zero, the resistance R.sub.P1R.sub.P2 in Equation 1 should be increased. As the first reference P-code [3:0] and the second reference P-code [3:0] increase, the resistance R.sub.P1R.sub.P2 increases. Thus, the pull-up code selector 200 increases each of the first reference P-code [3:0] and the second reference P-code [3:0] by 1, and sequentially applies the increased first reference P-code [3:0] and the increased second reference P-code [3:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, and perform the above-described process again with the newly obtained first comparison value V.sub.COMP11, the newly obtained second comparison value V.sub.COMP12, and the newly obtained third comparison value V.sub.COMP13.

[0142] Similarly, when the comparison results are V.sub.COMP11=0, V.sub.COMP12=0, and V.sub.COMP13=0, each of the first reference P-code [3:0] and the second reference P-code [3:0] are decreased by 1 to decrease the resistanceR.sub.P1R.sub.P2, and the above process is performed again with the first comparison value V.sub.COMP11, the second comparison value V.sub.COMP12, and the third comparison value V.sub.COMP13 newly obtained from the decreased first reference P-code [3:0] and the decreased second reference P-code [3:0].

[0143] The pull-up code selection process of the pull-up code selector 200 described above is summarized in Table 1 below.

TABLE-US-00001 TABLE 1 V.sub.COMP11 V.sub.COMP12 V.sub.COMP13 Pull-up code 1 1 0 Second reference P-code 1 0 0 First reference P-code 1 1 1 Increase first and second reference P-codes by 1 0 0 0 Decrease first and second reference P-codes by 1 0 0 1 Non-existent comparison values 0 1 1 1 0 1 0 1 0

[0144] Hereinafter, the pull-down code selection process of the pull-down code selector 500 is described when the pull-up code [3:0], which minimizes the difference between the resistance R.sub.REF2 of the second reference resistor 400c and the resistance R.sub.REF1 (=50), is applied to the second reference resistor 400c.

[0145] Except that the second reference resistor 400c having the resistance determined by the pull-up code [3:0] is employed instead of the first reference resistor 100c having a constant resistance, the pull-down code selection process of the pull-down code selector 500 is substantially the same as that of the pull-up code selector 200.

[0146] First, in order to describe the pull-down code selection process of the pull-down code selector 500, it is assumed that K=4, the resistance R.sub.REF2 of the second reference resistor 400c is 50 when pull-up code [3:0] (=X.sub.1+1) is applied, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 102 when the first reference N-code [3:0] (=Y.sub.1) is applied thereto, and the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 94 when the second reference N-code [3:0] (=Y.sub.1+1) is applied.

[0147] FIGS. 13A to 13C are circuit diagrams illustrating the first pull-down resistor 400a and the second pull-down resistor 400b, respectively, when the first reference N-code [3:0] (=Y.sub.1) and the second reference N-code [3:0] (=Y.sub.1+1) are applied according to the present invention.

[0148] First, referring to FIG. 13A, the first reference N-code [3:0] (=Y.sub.1) is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b.

[0149] When Y.sub.1 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 102. Thus, R.sub.N1R.sub.N2=51.

[0150] Here, the voltage V.sub.DIV21 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel may be calculated from Equation 2 as shown in Equation 9 below.

[00009]$\begin{array}{cc}{V}_{\mathrm{DIV}21}=\frac{\left(R_{N1}.Math.R_{N2}\right)}{\left(R_{N1}.Math.R_{N2}\right)+R_{\mathrm{REF}2}}{V}_{DD}=\frac{51}{51+50}{V}_{DD}0.505V_{DD}& \left[\mathrm{Equation}9\right]\end{array}$

[0151] Next, referring to FIG. 13B, the first reference N-code [3:0] (=Y.sub.1) and the second reference N-code [3:0] (=Y.sub.1+1) are applied to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively.

[0152] When Y.sub.1 and Y.sub.1+1 are applied to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are 102 and 94, respectively. Thus, R.sub.N1R.sub.N249.

[0153] Here, the voltage V.sub.DIV22 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel may be calculated from Equation 2 as shown in Equation 10 below.

[00010]$\begin{array}{cc}{V}_{\mathrm{DIV}22}=\frac{\left(R_{N1}.Math.R_{N2}\right)}{\left(R_{N1}.Math.R_{N2}\right)+R_{\mathrm{REF}2}}{V}_{DD}=\frac{49}{49+50}{V}_{DD}0.495V_{DD}& \left[\mathrm{Equation}10\right]\end{array}$

[0154] Next, referring to FIG. 13C, the second reference N-code [3:0] (=Y.sub.1+1) is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b.

[0155] When Y.sub.1+1 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 94. Thus, R.sub.N1R.sub.N2=47.

[0156] Here, the voltage V.sub.DIV23 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel may be calculated from Equation 2 as shown in Equation 11 below.

[00011]$\begin{array}{cc}{V}_{\mathrm{DIV}23}=\frac{\left(R_{N1}.Math.R_{N2}\right)}{\left(R_{N1}.Math.R_{N2}\right)+R_{\mathrm{REF}2}}{V}_{DD}=\frac{47}{47+50}{V}_{DD}0.485V_{DD}& \left[\mathrm{Equation}11\right]\end{array}$

[0157] The second comparator 600 sequentially compares voltages V.sub.DIV21, V.sub.DIV22 and V.sub.DIV23 to 0.5V.sub.DD and outputs the comparison value V.sub.COMP2 for each of the voltages V.sub.DIV21, V.sub.DIV22 and V.sub.DIV23.

[0158] The comparison values outputted by the second comparator 600 are: V.sub.COMP21=1 (0.505V.sub.DD>0.5V.sub.DD); V.sub.COMP22=0 (0.495V.sub.DD<0.5V.sub.DD); and V.sub.COMP23=0 (0.485V.sub.DD<0.5V.sub.DD) where first comparison value V.sub.COMP21, second comparison value V.sub.COMP22 and third comparison value V.sub.COMP23 represent the comparison results for the voltages V.sub.DIV21, V.sub.DIV22 and V.sub.DIV23, respectively.

[0159] This change (1.fwdarw.0.fwdarw.0) of the first comparison value V.sub.COMP21, the second comparison value V.sub.COMP22 and the third comparison value V.sub.COMP23 represents that R.sub.N1R.sub.N2 decreases as the applied reference N-code increases, as shown in FIG. 14, and in particular, when Y.sub.1 and Y.sub.1+1 are applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, respectively, R.sub.N1R.sub.N2 is smaller than 50, which is the resistance R.sub.REF2 of the second reference resistor 400c, and when Y.sub.1+1 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, R.sub.N1R.sub.N2 is much smaller than 50, which is the resistance R.sub.REF2 of the second reference resistor 400c.

[0160] That is, as shown in FIG. 14, when Y.sub.1 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, the difference Do between the resistance R.sub.N1R.sub.N2 and the resistance R.sub.REF2 of the second reference resistor 400c is minimum (D.sub.0<D.sub.1). Therefore, the pull-down code selector 500 selects the first reference N-code [3:0] (=Y.sub.1) as the pull-down code [3:0].

[0161] Next, to describe the pull-down code selection process of the pull-down code selector 500 for another reference N-code, it is assumed that K=4, the resistance R.sub.REF2 of the second reference resistor 400c is 50, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 106 when the first reference N-code [3:0] (=Y.sub.2) is applied thereto, and the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 98 when the second reference N-code [3:0] (=Y.sub.2+1) is applied.

[0162] FIGS. 15A to 15C are circuit diagrams illustrating the first pull-down resistor 400a and the second pull-down resistor 400b when the first reference N-code [3:0] (=Y.sub.2) and the second reference N-code [3:0] (=Y.sub.2+1) are applied according to the present invention.

[0163] First, referring to FIG. 15A, the first reference N-code [3:0] (=Y.sub.2) is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b.

[0164] When Y.sub.2 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 106. Thus, R.sub.N1R.sub.N2=53.

[0165] Here, the voltage V.sub.DIV21 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel may be calculated from Equation 2 as shown in Equation 12 below.

[00012]$\begin{array}{cc}{V}_{\mathrm{DIV}21}=\frac{\left(R_{N1}.Math.R_{N2}\right)}{\left(R_{N1}.Math.R_{N2}\right)+R_{\mathrm{REF}2}}{V}_{DD}=\frac{53}{53+50}{V}_{DD}0.515V_{DD}& \left[\mathrm{Equation}12\right]\end{array}$

[0166] Next, referring to FIG. 15B, the first reference N-code [3:0] (=Y.sub.2) and the second reference N-code [3:0] (=Y.sub.2+1) are applied to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively.

[0167] When Y.sub.2 and Y.sub.2+1 are applied to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are 106 and 98, respectively. Thus, R.sub.N1R.sub.N251.

[0168] Here, the voltage V.sub.DIV22 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel may be calculated from Equation 2 as shown in Equation 13 below.

[00013]$\begin{array}{cc}{V}_{\mathrm{DIV}22}=\frac{\left(R_{N1}.Math.R_{N2}\right)}{\left(R_{N1}.Math.R_{N2}\right)+R_{\mathrm{REF}2}}{V}_{DD}=\frac{51}{51+50}{V}_{DD}0.505V_{DD}& \left[\mathrm{Equation}13\right]\end{array}$

[0169] Next, referring to FIG. 15C, the second reference N-code [3:0] (=Y.sub.2+1) is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b.

[0170] When Y.sub.2+1 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, the resistance R.sub.N1 of the first pull-down resistor 400a and the resistance R.sub.N2 of the second pull-down resistor 400b are both 98. Thus, R.sub.N1R.sub.N2=49.

[0171] Here, the voltage V.sub.DIV23 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel may be calculated from Equation 2 as shown in Equation 14 below.

[00014]$\begin{array}{cc}{V}_{\mathrm{DIV}23}=\frac{\left(R_{N1}.Math.R_{N2}\right)}{\left(R_{N1}.Math.R_{N2}\right)+R_{\mathrm{REF}2}}{V}_{DD}=\frac{49}{49+50}{V}_{DD}0.495V_{DD}& \left[\mathrm{Equation}14\right]\end{array}$

[0172] The second comparator 600 sequentially compares voltages V.sub.DIV21, V.sub.DIV22 and V.sub.DIV23 to 0.5V.sub.DD and outputs the comparison value V.sub.COMP2 for each of the voltages V.sub.DIV21, V.sub.DIV22 and V.sub.DIV23.

[0173] The comparison values outputted by the second comparator 600 are: V.sub.COMP21=1 (0.515V.sub.DD>0.5V.sub.DD); V.sub.COMP22=1 (0.505V.sub.DD>0.5V.sub.DD); and V.sub.COMP23=0 (0.495V.sub.DD<0.5V.sub.DD) where first comparison value V.sub.COMP21, second comparison value V.sub.COMP22 and third comparison value V.sub.COMP23 represent the comparison values for the voltages V.sub.DIV21, V.sub.DIV22 and V.sub.DIV23, respectively.

[0174] This change (1.fwdarw.1.fwdarw.0) of the first comparison value V.sub.COMP21, the second comparison value V.sub.COMP22 and third comparison value V.sub.COMP23 represents that R.sub.N1R.sub.N2 decreases as the applied reference N-code increases, as shown in FIG. 16, and in particular, when Y.sub.2+1 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, R.sub.N1R.sub.N2 is then smaller than 50, which is the resistance R.sub.REF2 of the second reference resistor 400c.

[0175] That is, as shown in FIG. 16, when Y.sub.2+1 is applied to each of the first pull-down resistor 400a and the second pull-down resistor 400b, the difference D.sub.1 between the resistance R.sub.N1R.sub.N2 and the resistance R.sub.REF2 of the second reference resistor 400c is minimum (D.sub.0>D.sub.1). Therefore, the pull-down code selector 500 selects the first reference N-code [3:0] (=Y.sub.2) as the pull-down code [3:0].

[0176] In the above-described pull-down code selection process, the first comparison value V.sub.COMP21, the second comparison value V.sub.COMP22 and the third comparison value V.sub.COMP23 may have values different from those described above, which will be explained below.

[0177] In the above-described pull-down code selection process, the comparison results may be V.sub.COMP21=1, V.sub.COMP22=1, and V.sub.COMP23=1. This means V.sub.DIV21>0.5V.sub.DD, V.sub.DIV22>0.5V.sub.DD, and V.sub.DIV23>0.5V.sub.DD, respectively. That is, the voltage V.sub.DIV2 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel in each comparison is greater than 0.5V.sub.DD. In such case, it is not possible to determine the pull-down code which minimizes the difference between the resistance R.sub.N1R.sub.N2 and the resistance R.sub.REF2 of the second reference resistor 400c.

[0178] Therefore, the resistance R.sub.N1R.sub.N2 should be increased or decreased by appropriately adjusting the first reference N-code [3:0] and the second reference N-code [3:0]. In order to make any one of the first comparison value V.sub.COMP21, the second comparison value V.sub.COMP22, and the third comparison value V.sub.COMP23 zero, the resistance R.sub.N1R.sub.N2 in Equation 2 should be decreased. As the first reference N-code [3:0] and the second reference N-code [3:0] increase, the resistance R.sub.N1R.sub.N2 decreases. Thus, the pull-down code selector 500 increases each of the first reference N-code [3:0] and the second reference N-code [3:0] by 1, and sequentially applies the increased first reference N-code [3:0] and the increased second reference N-code [3:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, and perform the above-described process again with the newly obtained first comparison value V.sub.COMP21, the newly obtained second comparison value V.sub.COMP22, and the newly obtained third comparison value V.sub.COMP23.

[0179] Similarly, when the comparison results are V.sub.COMP21=0, V.sub.COMP22=0, and V.sub.COMP2=0, each of the first reference N-code [3:0] and the second reference N-code [3:0] are decreased by 1 to increase the resistance R.sub.N1R.sub.N2, and the above process is performed again with the first comparison value V.sub.COMP21, the second comparison value V.sub.COMP22, and the third comparison value V.sub.COMP23 newly obtained from the decreased first reference N-code [3:0] and the decreased second reference N-code [3:0].

[0180] The pull-down code selection process of the pull-down code selector 500 described above is summarized in Table 2 below.

TABLE-US-00002 TABLE 2 V.sub.COMP21 V.sub.COMP22 V.sub.COMP23 Pull-down code 1 1 0 Second reference N-code 1 0 0 First reference N-code 1 1 1 Increase first and second reference N-codes by 1 0 0 0 Decrease first and second reference N-codes by 1 0 0 1 Non-existent comparison values 0 1 1 1 0 1 0 1 0

[0181] FIG. 17 is a circuit diagram illustrating a circuit capable of automatically adjusting impedance thereof according to a second embodiment of the present invention.

[0182] Referring to FIG. 17, a circuit 2000 capable of automatically adjusting impedance thereof according to the second embodiment of the present invention includes: a first voltage divider 400; a pull-down code selector 500; a first comparator 600; a second voltage divider 100; a pull-up code selector 200; and a second comparator 300.

[0183] The first voltage divider 400, the pull-down code selector 500, the first comparator 600, the second voltage divider 100, the pull-up code selector 200 and the second comparator 300 constituting the circuit 2000 capable of automatically adjusting impedance thereof according to the second embodiment of the present invention are identical in operation and function to the second voltage divider 400, the pull-down code selector 500, the second comparator 600, the first voltage divider 100, the pull-up code selector 200 and the first comparator 300 constituting the circuit 1000 capable of automatically adjusting impedance thereof according to the first embodiment, respectively.

[0184] However, the circuit 2000 capable of automatically adjusting impedance thereof according to the second embodiment differs from the circuit 1000 capable of automatically adjusting impedance thereof according to the first embodiment in that the pull-down code is determined first and then the pull-up code is determined, and the resistance of the second reference resistor 400c is constant, while the resistance of the second reference resistor 100c is determined by the pull-down code determined by the pull-down code selector 500.

[0185] That is, the first voltage divider 400 according to the second embodiment of the present invention includes: a first pull-down resistor 400a and a second pull-down resistor 400b connected in parallel and having resistances, respectively, varying according to a reference N-code [K-1:0] applied thereto; and a first reference resistor 400c having a constant resistance and connected in series with the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel, the pull-down code selector 500 according to the second embodiment of the present invention sequentially applies: a first reference N-code [K-1:0] and the first reference N-code [K-1:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively; the first reference N-code [K-1:0] and a second reference N-code [K-1:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively; and the second reference N-code [K-1:0] and the second reference N-code [K-1:0] to the first pull-down resistor 400a and the second pull-down resistor 400b, respectively, the first comparator 600 according to the second embodiment of the present invention provides a comparison value V.sub.COMP1 to the pull-down code selector 500 wherein the comparison value V.sub.COMP1 is obtained by comparing 0.5V.sub.DD to a voltage V.sub.DIV1 across the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel when a voltage V.sub.DD is applied to the first voltage divider 400, the second voltage divider 100 according to the second embodiment of the present invention includes: a second reference resistor 100c having a resistance varying according to a pull-down code applied by the pull-down code selector 500; and a first pull-up resistor 100a and a second pull-up resistor 100b connected in parallel and having resistances, respectively, varying according to a reference P-code [K-1:0] applied thereto wherein the first pull-up resistor 100a and the second pull-up resistor 100b are connected in series with the second reference resistor 100c, the pull-up code selector 200 according to the second embodiment of the present invention sequentially applies: a first reference P-code [K-1:0] and the first reference P-code [K-1:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively; the first reference P-code [K-1:0] and a second reference P-code [K-1:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively; and the second reference P-code [K-1:0] and the second reference P-code [K-1:0] to the first pull-up resistor 100a and the second pull-up resistor 100b, respectively; and the second comparator 300 according to the second embodiment of the present invention provides a comparison value V.sub.COMP2 to the pull-up code selector 200 wherein the comparison value V.sub.COMP2 is obtained by comparing 0.5V.sub.DD to a voltage V.sub.DIV2 across the second reference resistor 100c when the voltage V.sub.DD is applied to the second voltage divider 100.

[0186] In addition, the first comparator 600 according to the second embodiment of the present invention performs a comparison each time the reference N-code [K-1:0] is applied and provides three comparison values V.sub.COMP1 to the pull-down code selector 500, the pull-down code selector 500 selects one of the first reference N-code [K-1:0] and the second reference N-code [K-1:0] as a pull-down code based on the three comparison values V.sub.COMP1, the pull-down code minimizing a difference between: a resistance of the first reference resistor 400c; and a resistance of the first pull-down resistor 400a and the second pull-down resistor 400b connected in parallel, the second comparator 300 performs a comparison each time the reference P-code [K-1:0] is applied and provides three comparison values V.sub.COMP2 to the pull-up code selector 200, and the pull-up code selector 200 selects one of the first reference P-code [K-1:0] and the second reference P-code [K-1:0] as a pull-up code based on the three comparison values V.sub.COMP2, the pull-up code minimizing the difference between: a resistance of the second reference resistor 100c; and a resistance of the first pull-up resistor 100a and the second pull-up resistor 100b connected in parallel (where second reference N-code [K-1:0] is equal to first reference N-code [K-1:0]+1, and second reference P-code [K-1:0] is equal to first reference P-code [K-1:0]+1).

[0187] The circuit capable of automatically adjusting impedance thereof according to the present invention has the following advantages. [0188] (1) The circuit capable of automatically adjusting impedance thereof according to the present invention is advantageous in that large PVT changes may be dealt with due to the wide adjustment range of impedance. [0189] (2) The circuit capable of automatically adjusting impedance thereof according to the present invention is advantageous in that internal resistance may be adjusted as closely as possible to the resistance of an external reference resistor with high accuracy.