AUTONOMOUS CONTROL BOARD

Abstract

An external control FPGA device includes a command receiving terminal configured to receive command data, a control outputting terminal configured to output a functioning control signal, and a plurality of FPGA connection terminals, and a data processing FPGA device that transmits a control command from an external command data receiver to a control signal outputter. The data processing FPGA device is connected to one of the plurality of FPGA connection terminals through a data processing line that is independent of a command transmission pathway including an external command data receiver, a command data line, the external control FPGA device, a functioning control signal line and the control signal outputter. The data processing FPGA device inputs data that is to be processed from the external control FPGA device through the data processing line, and outputs the processed data to the external control FPGA device.

Claims

1. An autonomous control board for an autonomous functioning apparatus, the autonomous functioning apparatus autonomously performing a series of operations based on command data transmitted from a command device that is either on-board or off-board with respect to the autonomous functioning apparatus, the autonomous functioning apparatus including an external environment sensor obtaining information of external environment of the autonomous functioning apparatus, and an on-board controlled object that is disposed outside the autonomous control board and is different from the command device, the autonomous control board comprising: an external command data receiver configured to obtain the command data transmitted from the command device for commanding at least an initiation of the series of operations; an external environment data obtainer communicatively connected to the external environment sensor, and being configured to obtain external environment data outputted from the external environment sensor; a control signal outputter communicatively connected to the on-board controlled object, and being configured to send a functioning control signal to the on-board controlled object, to thereby control the on-board controlled object; and a functioning control signal generation circuit configured to generate the functioning control signal based on the command data, the functioning control signal generation circuit comprising: an external control field-programmable gate array (FPGA) device including a first logic circuit that is programmable, and a processor; at least one data processing FPGA device, each including a second logic circuit that is programmable; a command data line configured to transmit the command data from the external command data receiver to the external control FPGA device; and a functioning control signal line configured to transmit the functioning control signal from the external control FPGA device to the control signal outputter, wherein the external control FPGA device further includes a command receiving terminal connected to the external command data receiver through the command data line, the command receiving terminal being configured to receive the command data from the command device when the command device is off-board with respect to the autonomous functioning apparatus, a control outputting terminal connected to the control signal outputter, the control outputting terminal being configured to output the functioning control signal for controlling the on-board controlled object, and at least one FPGA connection terminal that is communicatively connected to the at least one data processing FPGA device; wherein the external command data receiver, the command data line, the external control FPGA device, the functioning control signal line, and the control signal outputter form a command transmission pathway for transmitting a control command between the external command data receiver and the control signal outputter, the control command being either the command data or the functioning control signal, and each of the at least one data processing FPGA device is one-to-one connected to one of the at least one FPGA connection terminals through a data processing line that is independent of the command transmission pathway, to thereby receive data that is to be processed from the external control FPGA device, and to thereby output processed data to the external control FPGA device.

2. The autonomous control board according to the claim 1, wherein the external environment sensor is a camera that captures the external environment of the autonomous functioning apparatus, and the external environment data obtainer obtains the image data, as the external environment data, outputted from the camera.

3. The autonomous control board according to claim 1, wherein the autonomous control board is constituted of a single printed wiring board on which the command data line and the functioning control signal line are formed, and the external control FPGA device, the at least one data processing FPGA device, the external command data receiver, and the control signal outputter are mounted on the single printed wiring board.

4. The autonomous control board according to the claim 3, wherein the single printed wiring board has a plurality of data processing device mounting areas that receive a plurality of data processing lines extending from the external control FPGA device and on each of which one of the at least one data processing FPGA device is mountable, the at least one data processing FPGA device is mounted on a part of or all of the plurality of data processing device mounting areas.

5. The autonomous control board according to claim 1, further comprising: a non-volatile first memory configured to store first configuration data that represent a first circuit constructed by the first logic circuit of the external control FPGA device, the non-volatile first memory being electrically connected to the external control FPGA device; and a non-volatile second memory configured to store second configuration data that represent at least a part of a second circuit constructed by the second logic circuit of one of the at least one data processing FPGA device, the non-volatile second memory being electrically connected to said one of the at least one data processing FPGA device, wherein the non-volatile first memory has a capacity equal to or larger than that of the non-volatile second memory.

6. The autonomous control board according to claim 1, wherein each of the at least one FPGA connection terminal of the external control FPGA device has a maximum data transfer speed higher than a maximum data transfer speed of the external environment data.

7. The autonomous control board according to claim 1, wherein the processor of the external control FPGA device is a first processor, and each of the at least one data processing FPGA device has a second processor.

8. The autonomous control board according to claim 1, wherein each of the at least one FPGA connection terminal performs serial communication.

9. The autonomous control board according to claim 1, further comprising a debug connector connected to each of the at least one data processing FPGA device, the debug connector being removably connectable to a communication device that is communicable with said each of the at least one data processing FPGA device.

10. The autonomous control board according to claim 1, further comprising a power relay configured to be conductive in response to an output signal of the external control FPGA device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0112] FIG. 1 is a block diagram showing a configuration of an autonomous control board according to a first embodiment of the present teaching.

[0113] FIG. 2 is a block diagram showing a first example of the autonomous control board shown in FIG. 1.

[0114] FIG. 3 is a block diagram showing a first application of the autonomous control board shown in FIG. 2.

[0115] FIG. 4 is a block diagram showing a first application of the autonomous control board shown in FIG. 2.

[0116] FIG. 5 is a block diagram showing a conventional solution, in which a plurality of FPGA devices is employed in response to processing that cannot be performed by a single FPGA device.

DESCRIPTION OF EMBODIMENTS

[0117] Embodiments of the present teaching will be described below with reference to the drawings.

First Embodiment

[0118] FIG. 1 is a block diagram showing a configuration of the autonomous control board according to the first embodiment of the present teaching.

[0119] The autonomous control board 10 shown in FIG. 1 is a board used for the autonomous functioning apparatus 1. The autonomous functioning apparatus 1 can autonomously perform a series of functioning without an operator, that is, the human operation. However, a series of functioning is at least initiated by an operation. The external command device RC is provided outside the autonomous functioning apparatus 1. The external command device RC commands at least an initiation of a series of functioning. For example, even when the functioning is performed without the operation at the reserved time, the reservation of the time and the corresponding functioning are instructed prior to the functioning. That is, a series of functioning including the count up to the reservation time is initiated by a preceding operation. However, when a series of functioning is initiated by an operation, the series of functioning is autonomously performed without any operations. The series of functioning may include a count of the time to the next functioning. That is, the series of functioning includes functioning that does not involve movement or deformation of the component. The series of functioning is highly abstract in that, for example, going around so as to cover a predetermined range while avoiding an obstacle based on an image captured by the on-board camera. However, the contents of the series of functioning are not limited to this, and may be, for example, more specific contents such as “stopping after moving 20 m forward”.

[0120] The autonomous control board 10 includes an external command data receiver 19, an external environment data obtainer 110, a control signal outputter 130, and a functioning control signal generation circuit 160. The autonomous control board 10 is a printed circuit board. The printed circuit board is a single printed wiring board 101 on which electronic components are mounted. The external environment data obtainer 110, the control signal outputter 130, and the functioning control signal generation circuit 160 are mounted on the printed wiring board 101.

[0121] The external command data receiver 19 obtains command data transmitted from the external command device RC. The external command data receiver 19 wirelessly communicates with, for example, the external command device RC at a remote area. However, it is also possible to adopt a configuration in which the external command data receiver 19 is wired to the external command device RC.

[0122] The external command data receiver 19 supplies command data to the external control FPGA device 170. Command data is a control command that is transmitted to the external control FPGA device 170.

[0123] The external environment data obtainer 110 is communicably connected to the external environment sensor 11. The external environment sensor 11 obtains external environment information of the autonomous functioning apparatus 1. The external environment data obtainer 110 obtains external environment data outputted from the external environment sensor 11.

[0124] The external environment sensor 11 is, for example, a camera for capturing outside the autonomous functioning apparatus 1. In this case, the external environment data is image data. The external environment data obtainer 110 is, for example, a connector connected to a cable extending from the external environment sensor 11.

[0125] The control signal outputter 130 is communicably connected to the on-board controlled object 121 provided in the autonomous functioning apparatus 1. The control signal outputter 130 outputs a functioning control signal for controlling the on-board controlled object 121 to the on-board controlled object 121.

[0126] The on-board controlled object 121 is, for example, a functioning device having an actuator and mechanically functioned by electric control. For example, when the autonomous functioning apparatus 1 is a vehicle, the on-board controlled object 121 is a travelling device having a motor as an actuator. The on-board controlled object 121 may include a control device different from the autonomous control board 10 for controlling, for example, an actuator. However, the on-board controlled object 121 is not limited to this, and may be, for example, an actuator without a control device.

[0127] The functioning control signal generation circuit 160 generates a functioning control signal based on command data. The functioning control signal generation circuit 160 generates a functioning control signal based on the external environment data. The functioning control signal generation circuit 160 starts the control of the autonomous functioning based on the command data and continues the control based on the external environment data. The functioning control signal generation circuit 160 includes the external control FPGA device 170 and data processing FPGA devices 180A, 180B. In the example shown in FIG. 1, a single external control FPGA device 170 and two data processing FPGA devices 180A, 180B are provided. The functioning control signal generation circuit 160 includes an external environment data line 111 and a functioning control signal line 131. The functioning control signal generation circuit 160 includes a first memory 170A that is nonvolatile and second memories 185A, 185B. The functioning control signal generation circuit 160 includes a command data line 191 and a functioning control signal line 131. The command data line 191 transmits command data from the external command data receiver 19 to the external control FPGA device 170. The functioning control signal line 131 transmits a functioning control signal from the external control FPGA device 170 to the control signal outputter 130. The functioning control signal generation circuit 160 includes an external environment data line 111.

[0128] The external control FPGA device 170 includes a first logic circuit 171, a processor 172, a command receiving terminal 175, a control outputting terminal 174, FPGA connection terminals 176, 177, 178, 179, and a data obtaining terminal 173. The first logic circuit 171 is a programmable circuit. That is, the first logic circuit 171 is a reprogrammable logic circuit. The external control FPGA device 170 loads connection information from the outside in initialization processing after power-on or reset, and constructs a processing function of the first logic circuit 171 based on this connection information. The external control FPGA device 170 starts processing after the processing function of the first logic circuit 171 has been constructed.

[0129] The processor 172 executes a program stored in the memory while sequentially reading the program by accessing the external memory after initialization processing after power-on or reset. On the other hand, in the first logic circuit 171, the processing function is basically constructed based on the connection information from the outside before the execution of the circuit, that is, at the time of initialization. In other words, the reading of the external memory is completed before the execution of the processing is started.

[0130] The external environment data line 111 transmits external environment data from the external environment data obtainer 110 to the external control FPGA device 170.

[0131] The functioning control signal line 131 transmits a functioning control signal from the external control FPGA device 170 to the control signal outputter 130.

[0132] The control outputting terminal 174 is connected to the control signal outputter 130 and outputs a functioning control signal for controlling the on-board controlled object 121.

[0133] The command receiving terminal 175 receives command data from the external command device RC provided outside the autonomous functioning apparatus 1. The command receiving terminal 175 is connected to the external command data receiver 19 through a command data line 191.

[0134] The data obtaining terminal 173 is connected to the external environment data line 111 and receives external environment data.

[0135] The FPGA connection terminals 176, 177, 178, and 179 are used for communicatively connecting the data processing FPGA devices 180A and 180B.

[0136] The autonomous control board 10 has a command transmission pathway CR. The command transmission pathway CR is configured to transmit a control command between the external command data receiver 19 and the control signal outputter 130. The autonomous control board 10 has the external command data receiver 19, the command data line 191, the external control FPGA device 170, the functioning control signal line 131, and the control signal outputter 130. The control command is either command data or a functioning control signal. The command transmission pathway CR includes the external command data receiver 19, the command data line 191, the external control FPGA device 170, the functioning control signal line 131, and the control signal outputter 130. The command transmission pathway CR transmits a control command from the external command data receiver to the control signal outputter.

[0137] More specifically, the external command data receiver 19, the command data line 191, the external control FPGA device 170, the functioning control signal line 131, and the control signal outputter 130 form the command transmission pathway CR.

[0138] The data processing FPGA device 180A includes a second logic circuit 181A. The other data processing FPGA device 180B also includes a second logic circuit 181B.

[0139] The plurality of data processing FPGA devices 180A and 180 B has one-to-one connection to any one of a plurality of FPGA connection terminals 176, 177, 178, 179 of the external control FPGA device 170. In the example shown in FIG. 1, the data processing FPGA device 180A has one-to-one connection to the FPGA connection terminal 176. The other data processing FPGA device 180B has one-to-one connection to the FPGA connection terminal 177. In the example of the autonomous control board 10 shown in FIG. 1, the remaining FPGA connection terminals 178 and 179 are spare terminals. The data processing FPGA devices 180A and 180B input data to be processed from the external control FPGA device 170 through data processing lines 183A, 183B, and output the processed data to the external control FPGA device 170.

[0140] The data processing FPGA device 180A includes FPGA connection terminals 186A, 187A, 188A, and 189A. The FPGA connection terminal 186A of the data processing FPGA device 180A is connected to the FPGA connection terminal 176 of the external control FPGA device 170.

[0141] The data processing FPGA device 180A is connected to the FPGA connection terminal 176 of the external control FPGA device 170 through the data processing line 183A.

[0142] The other data processing FPGA device 180B includes FPGA connection terminals 186B, 187B, 188B, and 189B. The FPGA connection terminal 187B of the data processing FPGA device 180B is connected to the FPGA connection terminal 177 of the external control FPGA device 170.

[0143] The data processing FPGA device 180B is connected to the FPGA connection terminal 177 of the external control FPGA device 170 through the data processing line 183B.

[0144] Each of the data processing lines 183A and 183B is a line independent of the command transmission pathway CR. The data processing lines 183A and 183B are not directly connected to any of the external command data receiver 19, the command data line 191, the functioning control signal line 131, or the control signal outputter 130. Therefore, none of the data processing FPGA devices 180A and 180B are directly connected to either the external command data receiver 19 or the control signal outputter 130.

[0145] None of the data processing FPGA devices 180A and 180B directly exchanges data with either the external command data receiver 19 or the control signal outputter 130. The data processing FPGA devices 180A and 180B indirectly exchange data with the external command data receiver 19 or the control signal outputter 130 through the external control FPGA device 170.

[0146] The external control FPGA device 170 in this embodiment mediates data in the command transmission pathway CR. More specifically, the command receiving terminal 175 of the external control FPGA device 170 receives command data from the external command device RC. The control outputting terminal 174 of the external control FPGA device 170 is connected to the control signal outputter 130 and outputs a functioning control signal for controlling the on-board controlled object 121. The command data or the functioning control signal is a functioning control command transmitted in the command transmission pathway CR.

[0147] The external control FPGA device 170 receives external environment data from the external environment data obtainer 110 through the external environment data line 111 connected to the data obtaining terminal 173. Each of two data processing FPGA devices 180A and 180B has respectively one-to-one connection to any one of the FPGA connection terminals 176, 177, 178, and 179 provided in the external control FPGA device 170. Consequently, the two data processing FPGA devices 180A and 180B can share at least a part of the processing based on the external environment data inputted to the external control FPGA device 170. Therefore, the autonomous control board 10 can control the on-board controlled object 121 provided in the autonomous functioning apparatus 1 based on the external environment data outputted from the external environment sensor 11 for obtaining the external information of the autonomous functioning apparatus 1.

[0148] As the autonomous functioning apparatus 1 become advanced, in the design stage of the autonomous control board 10, the command data received from the external command device RC may become more abstract than the actual condition of the previous model or the assumption in the design of the previous stage. For example, after command data including a destination in the autonomous travelling is received, the command may be executed while performing advanced processing such as travelling to the destination while regulating a travelling route in accordance with an image recognition result based on data of a camera as the external environment sensor 11. In such a case, one or more data processing FPGA devices 180A, 180B are not connected to the external command data receiver 19, and the external control FPGA device 170 is connected to the external command data receiver 19 and the control signal outputter 130. Accordingly, without changing the connection between the external command data receiver 19 and the control signal outputter 130, the increased processing can be responded by regulating the number of the data processing FPGA devices 180A and 180B connected to the plurality of FPGA connection terminals 176, and 177. In other words, the change for responding to the increased processing is possible while the basic configuration of the command transmission pathway CR for transmitting the functioning control command remain unchanged.

[0149] The processor 172 provided in the external control FPGA device 170 executes software. Accordingly, the external control FPGA device 170 can flexibly distribute processing to the data processing FPGA devices 180A and 180B depending on the increased or decreased amounts of external environment data outputted from the external environment sensor 11 in relation to the command data. Consequently, high scalability is achieved for various applications of the autonomous functioning apparatus 1.

[0150] As the autonomous functioning apparatus 1 become more advanced, some types of the autonomous functioning apparatus 1 may be provided with an external environment sensor 11 with different performance, and thus the amount of external environment data outputted from the external environment sensor 11 may be different from that of the conventional sensor. In such a case, one or more data processing FPGA devices 180A and 180B are not directly connected to the external environment data obtainer and the external control FPGA device 170 is connected to the external environment data obtainer 110. Accordingly, the different amounts of data can be processed without changing the connection to the external environment data obtainer 110 by regulating the number of data processing FPGA devices 180A and 180B, which process data. Since both the logic circuit of the external control FPGA device 170 and the data processing FPGA devices 180A and 180B are programmable, the logic circuit constructed in both FPGA devices 170, 180A, 180B can be easily changed when the application of the autonomous control board 10 is changed. In addition, for example, in response to the additional input of data other than the external environment data, the external control FPGA device 170 configured to execute software can flexibly distribute the processing and the data to the data processing FPGA devices 180A and 180B.

[0151] Consequently, high versatility is achieved for the types of the on-board controlled object in the autonomous functioning apparatus 1.

First Application

[0152] FIG. 2 is a block diagram showing a first example of the autonomous control board shown in FIG. 1.

[0153] In FIG. 2, elements corresponding to those in FIG. 1 are denoted by the same reference numerals as those in the first embodiment, and a part of the common description is omitted.

[0154] The autonomous control board 10 of the application shown in FIG. 2 is on-board the autonomous functioning apparatus 1′, which autonomously functions. The autonomous functioning apparatus 1′ detects the external environment of the autonomous functioning apparatus 1′ by itself. The autonomous functioning apparatus 1′ recognizes the content of the detected result and controls the functioning of the autonomous functioning apparatus 1′ based on the recognized result.

[0155] The autonomous functioning apparatus 1′ as an example on which the autonomous control board 10 is mounted is an autonomous travelling vehicle. A camera 11′ is used as the external environment sensor. A travelling device 121′ having an actuator is used as the on-board controlled object. That is, the autonomous functioning apparatus 1′ includes the camera 11′, the autonomous control board 10, and the travelling device 121′.

[0156] The external control FPGA device 170 obtains command data representing the initiation of a series of autonomous functioning from the external command device RC through the external command data receiver 19. The external control FPGA device 170 initiates the control of autonomous travelling based on the command data.

[0157] The autonomous functioning apparatus 1′ on which the autonomous control board 10 is mounted determines its own travelling route based on an image captured by the camera 11′ and travels. The autonomous control board 10 determines the travelling route of the autonomous functioning apparatus 1′ based on the image data of the image outputted from the camera 11′. The autonomous control board 10 controls the travelling device 121′ based on the determined travelling route. The travelling device 121′ travels the autonomous travelling vehicle as the autonomous functioning apparatus 1′ based on the control of the autonomous control board 10.

[0158] The autonomous control board 10 includes the external environment data obtainer 110, the control signal outputter 130, and the functioning control signal generation circuit 160.

[0159] The external environment data obtainer 110 is communicably connected to the camera 11′.

[0160] The camera 11′ captures the outside of the autonomous functioning apparatus 1′. The camera 11′ outputs image data representing the captured image as external environment data. The external environment data obtainer 110 is connected to, for example, a cable extending from the camera 11′. The external environment data obtainer 110 obtains image data outputted from the camera 11′.

[0161] The control signal outputter 130 is communicatively connected to the travelling device 121′. The control signal outputter 130 outputs a functioning control signal for controlling the travelling device 121′ to the travelling device 121′.

[0162] The travelling device 121′ is a functioning device having, for example, an actuator, and mechanically functioned by electrical control. The travelling device 121′ also includes a control device different from the autonomous control board 10, for example, for controlling an actuator.

[0163] The functioning control signal generation circuit 160 generates a functioning control signal based on image data. The functioning control signal generation circuit 160 includes the external control FPGA device 170 and two data processing FPGA devices 180A and 180B.

[0164] The external control FPGA device 170 includes the first logic circuit 171, the processor 172, the FPGA connection terminal 176, 177, 178, 179, and the data obtaining terminal 173. The first logic circuit 171 is a programmable circuit. That is, the first logic circuit 171 is a reprogrammable logic circuit. The external control FPGA device 170 loads connection information from the outside in initialization processing after power-on or reset, and constructs a processing function of the first logic circuit 171 based on the connection information. The external control FPGA device 170 starts processing after the processing function of the first logic circuit 171 is constructed.

[0165] The processor 172 executes the program stored in the memory while sequentially reading the program by accessing the external memory after initialization processing after power-on or reset. On the other hand, in the first logic circuit 171, the processing function is basically constructed based on the connection information from the outside before the execution of the circuit, that is, at the time of initialization. That is, the reading of the external memory is completed before the execution of the process is started.

[0166] The data obtaining terminal 173 is connected to the external environment data line 111 and receives image data.

[0167] The external environment data line 111 transmits image data from the external environment data obtainer 110 to an external control FPGA device 170.

[0168] The functioning control signal line 131 transmits a functioning control signal from the external control FPGA device 170 to the control signal outputter 130.

[0169] Each of the FPGA connection terminals 176, 177, 178, 179 is a dedicated terminal for communicating with an FPGA device other than the external control FPGA device 170. Each of the FPGA connection terminals 176, 177, 178, 179 is a high-speed transfer terminal having a maximum data transfer speed higher than the external environment data. The FPGA connection terminal 176, 177, 178, 179 is a terminal capable of performing serial communication.

[0170] A plurality of data processing device mount areas (or amounting areas) TA, TB, TC are formed on a single printed wiring board 101. Each of the data processing device mount areas TA, TB, TC is formed so as to be able to mount a data processing FPGA device. Each of the data processing device mount areas TA, TB, TC receives a plurality of data processing lines 183A, 183B, 183C extending from the external control FPGA device 170. That is, the plurality of data processing lines 183A, 183B, and 183C respectively extend from the external control FPGA device 170 to the data processing device mount areas TA, TB, and TC.

[0171] The data processing FPGA devices 180A and 180B are mounted on data processing device mount areas TA, TB, which are a part of data processing device mount areas TA, TB, TC.

[0172] The data processing FPGA device 180A includes a second logic circuit 181A and a processor 182A. The other data processing FPGA device 180B also includes a second logic circuit 181B and a processor 182B. A variety of processing that can be responded by the use of the data processing FPGA devices 180A and 180B can be wider by providing a processor in the data processing FPGA devices 180A and 180B.

[0173] The data processing FPGA device 180A has one-to-one connection to the FPGA connection terminal 176. The other data processing FPGA device 180B has one-to-one connection to the FPGA connection terminal 177. The FPGA connection terminals 178 and 179 are spare terminals.

[0174] The data processing FPGA device 180A includes the FPGA connection terminals 186A, 187A, 188A, 189A. The FPGA connection terminal 186A of the data processing FPGA device 180A and the FPGA connection terminal 176 of the external control FPGA device 170 are connected.

[0175] The other data processing FPGA device 180B includes FPGA connection terminals 186B, 187B, 188B, 189B. The FPGA connection terminal 187B of the data processing FPGA device 180B and the FPGA connection terminal 177 of the external control FPGA device 170 are connected.

[0176] The autonomous control board 10 includes the nonvolatile first memory 170A that is electrically connected to the external control FPGA device 170, and nonvolatile second memories 185A, 185B that are electrically connected to the data processing FPGA devices 180A, 180B. The autonomous control board 10 includes volatile memories 17RA, 18RA, 18RB that are electrically connected to the external control FPGA device 170 and the data processing FPGA devices 180A, 180B, respectively.

[0177] The first memory 170A stores configuration data of a logic circuit constructed in the external control FPGA device 170 (first configuration data). The second memories 185A and 185B store configuration data of a logic circuit constructed in the data processing FPGA devices 180A and 180B (second configuration data).

[0178] The first memory 170A has a capacity equal to or larger than any of the second memories 185A and 185B.

[0179] More specifically, the first memory 170A stores configuration data of a logic circuit secondarily constructed in the data processing FPGA devices 180A, 180B. The logic circuit constructed secondarily is different from the logic circuit constructed by the second configuration data of the second memories 185A, 185B. The logic circuit constructed secondarily is a circuit for processing image data in the data processing FPGA devices 180A and 180B.

[0180] In the second memories 185A and 185B, configuration data of an initialization circuit for constructing circuits of the data processing FPGA devices 180 A, 180 B by configuration data stored in the first memory 170A is stored.

[0181] The data processing FPGA devices 180A and 180B construct an initialization circuit by the second configuration data stored in the second memories 185A and 185B after resetting. The initialization circuit constructed in the data processing FPGA devices 180A and 180B reconstructs a logic circuit based on the first configuration data stored in the first memory 170A. In this case, the second memories 185A and 185B store only the second configuration data representing the initialization circuit regardless of the contents of the processing function of data. Since the first memory 170A has a capacity equal to or larger than any of the second memories 185A and 185B, configuration data of a circuit for processing image data reconstructed in the data processing FPGA devices 180A and 180B can be stored.

[0182] The autonomous control board 10 includes a debug connector DC connected to each of the data processing FPGA devices 180A and 180B. A communication device (not shown) that is communicable with the data processing FPGA devices 180A and 180B is removably connected to the debug connector DC. The communication device is, for example, a debugger device.

[0183] For example, during the maintenance of the autonomous control board 10, the communication device can be connected to the debug connector DC when debugging circuits and execution programs constructed in the data processing FPGA devices 180A and 180B.

[0184] The processing in the autonomous control board 10 of the example shown in FIG. 2 includes, for example, the following processing.

[0185] The external control FPGA device 170 obtains command data representing the initiation of a series of autonomous functioning from the external command device RC through the external command data receiver 19. The external control FPGA device 170 starts the control of autonomous travelling based on the command data. In control, the external control FPGA device 170 outputs a functioning control signal to the control signal outputter 130. In this way, the instruction from the external command device RC and the control of the on-board controlled object 121 are performed along the command transmission pathway CR from the external command data receiver 19 to the control signal outputter 130.

[0186] The external control FPGA device 170 receives image data outputted from the camera 11′. The external control FPGA device 170 outputs data based on the received image data to data processing FPGA devices 180A and 180B. The data that the external control FPGA device 170 outputs to the data processing FPGA devices 180A and 180B is, for example, image data. However, the data that the external control FPGA device 170 outputs may be, for example, data obtained by processing the image data.

[0187] The data processing FPGA devices 180A and 180B, for example, function as accelerators that assist the processing of image data received by the external control FPGA device 170. The data processing FPGA devices 180A and 180B share processing of image data. In the example shown in FIG. 2, the data processing FPGA devices 180A and 180B output the processed data to the external control FPGA device 170. The external control FPGA device 170 generates a functioning control signal based on the processed result outputted from the data processing FPGA devices 180A and 180B. The external control FPGA device 170 outputs a functioning control signal to the travelling device 121′. The data processing FPGA device 180A and the data processing FPGA device 180B perform different processing, for example, for common image data. However, the data processing FPGA device 180A and the data processing FPGA device 180B can be configured to process mutually different image data. For example, the data processing FPGA device 180A receives a part of the image data received by the external control FPGA device 170. The data processing FPGA device 180B receives a part of data different from a part of data received by the data processing FPGA device 180A.

[0188] Although the example of the processing has been described above, the processing in the autonomous control board 10 of the example shown in FIG. 2 is not limited to the above. For example, the external control FPGA device 170 can be configured to perform processing of image data, and the data processing FPGA devices 180A and 180B can be configured to perform processing other than image data processing. For example, the data processing FPGA devices 180A and 180B can be configured to perform processing of selecting a travelling route.

[0189] The autonomous control board 10 includes a power relay 120. The power relay 120 is connected to a power supply device (not shown) of the autonomous functioning apparatus 1′. The power relay 120 is controlled by the external control FPGA device 170. The power relay 120 is conducted by the output of the external control FPGA device 170. The power relay 120 controls the state of power supply to the autonomous functioning apparatus 1′ including the autonomous control board 10. For example, when the power relay 120 functions in response to the control of the external control FPGA device 170, the power supply to the power supply device (not shown) is cut off. The output signal of the power relay 120 can be connected in series with the power relay provided on a board (not shown) other than the autonomous control board 10. Thus, for example, when abnormal functioning of the autonomous control board 10 and the peripheral device is detected, the conduction of the autonomous functioning apparatus 1′ can be forcibly stopped. The forced stop can be achieved by a simple and highly reliable configuration using the power relay.

[0190] As the function of the vehicle as the autonomous functioning apparatus 1 become advanced, command data received from the external command device RC may be more abstract than the actual condition of the previous model or the assumption in the design of the previous stage. According to the autonomous control board 10 of this example, the data processing FPGA devices 180A, 180B, . . . are provided in a pathway independent of the command transmission pathway CR. Accordingly, as the application or function of the vehicle as the autonomous functioning apparatus 1 become advanced, the number of cameras 11′ or the processing of image data may be changed, and this change can be responded by regulating the number of the data processing FPGA devices 180A, 180B, . . . . For example, the data processing FPGA devices 180A, 180B, and 180C are mounted on all of the data processing device mount areas TA, TB, and TC, which are part of the data processing device mount areas TA, TB, and TC.

[0191] This case can be responded by regulating the number of data processing FPGA devices 180A, 180B, and 180C connected to the FPGA connection terminals 176, 177, 178, 179 without changing the connection with the external environment data obtainer 110. Therefore, it is possible to flexibly respond to the increased or decreased amounts of image data outputted from the camera 11′ that can be used for the autonomous functioning apparatus 1.

[0192] For example, in response to the additional input of data other than the external environment data, the external control FPGA device 170 configured to execute software can flexibly distribute the processing and the data to the data processing FPGA devices 180A, 180B, and 180C. Consequently, high versatility is achieved for the types of the on-board controlled object in the autonomous functioning apparatus 1.

[0193] Thus, the autonomous control board 10 can have high scalability and high versatility.

[0194] Each of the data processing FPGA devices 180A and 180B has one-to-one connection to the FPGA connection terminal 176 and 177 without having connection to the external environment data obtainer 110. Therefore, the processing capability of the autonomous control board 10 can be changed while a circuit for supplying image data to the external control FPGA device 170 remains unchanged. Therefore, the autonomous control board 10 has higher scalability.

[0195] The first memory 170A has a capacity equal to or larger than any of the second memories 185A and 185B. Therefore, the first memory 170A can store configuration data of the processing function of data, which is reconstructed in the data processing FPGA devices 180A and 180B. On the other hand, the second memories 185A and 185B can store configuration data of the initialization circuit constructed in the data processing FPGA devices 180 A, 180 B (second configuration data) regardless of the processing contents of image data. Accordingly, it is easy to add a data processing FPGA device including the second memory (e.g., 180C). Therefore, the autonomous control board 10 can have higher scalability and versatility.

[0196] Each of the FPGA connection terminals 176, 177, 178, 179 has a maximum data transfer speed higher than the external environment data. Consequently, each of the data processing FPGA devices 180A, 180B is allowed to perform processing for generating a functioning control signal after image data is transmitted to each of the data processing FPGA devices 180A, 180B.

[0197] The FPGA connection terminals 176, 177, 178, 179 performs serial communication. The number of the respective FPGA connection terminals 176, 177, 178, 179 is smaller than, for example, that of the parallel communication. Thus, more data processing FPGA devices 180A, 180B, 180C . . . can be connected to the external control FPGA device 170 having a limited number of terminals. Higher scalability can be achieved.

[0198] FIG. 3 is a block diagram showing a first application of the autonomous control board shown in FIG. 2.

[0199] The application shown in FIG. 3 is an autonomous travelling vehicle 1A. The autonomous travelling vehicle 1A includes the camera 11′, the autonomous control board 10, the travelling device 121A, the external command data receiver 19, and a power supply unit 14. The travelling device 121A is a device for travelling the autonomous travelling vehicle 1A. The external command data receiver 19 communicates with the external command device RC at a remote area.

[0200] FIG. 4 is a block diagram showing a second application of the autonomous control board shown in FIG. 2.

[0201] The application shown in FIG. 4 is a robot arm 1B. The robot arm 1B includes the camera 11′, the autonomous control board 10, and an arm functioning device 121B.

[0202] The autonomous control board 10 shown in FIG. 2 is applicable to the autonomous travelling vehicle 1A or the robot arm 1B while changing, for example, the number of the data processing FPGA devices 180A, 180B, 180C . . . and the contents of the first configuration data without changing the basic structure of the autonomous control board 10.

REFERENCE SIGNS LIST

[0203] 1,1′ autonomous functioning apparatus

[0204] 10 autonomous control board

[0205] 11 external environment sensor

[0206] 101 printed wiring board

[0207] 110 external environment data obtainer

[0208] 111 external environment data line

[0209] 120 power relay

[0210] 121 on-board controlled object

[0211] 130 control signal outputter

[0212] 131 functioning control signal line

[0213] 160 functioning control signal generation circuit

[0214] 170 external control FPGA device

[0215] 171 first logic circuit

[0216] 172 processor

[0217] 173 data obtaining terminal

[0218] 174 control outputting terminal

[0219] 175 command receiving terminal

[0220] 170A first memory

[0221] 176,177,178,179 FPGA connection terminal

[0222] 180A,180B data processing FPGA device

[0223] 181A,181B second logic circuit

[0224] 182A,182B processor

[0225] 19 external command data receiver

[0226] DC debug connector

[0227] RC external command device

[0228] TA,TB,TC data processing device mount area