Integrated circuit comprising a single photon-based avalanche diode array and method for manufacturing such integrated circuit

Abstract

An integrated circuit is formed in a semiconductor substrate. An array of single-photon-avalanche diodes is formed at a front side of the semiconductor substrate. The array includes first and second diodes that are adjacent to each other. A Bragg mirror is positioned between the first and second diodes. The Bragg mirror is configured to prevent a propagation of light between the first and second diodes.

Claims

1. An integrated circuit comprising: a semiconductor substrate; an array of single-photon-avalanche diodes formed at a front side of the semiconductor substrate, the array including first and second diodes that are adjacent to each other; and a Bragg mirror positioned between the first and second diodes, the Bragg mirror configured to prevent a propagation of light between the first and second diodes, wherein each Bragg mirror (MB) comprises at least three alternate layers of at least two materials of different refractive indices, at least two of the layers extending depthwise into the substrate (SBT) from the front side down to a bottom insulating region that defines a bottom of each diode, the bottom insulating region electrically insulating each diode from the rest of the substrate, wherein at least one of the layers extends depthwise from the front side down to a far end located between the front side and the bottom insulating region.

2. The integrated circuit according to claim 1, wherein each Bragg mirror is configured to prevent the propagation of light having a wavelength among the wavelengths capable of being generated by an energetic relaxation of hot carriers generated by an avalanche effect triggered in the first or second diode.

3. The integrated circuit according to claim 1, wherein each Bragg mirror (MB) comprises a plurality of layers and is configured to reflect light having an angle of incidence between 0° and 90° on the Bragg mirror, with respect to an axis orthogonal to each layer of material of the Bragg mirror.

4. The integrated circuit according to claim 1, wherein the at least two materials of different refractive indices comprise silicon and silicon dioxide.

5. The integrated circuit according to claim 4, further comprising lateral deep trench isolation regions, wherein the at least three alternate layers of at least two materials comprising silicon dioxide and the lateral deep trench isolation regions have the same depth and the same structure.

6. A method for fabricating an integrated circuit, the method comprising: forming an array of single-photon-avalanche diodes within a semiconductor substrate, the array including first and second diodes, wherein forming the array of single-photon-avalanche diodes comprises forming a bottom insulating region in the substrate, the bottom insulating region defining a bottom of each diode and electrically insulating each diode from the rest of the substrate; and forming a Bragg mirror between the first and second diodes, the Bragg mirror configured to prevent a propagation of light between the first and second diodes, wherein each Bragg mirror (MB) comprises at least three alternate layers of at least two materials of different refractive indices, at least two of the layers extending depthwise into the substrate (SBT) from a front side down to the bottom insulating region, and wherein at least one of the layers extends depthwise from the front side down to a far end located between the front side and the bottom insulating region.

7. The method according to claim 6, wherein the Bragg mirror is formed so as to reflect light having a wavelength among the wavelengths capable of being generated by an energetic relaxation of hot carriers generated by an avalanche effect triggered in the first or second diodes.

8. The method according to claim 6, wherein the Bragg mirror is formed so as to reflect light having an angle of incidence comprised between 0° and 90° on the Bragg mirror relative to an axis orthogonal to a main surface of the Bragg mirror.

9. The method according to claim 6, wherein forming the Bragg mirror comprises forming at least three alternate layers of at least two materials of different refractive indices between the first and second diodes.

10. The method according to claim 6, wherein forming the Bragg mirror comprises: forming an initial volume of a first material between the first and second diodes, the first material having a first refractive index; etching a trench into this first material, the trench having lateral edges delineated by the first material; and forming alternating layers of a second material and the first material successively from the lateral edges of the trench until the trench is filled, the second material having a second refractive index different from the first refractive index.

11. The method according to claim 10, wherein the first material is one of silicon or silicon diode and the second material the other of silicon or silicon dioxide.

12. The method according to claim 6, wherein forming the Bragg mirror comprises: forming an initial volume of a first material between the first and second diodes, the first material having a first refractive index; etching a plurality of trenches into the volume of the first material; and filling each trench with a second material having a second refractive index different from the first refractive index in order to form layers of second material, each volume of first material located between two layers of second material forming a layer of first material.

13. The method according to claim 12, wherein at least one of the trenches filled with second material extends depthwise from the front side down to the far end located between the front side and the bottom insulating region.

14. The method according to claim 13, wherein the first material is one of silicon or silicon diode and the second material the other of silicon or silicon dioxide, the method further comprising forming lateral deep trench isolation regions comprising silicon dioxide, wherein the layers of silicon dioxide are formed simultaneously with the formation of the lateral deep trench isolation regions.

15. A method for fabricating an integrated circuit, the method comprising: forming an array of single-photon-avalanche diodes within a semiconductor substrate; and forming a plurality of structures, each structure including alternating layers of silicon and silicon dioxide extending into the substrate between adjacent pairs of the diodes, wherein forming the plurality of structures comprises: forming a plurality of first trenches in the substrate, each first trench disposed between a respective one of the adjacent pairs of the diodes, filling in the plurality of first trenches with a first material, the first material being one of silicon or silicon dioxide, etching a respective second trench into the first material of each of the plurality of first trenches so that each respective second trench has lateral edges delineated by the first material, and forming alternating layers of a second material and the first material successively from the lateral edges of each respective second trench, the second material being the other one of silicon or silicon dioxide.

16. The method of claim 15, further comprising forming lateral deep trench isolation regions around each pair of the array of single-photon-avalanche diodes.

17. The method according to claim 15, wherein forming the array of single-photon-avalanche diodes comprises forming a bottom insulating region in the substrate, the bottom insulating region defining a bottom of each diode and electrically insulating each diode from the rest of the substrate.

18. A method for fabricating an integrated circuit, the method comprising: forming an array of single-photon-avalanche diodes within a semiconductor substrate; and forming a plurality of structures, each structure including alternating layers of silicon and silicon dioxide extending into the substrate between adjacent pairs of the diodes, wherein forming the plurality of structures comprises: forming a plurality of trenches in the substrate, each trench disposed between a respective one of the adjacent pairs of the diodes; filling each trench with a first material, the first material being one of silicon or silicon dioxide; for each of the trenches, etching a plurality of smaller trenches into the first material; and for each of the trenches, filling each smaller trench with a second material, the second material being the other one of silicon or silicon dioxide.

19. The method of claim 18, further comprising forming lateral deep trench isolation regions around each pair of the array of single-photon-avalanche diodes.

20. The method according to claim 18, wherein forming the array of single-photon-avalanche diodes comprises forming a bottom insulating region in the substrate, the bottom insulating region defining a bottom of each diode and electrically insulating each diode from the rest of the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent on examining the detailed description of completely non-limiting modes of implementation and embodiments and the appended drawings, in which:

(2) FIG. 1 is a schematic representation of a top view of an integrated circuit according to one embodiment of the invention;

(3) FIG. 2 is a schematic representation of a partial cross section through an integrated circuit according to a first embodiment of the invention;

(4) FIG. 3 is a schematic representation of a partial cross section through an integrated circuit according to a second embodiment of the invention;

(5) FIG. 4 is a schematic representation of an electronic device according to one embodiment of the invention;

(6) FIG. 5 illustrates the results of steps of a process for fabricating an integrated circuit according to a first mode of implementation of the invention; and

(7) FIG. 6 illustrates the results of steps of a process for fabricating an integrated circuit according to a second mode of implementation of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(8) FIG. 1 shows one embodiment of an integrated circuit CI according to the invention. The integrated circuit CI comprises a photodetector array RES. The photodetector array RES comprises a plurality of single-photon-avalanche diodes, i.e. what are called SPADs. In the embodiments shown in FIGS. 2 and 3, only two diodes SPAM.sub.1, SPAD.sub.2 have been shown. Preferably, all of the SPADs of the photodetector array RES are identical. In particular, each SPAD has a parallelogram shape. Preferably, the photodetector array RES lies in a plane.

(9) The SPADs allow light to be detected. In particular, the SPADs exploit the avalanche current of a p-n junction triggered by an incident photon to detect this photon.

(10) In particular, in the embodiments shown in FIGS. 2 and 3, each SPAD is formed in a semiconductor substrate SBT. Each SPAD comprises a first region REG.sub.1. of the SPAD. This first region REG.sub.1. is of a first conductivity type, for example n+-type. This first region REG.sub.1. is designed to capture photons incident on this portion of a side, called the front side FAV, of the semiconductor substrate SBT. This front side FAV in particular bounds the first region REG.sub.1.

(11) The front side FAV of the semiconductor substrate SBT bears components of the integrated circuit. In particular, the front side FAV is the side on which the region of the integrated circuit containing the electronic elements of the integrated circuit, such as transistors and diodes, is fabricated. This region is also referred to by the conventional acronym “FEOL” for “Front End Of Line”. The light signal to be detected by the array may be received either via the front side FAV or via a back side FAR of the substrate SBT, which side is opposite the front side FAV.

(12) The first region REG.sub.1 is connected to a cathode contact.

(13) Each SPAD furthermore comprises a second region REG.sub.2 of a second conductivity type, for example p−-type. This second region REG.sub.2 laterally frames the first region REG.sub.1.

(14) Each SPAD also comprises a third region REG.sub.3 of a third conductivity type, for example of p-type, connected to an anode contact. This third region REG.sub.3 in particular extends under the first region REG.sub.1 and the second region REG.sub.2.

(15) Each SPAD furthermore comprises a deep region REG.sub.4 of the second conductivity type, for example p−-type. This deep region REG.sub.4 is surrounded by the third region REG.sub.3.

(16) This deep region REG.sub.4 rests on a bottom insulating region ISO that extends under all of the SPADs of the photodetector array RES. Thus, each diode has a height suitable for capturing photons that is defined between the front side FAV of the substrate SBT and the back side FAR of the substrate SBT, which makes contact with the bottom insulating region ISO.

(17) Each SPAD is reverse biased. For example, the first region of REG.sub.1 of n+-type is raised to 20 V and the third region REG.sub.3 of p-type is kept at 0 V. In particular, each SPAD is the reversed biased beyond its breakdown voltage.

(18) A high reverse bias voltage generates a sufficiently high electric field for a single charge carrier introduced into a depletion region of the SPAD to be able to cause an avalanche that is self-sustained via one ionization per impact.

(19) During the avalanche in a SPAD, a high number of hot carriers are generated. These hot carriers relax by emitting parasitic light in the red or in the near infrared in all directions.

(20) In order to avoid electro-optical crosstalk between the SPADs of the array, the photodetector array RES also comprises a Bragg mirror MB between each SPAD of the photodetector array RES. Specifically, each Bragg mirror MB allows the parasitic light generated by a receiver SPAD to be reflected and/or absorbed so as to prevent this parasitic light from being communicated to a SPAD adjacent to this receiver SPAD.

(21) FIGS. 2 and 3 show two embodiments that include a Bragg mirror MB between two diodes SPAD.sub.1 and SPAD.sub.2. In these two embodiments, the Bragg mirror MB comprises a succession of at least two layers CO of materials MAT.sub.1, MAT.sub.2 of different refractive indices. This succession of layers CO allows the light incident on the Bragg mirror MB to be reflected and/or absorbed.

(22) In particular, the layers CO are oriented so as to extend vertically, i.e. orthogonally with respect to the front side FAV of the substrate SBT. Furthermore, the refractive index of a layer CO of the Bragg mirror MB is different from that of the adjacent layers CO.

(23) Each Bragg mirror MB thus has a first lateral side CL.sub.1 making contact with a first diode SPAM of the photodetector array RES and a second lateral side CL.sub.2, opposite the first lateral side CL.sub.1, making contact with a second diode SPAD.sub.2 of the photodetector array RES, which diode is adjacent to the first diode SPAD.sub.1.

(24) More particularly, the Bragg mirror MB may then comprise an alternate succession of layers CO of silicon and of layers CO of silicon dioxide, silicon and silicon dioxide having different refractive indices. These materials possess refractive indices allowing the use of layers CO of small thickness while being propitious to the reflection of the light able to be generated by an energetic relaxation of hot carriers generated by an avalanche effect triggered in one of the two respective diodes. Furthermore, silicon and silicon dioxide are materials that are mastered and commonplace in semiconductor devices. Thus, the fabrication of a Bragg mirror MB with such materials is relatively simple to implement and advantageous, in particular in terms of cost savings.

(25) The greater the number of layers CO that the Bragg mirror MB comprises, the higher its performance with respect to prevention of a diffusion of photons between the two diodes SPAD.sub.1, SPAD.sub.2 between which the Bragg mirror is positioned. In the embodiments shown in FIGS. 2 and 3, the Bragg mirror MB comprises five layers CO of silicon dioxide and four layers CO of silicon.

(26) The thickness of each layer may be chosen using the following Bragg relationship:
L=λo/4 n,

(27) where λo is the wavelength of interest and n is the refractive index of the layer.

(28) In particular, the wavelength of interest may be calculated using the following formula:

(29) $\begin{array}{cc}{\lambda }_0=\frac{{\lambda }_{\max }-{\lambda }_{\min }}{{\lambda }_{\max }\times {\lambda }_{\min }}& \left[\mathrm{Equation}1\right]\end{array}$

(30) In order to reflect parasitic light able to cause an avalanche in a SPAD adjacent to a SPAD that receives a photon, Xmin may be chosen to be between 500 nm and 600 nm (red) and λmax may be chosen to be between 1.1 μm and 1.2 μm (near infrared). Thus, λo may be equal to 824 nm. The thickness of the layers of silicon dioxide may then be equal to 142 nm and the thickness of the layers of silicon may be 56 nm.

(31) Each Bragg mirror MB of the photodetector array RES is at least suitable for reflecting light having an angle of incidence comprised between 0° and 60° on the Bragg mirror MB. Each Bragg mirror MB is then suitable for preventing the diffusion of the most detrimental photons. Specifically, the risk of crosstalk is highest for photons having an angle of incidence comprised between 0° and 60°.

(32) In the embodiment described above with reference to FIG. 2, each of the layers CO extends over the height of the diodes between which the Bragg mirror MB is positioned. Each layer CO therefore extends from the front side FAV of the substrate SBT to the bottom insulating region ISO.

(33) As a variant, as shown in FIG. 3, certain layers CO′ of the Bragg mirror MB may extend only over a fraction of the height of the diodes between which the Bragg mirror MB is positioned. In particular, in the embodiment shown in FIG. 3, two layers CO′ of silicon dioxide extend only over a fraction of the height of the diodes. In particular, each layer CO′ extending only over one portion of the height of the diodes extends depthwise from the front side FAV down to a far end located between the front side FAV and the bottom insulating region ISO.

(34) Each layer CO′ extending only over one portion of the height of the SPADs is suitable for preventing the diffusion of light having a small angle of incidence between the diodes, and in particular an angle of incidence comprised between 0° and Brewster's angle.

(35) An integrated circuit CI according to the invention is thus suitable for eliminating crosstalk between two adjacent SPADs between which a Bragg mirror MB is positioned.

(36) When an SPAD placed on one side CL.sub.1, CL.sub.2 of a Bragg mirror MB receives a photon, this Bragg mirror MB allows the incident parasitic light emitted by the hot carriers generated during an avalanche in this receiver SPAD to be reflected and/or absorbed.

(37) Thus, the parasitic light is not transmitted to the adjacent SPAD placed on the other side CL.sub.1, CL.sub.2 of the Bragg mirror MB. Thus, these two SPADs may operate at the same time and do not run the risk of being deactivated by parasitic light generated by one of these SPADs.

(38) Furthermore, positioning a Bragg mirror MB between the SPADs makes it possible to continue to employ a high excess bias voltage. Specifically, the number of hot carriers generated during the avalanche no longer has any impact on the adjacent SPADs. It is thus therefore possible to design a high-performance photodetector array RES.

(39) Moreover, the integrated circuit may comprise lateral deep trench isolations DTI as shown in FIGS. 2 and 3. Deep trench isolations are well-known to those skilled in the art, who refer to them by the acronym “DTI”.

(40) FIG. 4 shows an electronic device AE comprising an integrated circuit CI according to the invention. The electronic device AE may be a time-of-flight sensor or a device equipped with a time-of-flight sensor.

(41) FIG. 5 illustrates the results of steps of a process for fabricating an integrated circuit according to a first mode of implementation.

(42) FIG. 6 illustrates the results of steps of a process for fabricating an integrated circuit according to a second mode of implementation.

(43) These two modes of implementation firstly comprise forming a plurality of SPADs that are adjacent to one another so as to form a photodetector array. In particular, an initial volume of a first material MAT.sub.1, for example of silicon, is also formed between each adjacent diode of the array.

(44) Each initial volume of the first material MAT.sub.1 extends against the SPADs adjacent to this initial volume over a height equal to that of the adjacent SPADs. Each Bragg mirror is then formed from this volume of silicon.

(45) FIGS. 5 and 6 thus illustrate two modes of implementation for fabricating a Bragg mirror from a volume of the first material MAT.sub.1 between two adjacent diodes of the photodetector array.

(46) The mode of implementation shown in FIG. 5 comprises a step A in which a plurality of trenches TR are etched into the first material MAT.sub.1. In this mode of implementation, the first material MAT.sub.1 is silicon. In particular, in FIG. 5 only two trenches TR have been illustrated. Nevertheless, it is possible to etch, in step A, more than two trenches TR.

(47) Layers CO of a second material MAT.sub.2 are then formed in the trenches TR produced in step B. This second material MAT.sub.2 has a refractive index different from that of the first material MAT.sub.1. In particular, the second material MAT.sub.2 may be silicon dioxide. These layers of second material MAT.sub.2 are formed so as to fill each of these trenches TR.

(48) In step C, another trench TR is then etched into the volume of the first material MAT.sub.1 between the layers of second material MAT.sub.2. Next, in step D, another layer of the second material MAT.sub.2 is formed in the trench TR produced in step C. This layer of second material MAT.sub.2 is formed so as to fill the trench TR produced in step C.

(49) Each trench TR etch is therefore used to form a layer of second material MAT.sub.2. The layers of first material MAT.sub.1 are formed between the layers of second material MAT.sub.2 from the initial volume of the first material MAT.sub.1.

(50) Thus, the width of the trenches TR is chosen depending on the thickness desired for the layers of second material MAT.sub.2. In particular, the width of each trench TR is 142 nm when the second material MAT.sub.2 is silicon dioxide. The arrangement of the trenches TR is chosen so as to form layers of first material MAT.sub.1 of 56 nm thickness when the first material MAT.sub.1 is silicon.

(51) The trenches TR are produced in two different steps (steps A and C) so as to avoid forming fragile layers CO of first material MAT.sub.1 of small thickness between the trenches TR before these trenches TR are filled with the second material MAT.sub.2. In this mode of implementation, the layers of first material MAT.sub.1 are all formed from the initial volume of the first material MAT.sub.1.

(52) Thus, such a process for fabricating the Bragg mirror may allow single-crystal layers of first material MAT.sub.1, and in particular single-crystal layers of silicon, to be preserved. Furthermore, in this mode of implementation, the formation of the layers of silicon dioxide may be implemented simultaneously with a formation of lateral deep trench isolations. Specifically, the layers of silicon dioxide and the lateral deep trench isolations have the same structure and may therefore be formed in the same fabricating step.

(53) As a variant, the mode of implementation shown in FIG. 6 comprises, in step A′, forming by etching a trench TR of sufficient width to contain a plurality of layers CO, and in particular all of the layers, of the Bragg mirror. In particular, the layers CO of material MAT.sub.1, MAT.sub.2 of the Bragg mirror are formed successively in the trench TR from the lateral edges of this trench TR until the trench TR is filled. For example, layers of silicon MAT.sub.1 and layers of silicon dioxide MAT.sub.2 are successively formed in the trench TR.

(54) More particularly, in the example shown in FIG. 6, a trench TR of 538 nm is etched into an initial volume of silicon. This width allows three layers of silicon dioxide MAT.sub.2 of 142 nm and two layers of silicon MAT.sub.1 of 56 nm to be received. In particular, in step B′, two layers of silicon dioxide MAT.sub.2 of 142 nm are formed on each lateral edge of the trench TR in contact with the silicon of the initial volume of silicon.

(55) Next, in step C′, two layers of silicon MAT.sub.1 of 56 nm are formed against the layers of silicon dioxide formed in step B′. Lastly, in step D′, a layer of silicon dioxide MAT.sub.2 of 142 nm is formed between the layers of silicon formed in step C′.

(56) Such a process for fabricating the Bragg mirror has the advantage of etching one and only one trench TR in the first material MAT.sub.1. Specifically, etching a plurality of trenches TR in the first material MAT.sub.1 weakens the latter.

(57) In the two modes of implementation shown in FIGS. 5 and 6, the depth of the etched features may be chosen depending on the height desired for the layers of the Bragg mirror, for example for the layers of silicon dioxide. Thus, the etched features may be formed over the height of the SPADs or over one portion of the height of the SPADs.

(58) In particular, layers CO′ of silicon dioxide extending only over one portion of the height of the SPADs may be formed easily and rapidly. Specifically, for such layers of silicon dioxide, it is not necessary to etch the volume of the first material MAT.sub.1 over the entire height of the diode and the formation of each layer of silicon dioxide is faster because of the smaller height of this layer.

(59) Of course, various variants of and modifications to the present invention will appear obvious to those skilled in the art. For example, nothing would prevent a Bragg mirror comprising an alternation of layers of silicon nitride and of germanium from being used instead of a mirror comprising an alternation of layers of silicon and of silicon dioxide.