Epitaxial structure, preparation method thereof, and LED

Abstract

An epitaxial structure, a preparation method thereof, and a light-emitting diode (LED) are provided. The epitaxial structure includes a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer stacked in sequence.

Claims

1. An epitaxial structure, comprising: a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer stacked in sequence, wherein defects are generated in from the GaN layer caused by lattice constant mismatch between the GaN layer and sapphire substrate, and extend to the defect termination layer through the defect exposure layer, the defect exposure layer is configured to enlarge and expose the defects in the GaN layer, the defect termination layer is configured to change directions of the defects in the defect termination layer and stop the defects from expanding, the GaN layer is a high temperature undoped GaN layer, the defect exposure layer is a low temperature undoped GaN layer or a low temperature undoped InGaN layer, the defect termination layer is a doped GaN layer, and a doping concentration gradually increases in a stacked direction of the epitaxial structure, in the defect termination layer.

2. The epitaxial structure of claim 1, wherein the doped GaN layer is an island-shaped silicon-doped GaN layer or an island-shaped magnesium-doped GaN layer, and the doped GaN layer has the doping concentration greater than 10.sup.19 cm.sup.−3.

3. The epitaxial structure of claim 1, further comprising: an n-type GaN layer, a light-emitting layer, an electron-blocking layer (EBL), and a p-type GaN layer which are sequentially stacked on the defect termination layer.

4. A light-emitting diode (LED), comprising an epitaxial structure comprising a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer stacked in sequence, wherein defects are generated in from the GaN layer caused by lattice constant mismatch between the GaN layer and sapphire substrate, and extend to the defect termination layer through the defect exposure layer, the defect exposure layer is configured to enlarge and expose the defects in the GaN layer, the defect termination layer is configured to change directions of the defects in the defect termination layer and stop the defects from expanding, the GaN layer is a high temperature undoped GaN layer, the defect exposure layer is a low temperature undoped GaN layer or a low temperature undoped InGaN layer, the defect termination layer is a doped GaN layer, and a doping concentration gradually increases in a stacked direction of the epitaxial structure, in the defect termination layer.

5. A method for preparing an epitaxial structure, comprising: preparing a sapphire substrate of the epitaxial structure, and growing a GaN layer of the epitaxial structure on the sapphire substrate; growing a defect exposure layer of the epitaxial structure on the GaN layer; and growing a defect termination layer of the epitaxial structure on the defect exposure layer, wherein defects are generated in from the GaN layer caused by lattice constant mismatch between the GaN layer and sapphire substrate, and extend to the defect termination layer through the defect exposure layer, the defect exposure layer enlarges and exposes the defects in the GaN layer, the defect termination layer changes directions of the defects in the defect termination layer and stops the defects from expanding, and the GaN layer is a high temperature undoped GaN layer, the defect exposure layer is a low temperature undoped GaN layer or a low temperature undoped InGaN layer, the defect termination layer is a doped GaN layer, and a doping concentration gradually increases in a stacked direction of the epitaxial structure, in the defect termination layer.

6. The method for preparing the epitaxial structure of claim 5, wherein growing the GaN layer on the sapphire substrate comprises: growing amorphous GaN on the sapphire substrate; performing heat treatment on the amorphous GaN to obtain single crystal GaN, wherein the heat treatment is performed at a temperature of 950° C.-1050° C.; and growing the GaN layer by using the single crystal GaN as a seed crystal.

7. The method for preparing the epitaxial structure of claim 5, wherein growing the defect exposure layer on the GaN layer comprises: growing GaN or InGaN on the GaN layer to obtain the defect exposure layer, wherein the GaN or InGaN is grown at a temperature of 600° C.-800° C. and with a V-III ratio of 1000-2500; and growing the defect termination layer on the defect exposure layer comprises: growing doped GaN on the defect exposure layer to obtain the defect termination layer, wherein the doped GaN is grown at a temperature of 1000° C.-1100° C. and with a V-III ratio of 4500-7500.

8. The method for preparing the epitaxial structure of claim 7, wherein silicon or magnesium is dopted in growing of the doped GaN, and the doped GaN has the doping concentration greater than 10.sup.19 cm.sup.−3.

9. The method for preparing the epitaxial structure of claim 5, further comprising: growing sequentially on the defect termination layer an n-type GaN layer, a light-emitting layer, an electron-blocking layer (EBL), and a p-type GaN layer.

10. The epitaxial structure of claim 1, wherein the low temperature undoped InGaN layer is In.sub.xGa.sub.1-xN (0.2≤x≤0.35).

11. The epitaxial structure of claim 2, wherein a silicon source of the island-shaped silicon-doped GaN layer is silane (SiH.sub.4), and a magnesium source of the island-shaped magnesium-doped GaN layer is magnesium cerene (Cp.sub.2Mg).

12. The LED of claim 4, wherein the doped GaN layer is an island-shaped silicon-doped GaN layer or an island-shaped magnesium-doped GaN layer, and the doped GaN layer has the doping concentration greater than 10.sup.19 cm.sup.−3.

13. The LED of claim 4, wherein the epitaxial structure further comprises an n-type GaN layer, a light-emitting layer, an electron-blocking layer (EBL), and a p-type GaN layer which are sequentially stacked on the defect termination layer.

14. The LED of claim 4, wherein the low temperature undoped InGaN layer is In.sub.xGa.sub.1-xN (0.2≤x≤0.35).

15. The LED of claim 12, wherein a silicon source of the island-shaped silicon-doped GaN layer is silane (SiH.sub.4), and a magnesium source of the island-shaped magnesium-doped GaN layer is magnesium cerene (Cp.sub.2Mg).

16. The method for preparing the epitaxial structure of claim 5, wherein the doped GaN layer is an island-shaped silicon-doped GaN layer or an island-shaped magnesium-doped GaN layer, and the doped GaN layer has the doping concentration greater than 10.sup.19 cm.sup.−3.

17. The method for preparing the epitaxial structure of claim 5, wherein growing the defect exposure layer on the GaN layer comprises: growing GaN or InGaN on the GaN layer to obtain the defect exposure layer, wherein the GaN or InGaN is grown at a temperature of 600° C.-800° C., with a V-III ratio of 1000-2500, and under a growth pressure of 300 torr-400 torr, wherein an N source of the defect exposure layer is ammonia gas, a Ga source of the defect exposure layer is trimethylgallium or triethylgallium, and a In source of the defect exposure layer is trimethylindium.

18. The epitaxial structure of claim 1, wherein the defect exposure layer has a thickness in a range of 0.5 μm-1 μm.

19. The LED of claim 4, wherein the defect exposure layer has a thickness in a range of 0.5 μm-1 μm.

20. The method for preparing the epitaxial structure of claim 5, wherein the defect exposure layer has a thickness in a range of 0.5 μm-1 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram illustrating a structure with defects in the related art.

(2) FIG. 2 is a schematic diagram illustrating an epitaxial structure in the related art.

(3) FIG. 3 is a schematic diagram illustrating an epitaxial structure of the disclosure.

(4) FIG. 4 is an atomic force microscope (AFM) image illustrating an epitaxial structure in the related art.

(5) FIG. 5 is an AFM image illustrating an epitaxial structure of the disclosure.

(6) FIG. 6 is a schematic structural diagram illustrating a GaN unit cell of the disclosure.

(7) FIG. 7 is a schematic flowchart illustrating a method for preparing an epitaxial structure of the disclosure.

DETAILED DESCRIPTION

(8) In order to clearly and accurately describe the objects, technical solutions, and advantages of the disclosure, the disclosure will be described below in details with reference to accompanying drawings and implementations. It should be understood that, specific implementations herein are merely used to explain the disclosure, and should not be construed as limiting the disclosure.

(9) Hereinafter, implementations to facilitate the understanding of an epitaxial structure of the disclosure are provided with reference to FIG. 3 to FIG. 6.

(10) Generally, as illustrated in FIG. 1 and FIG. 2, an epitaxial structure includes a sapphire substrate 1, an undoped GaN layer (i.e., a buffer layer 2), an N-type GaN layer 3, a stress relief layer 4, a light-emitting layer 5 (a multi-quantum well (MQW) layer), an EBL layer 6 (i.e., an electron-blocking layer, such as a p-type AlGaN layer), and a p-type GaN layer 7 which are stacked in sequence. Since GaN of the buffer layer 2 does not match the sapphire substrate 1 in terms of lattice constants, there is stress when GaN is grown on the sapphire substrate 1, which results in many defects (i.e., V-pits, pits with a V-shaped). Generally, the density of the defects is 10.sup.9-10.sup.10 cm.sup.−2 (i.e., 10.sup.9-10.sup.10 defects per square centimeter area). During growing of subsequent layers, the subsequent layers will continue to grow on the basis of a lattice with V-pits. As a result, the V-pits extend to the outermost P-GaN layer, and the size of the V-pits becomes larger and larger with the extension. It should be noted that, once there are defects in the epitaxial structure, electrons and holes take a shortest path (i.e., a defect path or a leakage path) and do not pass through the light-emitting layer 5, such that the epitaxial structure will not emit lights and an initial voltage is abnormally low, so that the device cannot operate normally.

(11) As illustrated in FIG. 3, an epitaxial structure of the disclosure includes: a sapphire substrate 1, a GaN layer, a defect exposure layer 21, and a defect termination layer 22 arranged in sequence.

(12) According to the disclosure, after the buffer layer 2 (i.e., the GaN layer) is prepared on the sapphire substrate 1, defects in the buffer layer 2 are enlarged and exposed in the defect exposure layer 21. Then directions of the defects are changed in the defect termination layer 22, and the defects are stopped from expanding. In this way, when the subsequent layers (e.g., the N-type GaN layer 3, the stress relief layer 4, the multi-quantum well layer, the electron-blocking layer, the p-type AlGaN layer, and the p-type GaN layer 7) are continuously prepared on the defect termination layer 22, they will not form relatively large V-pits on the basis of V-pits of the buffer layer 2.

(13) As illustrated in FIG. 4, there are multiple V-pits in an atomic force microscope (AFM) image of an existing epitaxial structure (including subsequent layers). In contrast, as illustrated in FIG. 5, there is no V-pit in an AFM image of an epitaxial structure (including the subsequent layers) of the disclosure.

(14) In one implementation of the disclosure, the GaN layer is a high temperature undoped GaN layer, the defect exposure layer 21 is a low temperature undoped GaN layer or a low temperature undoped InGaN layer, and the defect termination layer 22 is an island-shaped doped GaN layer.

(15) The “high temperature” and “low temperature” herein are relative terms. That is, compared to a temperature for preparing the GaN or InGaN of the defect exposure layer 21, the GaN of the buffer layer 2 is prepared at a high temperature, and the temperature is in a range of 950° C.-1050° C. for example. Compared to a temperature for preparing the GaN of the buffer layer 2, the GaN or InGaN of the defect exposure layer 21 is prepared at a low temperature, and the temperature is in a range of 600° C.-800° C. for example. The GaN or InGaN is prepared at a low temperature, which is beneficial to enlarging the V-pits in the buffer layer 2, that is, the size of openings of the V-pits can be enlarged. As such, the V-pits can be exposed in advance, so that the exposed V-pits can be terminated by the defect termination layer 22.

(16) As illustrated in FIG. 6, GaN is a hexagonal crystal system (i.e., a unit cell of GaN is in a shape of a hexagonal prism). Growth rates of GaN along a c-axis and an a-axis are fixed. In the defect termination layer 22, doped GaN is adopted to form an island-shaped structure, that is, an island-shaped doped GaN layer. Since the GaN herein is doped, the growth rate of GaN along the c-axis is different from the growth rate of GaN along the a-axis. Specifically, as a doping concentration increases, the growth rate of GaN along the a-axis gradually increases while the growth rate of GaN along the c-axis gradually decreases. In the epitaxial structure, the c-axis is perpendicular to the sapphire substrate 1, and the a-axis is parallel to the sapphire substrate 1. As the growth rate of doped GaN along the a-axis increases and the growth rate of the doped GaN along the c-axis decreases, the doped GaN tends to grow sideways and expand in a horizontal direction. The V-pits turns as the doped GaN tends to grow sideways. Therefore, the V-pits will not extend into subsequent layers, nor will a larger size V-pits be formed.

(17) In one implementation of the disclosure, the island-shaped doped GaN layer is an island-shaped silicon-doped GaN layer or an island-shaped magnesium-doped GaN layer. The island-shaped doped GaN layer has a doping concentration greater than 10.sup.19 cm.sup.−3.

(18) For example, a silicon source is silane (SiH.sub.4), and a magnesium source is magnesium cerene (Cp.sub.2Mg). A silicon or magnesium concentration (i.e., the doping concentration) is greater than 10.sup.19 cm.sup.−3. In other words, the amount of Si atoms replacing Ga atoms in each cubic centimeter volume is greater than 10.sup.20. Since a Si atom has one more electron than a Ga atom in atomic periphery, doped GaN is the main electron supply material.

(19) In one implementation of the disclosure, as illustrated in FIG. 3, the epitaxial structure further includes an N-type GaN layer 3, a light-emitting layer 5, an EBL layer 6, a p-type GaN layer 7 which are stacked on the defect termination layer 22 sequentially. In another implementation, a stress relief layer 4 is provided between the N-type GaN layer 3 and the light-emitting layer 5.

(20) Based on the above epitaxial structure, a light-emitting diode (LED) is further provided according to implementations of the disclosure. The LED of the implementations of the disclosure includes the epitaxial structure as described in any of the foregoing implementations.

(21) Based on the above epitaxial structure, a method for preparing an epitaxial structure is further provided according to implementations of the disclosure. As illustrated in FIG. 7, the method of the implementations of the disclosure includes the following.

(22) At block S100, a sapphire substrate 1 is prepared, and a GaN layer is grown on the sapphire substrate 1.

(23) In one implementation, the operations at block S100 include the following.

(24) At S110, the sapphire substrate 1 is prepared.

(25) At S120, amorphous GaN is grown on the sapphire substrate 1.

(26) At S130, perform heat treatment on the amorphous GaN to obtain single crystal GaN, where the heat treatment is performed at a temperature of 950° C.-1050° C.

(27) At S140, the GaN layer is grown by using the single crystal GaN as a seed crystal.

(28) At block S200, a defect exposure layer 21 is grown on the GaN layer.

(29) In one implementation, the operations at block S200 include the following.

(30) At S210, GaN or InGaN is grown on the GaN layer to obtain the defect exposure layer 21, where the GaN or InGaN is grown at a temperature of 600° C.-800° C., with a V-III ratio (a molar ratio of an N source and Ga+In sources) of 1000-2500, and under a growth pressure of 300 torr-400 torr. The N source herein uses ammonia gas, the Ga source uses trimethylgallium or triethylgallium, and the In source uses trimethylindium.

(31) For example, the defect exposure layer 21 is a low temperature undoped GaN layer or a low temperature undoped InGaN layer. The specific composition of the low temperature undoped InGaN layer is In.sub.xGa.sub.1-xN (0.2≤x≤0.35). The defect exposure layer 21 has a thickness in a range of 0.5 μm-1 μm.

(32) At block S300, a defect termination layer 22 is grown on the defect exposure layer 21.

(33) In one implementation, the operations at block S300 include the following.

(34) At S310, doped GaN is grown on the defect exposure layer 21 to obtain the defect termination layer 22, where the doped GaN is grown at a temperature of 1000° C.-1100° C. and with a V-III ratio of 4500-7500.

(35) The thickness of the defect termination layer 22 is 1 μm-1.5 μm for example. The grown doped GaN is doped with silicon or magnesium, and has a doping concentration greater than 10.sup.19 cm.sup.−3. The doping concentration increases with time of the extension. That is, as the defect termination layer 22 grows, the concentration of a doping source increases.

(36) At S400, an N-type GaN layer 3, a light-emitting layer 5, an EBL layer 6, and a p-type GaN layer 7 are sequentially grown on the defect termination layer 22.

(37) In one implementation, a stress relief layer 4 is grown between the N-type GaN layer 3 and the light-emitting layer 5.

(38) In sum, according to the disclosure, an epitaxial structure, a preparation method thereof, and an LED are provided. The epitaxial structure includes the sapphire substrate, the GaN layer, the defect exposure layer, and the defect termination layer which are stacked in sequence. After the buffer layer (i.e., the GaN layer) is prepared on the sapphire substrate, defects in the buffer layer are enlarged and exposed in the defect exposure layer. Then directions of the defects are changed in the defect termination layer, and the defects do not continue to expand. In this way, subsequent layers will not form relatively large defects on the basis of the defects in the buffer layer when the subsequent layers are continuously prepared on the defect termination layer.

(39) It is to be understood that, the disclosure is not limited to foregoing illustrative implementations. Those of ordinary skill in the art are able to make several improvements and changes, and these improvements and changes are also deemed as falling in the protection scope of the disclosure.