Solar cell design for improved performance at low temperature

Abstract

A panel including at least one solar cell having a cell comprised of gallium arsenide (GaAs) or indium gallium arsenide (InGaAs) with a back surface field (BSF) comprised of aluminum gallium arsenide (AlGaAs) or indium aluminum gallium arsenide (InAlGaAs) p-type doped for enhanced operation of the solar cell at temperatures less than 50 C. In one example, the back surface field comprises Al.sub.xGa.sub.1-xAs or In.sub.0.01Al.sub.xGa.sub.1-xAs, wherein x is less than about 0.8, for example, 0.2. The back surface field may be p-type doped with zinc (Zn) or carbon (C).

Claims

1. A device, comprising: a panel including at least one solar cell optimized for enhanced operation at temperatures less than about 50 C., the at least one solar cell including: a middle cell comprised of an indium gallium arsenide (InGaAs) emitter and a gallium indium arsenide (GaInAs) base deposited on a back surface field (BSF), wherein the back surface field is comprised of aluminum gallium arsenide (Al.sub.xGa.sub.1-xAs) or indium aluminum gallium arsenide (In.sub.0.01Al.sub.xGa.sub.1-xAs), where x is less than 0.8, the back surface field forms a heterojunction with the GaInAs base having a barrier height of 90 meV or less in a valance band, the back surface field is lattice matched to the GaInAs base for reducing an interfacial recombination velocity of minority carriers at an interface between the back surface field and the GaInAs base, the back surface field is p-type doped with zinc (Zn), and the back surface field has a valence band offset of less than 100 meV relative to the GaInAs base; and a nucleation layer surrounded by and in direct contact with a substrate and a buffer, the buffer being surrounded by and in direct contact with the nucleation layer and a tunnel junction.

2. The device of claim 1, wherein x=0.2.

3. The device of claim 1, wherein the back surface field forms a heterojunction with the base having a lower barrier height as compared to a back surface field comprised of gallium indium phosphide (GaInP).

4. The device of claim 1, wherein the barrier height allows for thermalization of majority carrier holes down to temperatures less than about 50 C., which eliminates resistive losses associated with the barrier.

5. The device of claim 1, wherein the barrier height eliminates resistive losses.

6. The device of claim 1, wherein the solar cell's efficiency increases monotonically with decreasing temperature for a temperature range between room temperature and a temperature of about 150 C.

7. The device of claim 1, further comprising a space vehicle including the panel.

8. A method, comprising: fabricating a panel including at least one solar cell optimized for enhanced operation at temperatures less than about 50 C., the at least one solar cell including: a middle cell comprised of an indium gallium arsenide (InGaAs) emitter and a gallium indium arsenide (GaInAs) base deposited on a back surface field (BSF), wherein the back surface field is comprised of aluminum gallium arsenide (Al.sub.xGa.sub.1-xAs) or indium aluminum gallium arsenide (In.sub.0.01Al.sub.xGa.sub.1-xAs), where x is less than 0.8, the back surface field forms a heterojunction with the GaInAs base having a barrier height of 90 meV or less in a valance band, the back surface field is lattice matched to the GaInAs base for reducing an interfacial recombination velocity of minority carriers at an interface between the back surface field and the GaInAs base, the back surface field is p-type doped with zinc (Zn), and the back surface field has a valence band offset of less than 100 meV relative to the GaInAs base; and a nucleation layer surrounded by and in direct contact with a substrate and a buffer, the buffer being surrounded by and in direct contact with the nucleation layer and a tunnel junction.

9. The method of claim 8, wherein x=0.2.

10. A method, comprising: generating a current using a panel including at least one solar cell optimized for enhanced operation at temperatures less than about 50 C., the at least one solar cell including: a middle cell comprised of an indium gallium arsenide (InGaAs) emitter and a gallium indium arsenide (GaInAs) base deposited on a back surface field (BSF), the back surface field is comprised of aluminum gallium arsenide (Al.sub.xGa.sub.1-xAs) or indium aluminum gallium arsenide (In.sub.0.01Al.sub.xGa.sub.1-xAs), where x is less than 0.8, the back surface field forms a heterojunction with the GalnAs base having a barrier height of 90 meV or less in a valance band, the back surface field is lattice matched to the GaInAs base for reducing an interfacial recombination velocity of minority carriers at an interface between the back surface field and the GaInAs base, the back surface field is p-type doped with zinc (Zn), and the back surface field has a valence band offset of less than 100 meV relative to the GaInAs base; and a nucleation layer surrounded by and in direct contact with a substrate and a buffer, the buffer being surrounded by and in direct contact with the nucleation layer and a tunnel junction.

11. The method of claim 10, wherein x=0.2.

12. A device, comprising: a panel including at least one solar cell having a middle cell (MC) with an emitter, a base and a back surface field (BSF) for enhanced operation of the solar cell at temperatures less than about 50 C.; wherein the base is comprised of gallium indium arsenide (GaInAs) deposited on the back surface field, the emitter is comprised of indium gallium arsenide (InGaAs) deposited on the base, and the back surface field is comprised of aluminum gallium arsenide (Al.sub.xGa.sub.1-xAs) or indium aluminum gallium arsenide (In.sub.0.01Al.sub.xGa.sub.1-xAs), where x is less than 0.8, such that: the back surface field has a valence band offset of below 100 meV relative to the GaInAs base; the back surface field has either a type-I or type-II band alignment relative to the GaInAs base; the back surface field maintains a conduction band offset of greater than 0 meV relative to the GaInAs base, so that the back surface field acts as a hetero-step passivation layer and reflects minority carrier electrons back to a p-n junction to be collected; the back surface field is lattice matched to the GaInAs base for reducing an interfacial recombination velocity of the minority carriers at an interface between the back surface field and the base; and the back surface field is p-type doped with zinc (Zn), and a nucleation layer surrounded by and in direct contact with a substrate and a buffer, the buffer being surrounded by and in direct contact with the nucleation layer and a tunnel junction.

13. The device of claim 12, wherein x=0.2.

14. The method of claim 8, wherein the back surface field forms a heterojunction with the base having a lower barrier height as compared to a back surface field comprised of gallium indium phosphide (GaInP).

15. The method of claim 8, wherein the barrier height allows for thermalization of majority carrier holes down to temperatures less than about 50 C., which eliminates resistive losses associated with the barrier.

16. The method of claim 8, wherein the barrier height eliminates resistive losses.

17. The method of claim 10, wherein the back surface field forms a heterojunction with the base having a lower barrier height as compared to a back surface field comprised of gallium indium phosphide (GaInP).

18. The method of claim 10, wherein the barrier height allows for thermalization of majority carrier holes down to temperatures less than about 50 C., which eliminates resistive losses associated with the barrier.

19. The device of claim 1, wherein the back surface field is either type-I or type-II band alignment relative to the GaInAs base.

20. The device of claim 1, wherein the back surface field maintains a band offset for the conduction band of greater than 0 meV relative to the GaInAs base.

Description

DRAWINGS

(1) Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

(2) FIGS. 1A and 1B are layer schematics of triple junction solar cells, illustrating a baseline solar cell in FIG. 1A and a new solar cell in FIG. 1B.

(3) FIG. 2 is a graph of LIV (light-current-voltage) curves measured from 150 C. to 30 C. for the baseline solar cell.

(4) FIGS. 3A and 3B are graphs providing a comparison of bandgap diagrams for the back surface fields of the new and baseline solar cells to a base heterojunction.

(5) FIGS. 4A, 4B and 4C are graphs showing possible band alignments for different material situations that improve low-temperature performance.

(6) FIG. 5 is a graph of LIV curves measured from 150 C. to 30 C. for the new solar cell.

(7) FIG. 6 is a graph of maximum power as a function of temperature for the back surface fields of the baseline and new solar cells.

(8) FIG. 7A illustrates a method of fabricating a solar cell, solar cell panel and/or satellite.

(9) FIG. 7B illustrates a resulting satellite having a solar cell panel comprised of solar cells.

(10) FIG. 8 is an illustration of the solar cell panel in the form of a functional block diagram.

DETAILED DESCRIPTION

(11) In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific example in which the disclosure may be practiced. It is to be understood that other examples may be utilized and structural changes may be made without departing from the scope of the present disclosure.

(12) Overview

(13) This disclosure describes a design rule for solar cells that improves their performance at low temperatures, for example, less than 50 C.

(14) Specifically, the main constraint in low temperature performance is the presence of heterojunction resistance that increases exponentially with decreasing temperature. The main heterojunction resistance in a standard triple junction (3J) solar cell occurs between a middle cell base and BSF. The offset in materials in the valence band acts as a rectification diode. At nominal operating temperatures, the barrier is easily surmounted by photogenerated holes to be collected in the circuit. At low temperatures, the interrupt, or hetero-step, in the valence band energies acts as a rectification barrier.

(15) There have been previous attempts to address this issue of 3J solar cell performance at low temperatures.

(16) One attempt was to use the standard 3J space solar cells in low temperatures and tolerate any low temperature performance degradations.

(17) Another attempt was to change the p-type doping in the middle cell base near an interface with the middle cell BSF. Changes in doping can narrow the width of the heterojunction barrier, allowing for increased tunneling transport across the heterojunction barrier and reduced heterojunction resistance. This mitigates the issue, but is tenuous at best depending on the temperature and exact doping level.

(18) This disclosure reduces this heterojunction resistance by replacing the baseline BSF material to reduce, eliminate, or re-orient the heterojunction barrier. Specifically, one example described in this disclosure describes a new solar cell having a middle cell BSF comprised of AlGaAs or InAlGaAs for improving performance of the solar cell at temperatures less than about 50 C. In one example, the new BSF comprises Al.sub.xGa.sub.1-xAs or In.sub.0.01Al.sub.xGa.sub.1-xAs, wherein x=0.2.

(19) Experimental data demonstrates an increase in efficiency of 25% for the new BSF at 150 C. relative to the baseline BSF. In fact, the new solar cell performance is 20-30% greater than the baseline solar cell.

Technical Description

(20) FIGS. 1A and 1B are layer schematics, each showing a cross-section of a device comprising baseline and new III-V 3J solar cells 100a, 100b, respectively.

(21) FIG. 1A shows the baseline I-V 3J solar cell 100a as currently manufactured. The solar cell 100a includes a 5-15 m p-doped germanium (p-Ge) substrate 102, upon which is deposited and/or fabricated a standard (std) nucleation layer 104, a buffer layer 106, a lower tunnel junction 108, a GaInP BSF 110a that is doped with Zn, a middle cell (MC) comprised of a GaInAs base 112 and an InGaAs emitter 114, an MC window 116, a top tunnel junction 118, a top cell (TC) BSF 120 that is comprised of GaInP, a TC comprised of GaInP 122, an aluminum indium phosphide (AlInP) window 124, and a GaInAs cap 126.

(22) FIG. 1B shows the new III-V 3J solar cell 100b according to this disclosure, which substitutes an AlGaAs BSF 110b that is p-type doped with Zn, for the GaInP BSF 110a in the middle cell of the baseline solar cell 100a. In one example, the BSF 110b comprises A.sub.xGa.sub.1-xAs, wherein x=0.2. In an alternative example, the BSF 110b may comprise In.sub.0.01Al.sub.xGa.sub.1-xAs, wherein x=0.2. In an alternative example, the BSF 110b may be p-type doped with carbon (C). The solar cells 100a, 100b may include other features not illustrated for the purposes of simplifying the drawings, such as an anti-reflection coating, front and back metal contacts, etc.

(23) FIG. 2 is a graph of current (A) vs. voltage (V) illustrating the consequences of using the GaInP BSF 110a in the middle cell of the baseline solar cell 100a. From room temperature down to 50 C., the LIV curves are well behaved, with linear behavior near Voc (open circuit voltage). The efficiency increases with decreasing temperature in this range due to the increasing Voc. However, for temperatures less than 50 C., the LIV show non-linearities near the Voc. These non-linearities result in losses in the fill factor and significant losses in solar cell 100a performance. This non-linearity is caused by a leaky diode rectification.

(24) FIGS. 3A and 3B are graphs providing a comparison of bandgap diagrams for the AlGaAs BSF 110b and the GaInP BSF 110a, both of which form a heterojunction with the GaInAs base 112.

(25) As shown in FIG. 3A, modeling indicates that the AlGaAs BSF 110b forms a heterojunction with the middle cell base 112 having a lower barrier height of about 90 meV or less in the valence band, as compared to the GaInP BSF 110a. The lower barrier height allows for thermalization of majority carrier holes down to much lower temperatures, i.e., temperatures less than about 50 C., which eliminates resistive losses associated with the barrier.

(26) As shown in FIG. 3B, the GaInP BSF 110a forms a significantly higher heterojunction barrier height of 300 meV in the valance band. At temperatures above 50 C., there is sufficient thermal energy for majority carrier holes to thermalize over this barrier. At temperatures less than 50 C., there is insufficient thermal energy, causing heterojunction resistance that manifests itself in the form a nonlinear behavior in the solar cell 100a LIV curve near Voc. Therefore, increasing doping does not eliminate the issue.

(27) FIGS. 4A, 4B and 4C are graphs showing possible band alignments for different material situations that improve low-temperature performance, e.g., below 50 C.

(28) FIG. 4A shows a similar case to that in FIG. 3A with a type-I offset where the valence band is near to that of the base material and a small offset of less than 100 meV is obtained. This limit is important as at temperatures below 50 C., the energy of the hole to surmount the barrier is approximately no more than five times the standard thermal energy of kT or 19.3 meV at 50 C.

(29) FIG. 4B shows a potential design where no offset occurs in the valence band between the base and BSF.

(30) FIG. 4C shows a potential design where the offset is type-II and there is a negative offset and the BSF valence band energy is higher than that of the base material. Again, a limitation of near 100 meV exists for a type-II band alignment material as the hetero-step offset will form a rectification barrier.

(31) For material selection, the actual energy level of the BSF material varies and are well understood by those skilled in the art of III-V semiconductor devices. Selection of BSF materials for GaAs or GaInAs base subcells would be best chosen from materials that follow the main criteria: first, they must have a valence band offset of below 100 meV; second, they may be either type-I or type-II band alignment relative to the base; and third, they must maintain a band offset of greater than 0 meV for the conduction band so that they continue to act as a hetero-step passivation layer and reflect minority carrier electrons away from the interface and back to the p-n junction to be collected.

(32) Lastly, the choice of material is superior if a lattice constant of the BSF is near or about the same as a lattice constant of the base. This criterion allows for the smallest number of defects to be created at the interface and the BSF reduces the interfacial recombination velocity of the minority carriers.

(33) As an example for GaAs and GaInAs, the best choices for BSF materials could be selected from: Al.sub.xGa.sub.1-xAs, where x is less than 0.8; Al.sub.xGa.sub.1-x-yIn.sub.yAs, where x is less than 0.8 and y is chosen to allow the alloy BSF to approximately match the base material lattice constant; Al.sub.xGa.sub.1-xAs.sub.1-ySb.sub.y, where x is less than 0.8 and y is chosen to match the type-I or type-II alignment. Various other combinations may be chosen from multinary alloys of GaNAs, AlGaAs, AlGaAsSb, AlGaPAs, AlGaPAsSb, AlGaInAs, AlGaInPAs, AlGaInPAsSb, AlGaAsBi, AlGaInPAsBi, BGaAs, BAlGaAs, BAlGaInAs, etc., and further examples of material alloys of combinations above. Further combinations may be proposed for subcells of other base materials, such as GaInP, AlGaInP, AlGaInAs, GaInNAs, GaInNAsSb, InPGaInAs, and GaAsSb, so long as the criteria outlined above are followed.

(34) FIG. 5 is a graph of current (A) vs. voltage (V) illustrating the effect of the reduced heterojunction barrier on the new solar cell's 100b performance. In contrast to the baseline solar cell 100a with the GaInP BSF 110a illustrated in FIG. 2, the new solar cell 100b with the AlGaAs BSF 110b shows well behaved LIV curves, particularly near Voc, down to the lowest measured temperature of 150 C. The new solar cell 100b with the AlGaAs BSF 110b still exhibits increasing Voc with decreasing temperature.

(35) FIG. 6 is a graph of maximum power (mW/cm.sup.2) vs. temperature (C) that compares the baseline solar cell 100a with the GaInP BSF 110a to the new solar cell 100b with the AlGaAs BSF 110b.

(36) For the GaInP BSF 110a case, the efficiency increases due to the increasing voltage for the baseline solar cell 100a from room temperature to 50 C. From temperatures of 50 C. to 150 C., the efficiency of the baseline solar cell 100a decreases with decreasing temperature due to the high heterojunction resistance and associated non-linearities near Voc.

(37) For the AlGaAs BSF 110b case, the efficiency of the new solar cell 100b increases monotonically with decreasing temperature for a temperature range between room temperature of about 20 C. to 30 C. and a temperature of about 150 C. This sharply contrasting behavior results in a divergence in low temperature cell performance starting at 50 C. At 150 C., the difference in new solar cell 100b efficiency is 25%, which is a significant improvement for solar cells 100a, 100b that operate in these conditions.

(38) Alternatives and Modifications

(39) The description set forth above has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the examples described. Many alternatives and modifications may be used in place of the specific description set forth above.

(40) For example, although AlGaAs and InAlGaAs are the materials studied most in depth thus far, multiple other potential materials could also be used. Compositions of AlGaAs other than Al.sub.0.2Ga.sub.0.8As and InAlGaAs other than In.sub.0.01Al.sub.0.2Ga.sub.0.8As may be used, as well as InGaAsP alloy lattice matched to Ge/GaAs substrates.

(41) In another example, although this disclosure describes the widely adopted triple junction solar cell, it could be broadened to cover any instance of a single junction, double junction, or other multiple junction solar cell designed to include materials that lower heterojunction resistance for majority carriers. This would include any BSF-to-base transition or window-to-emitter transition for the valence or conduction bands, respectively.

(42) In yet another example, although this disclosure describes the new solar cell 100b generally, and BSF 110b specifically, as comprising certain materials, alternatives may describe the new solar cell 100b and BSF 110b as consisting of, or consisting essentially of, these or other materials.

(43) Similarly, although this disclosure describes the new solar cell 100a performing in a desired manner at a temperature of about 50 C. or less, alternatives may describe the new solar cell 100 as performing at a temperature of about 100 C. or less, 150 C. or less, or other lesser temperatures.

(44) Aerospace Applications

(45) Examples of the disclosure may be described in the context of a method 700 of fabricating a solar cell, solar cell panel and/or aerospace vehicle such as a satellite, comprising steps 702-714, as shown in FIG. 7A, wherein the resulting satellite 716 comprised of various systems 718 and a body 720, including a panel 722 comprised of an array 724 of one or more solar cells 100b is shown in FIG. 7B.

(46) As illustrated in FIG. 7A, during pre-production, exemplary method 700 may include specification and design 702 of the satellite 716, and material procurement 704 for same. During production, component and subassembly manufacturing 706 and system integration 708 of the satellite 716 takes place, which include fabricating the satellite 716, panel 722, array 724 and solar cells 100b. Thereafter, the satellite 716 may go through certification and delivery 710 in order to be placed in service 712. The satellite 716 may also be scheduled for maintenance and service 714 (which includes modification, reconfiguration, refurbishment, and so on), before being launched.

(47) Each of the processes of method 700 may be performed or carried out by a system integrator, a third party, and/or an operator (e.g., a customer). For the purposes of this description, a system integrator may include without limitation any number of manufacturers and major-system subcontractors; a third party may include without limitation any number of venders, subcontractors, and suppliers; and an operator may be a satellite company, military entity, service organization, and so on.

(48) As shown in FIG. 7B, the satellite 716 fabricated by exemplary method 700 may include various systems 718 and a body 720. Examples of the systems 718 included with the satellite 716 include, but are not limited to, one or more of a propulsion system 726, an electrical system 728, a communications system 730, and a power system 732. Any number of other systems also may be included.

(49) Functional Block Diagram

(50) FIG. 8 is an illustration of the panel 722 in the form of a functional block diagram, according to one example. The panel 722 is comprised of the array 724, which is comprised of one or more of the solar cells 100b individually attached to the panel 722. At least one of the solar cells 100b has an AlGaAs BSF 110b. Each of the solar cells 100b absorbs light 800 from a light source 802 and generates an electrical output 804 in response thereto.