DEVICE COMPRISING AN ACOUSTIC LAYER AND VIA INTERCONNECT
20260101673 · 2026-04-09
Inventors
- Sebastian BRUNNER (Graz, AT)
- Thomas Metzger (Munich, DE)
- Maximilian SCHIEK (Puchheim, DE)
- Willi AIGNER (Moosinning, DE)
- Ralph DURNER (München, DE)
- Christian CERANSKI (München, DE)
- Marc ESQUIUS MOROTE (Munich, DE)
- Horst Droescher (Frauental an der Laßnitz, AT)
Cpc classification
H10N30/874
ELECTRICITY
International classification
Abstract
A device comprising a lid layer; an acoustic layer coupled to the lid layer, wherein the acoustic layer comprises: a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer; a cavity located between the lid layer and the piezoelectric layer; a substrate coupled to the dielectric layer of the acoustic layer; and at least one via interconnect coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate.
Claims
1. A device comprising: a lid layer; an acoustic layer coupled to the lid layer, wherein the acoustic layer comprises: a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer; a cavity located between the lid layer and the piezoelectric layer; a substrate coupled to the dielectric layer of the acoustic layer; and at least one via interconnect coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate.
2. The device of claim 1, wherein the dielectric layer comprises a first acoustic impedance, and wherein the at least one material layer comprises a second acoustic impedance that is different from the first acoustic impedance.
3. The device of claim 1, wherein at least part of the dielectric layer and the at least one material layer are configured as an acoustic mirror.
4. The device of claim 1, wherein the at least one via interconnect is configured to provide an electrical path through the dielectric layer and the substrate.
5. The device of claim 1, wherein the lid layer further comprises a lid via interconnect that extends through the lid layer.
6. The device of claim 5, wherein the lid via interconnect is coupled to the plurality of interconnects of the acoustic layer.
7. The device of claim 1, further comprising a plurality of metallization interconnects coupled to the at least one via interconnect.
8. The device of claim 1, wherein the at least one via interconnect comprises: a first via interconnect that extends through the dielectric layer; a pad coupled to the first via interconnect; and a second via interconnect that extends through the substrate, wherein the second via interconnect is coupled to the pad.
9. The device of claim 1, wherein the lid layer is coupled to the acoustic layer such that a hermetic seal is provided between the lid layer and the acoustic layer.
10. The device of claim 1, wherein the lid layer comprises silicon, glass, fused silica, ceramic, polymer, or a combination thereof.
11. The device of claim 1, wherein the device includes an acoustic wave device.
12. The device of claim 1, further comprising at least one thermal via interconnect extending through the substrate, wherein the at least one thermal via interconnect is free of any electrical connection with the piezoelectric layer.
13. The device of claim 1, wherein the plurality of interconnects are configured as electrodes.
14. The device of claim 1, wherein the at least one material layer includes tungsten.
15. The device of claim 1, wherein the piezoelectric layer includes aluminum nitride (Aln) or aluminum scandium nitride (AlScN).
16. A method for fabricating an acoustic device, comprising: providing a lid layer; coupling an acoustic layer to the lid layer, wherein the acoustic layer comprises: a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer, wherein the acoustic layer is coupled to the lid layer such that a cavity is located between the lid layer and the piezoelectric layer; coupling a substrate to the dielectric layer of the acoustic layer; and forming at least one via interconnect that is coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate.
17. The method of claim 16, wherein the dielectric layer comprises a first acoustic impedance, and wherein the at least one material layer comprises a second acoustic impedance that is different from the first acoustic impedance.
18. The method of claim 16, wherein at least part of the dielectric layer and the at least one material layer are configured as an acoustic mirror.
19. The method of claim 16, wherein the at least one via interconnect is configured to provide an electrical path through the dielectric layer and the substrate.
20. The method of claim 16, wherein the at least one via interconnects comprises: a first via interconnect that extends through the dielectric layer; a pad coupled to the first via interconnect; and a second via interconnect that extends through the substrate, wherein the second via interconnect is coupled to the pad.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.
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DETAILED DESCRIPTION
[0027] In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown as block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.
[0028] The present disclosure describes a device comprising a lid layer; an acoustic layer coupled to the lid layer, wherein the acoustic layer comprises: a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer; a cavity located between the lid layer and the piezoelectric layer; a substrate coupled to the dielectric layer of the acoustic layer; and at least one via interconnect coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate. The use of the at least one via interconnect helps provide an electrical and/or thermal path for to and/or from the piezoelectric layer.
Exemplary Device Comprising an Acoustic Layer and at Least One Via Interconnect
[0029]
[0030] The device 100 includes a lid layer 102 and a device base 107. The device base 107 may include the acoustic layer 101, the substrate 104, at least one dielectric layer 106, a plurality of via interconnects 105, and a plurality of metallization interconnects 150. The acoustic layer 101 may include the at least one dielectric layer 106, a piezoelectric layer 108, a plurality of interconnects 130, a plurality of interconnects 131, and at least one material layer 109. The plurality of interconnects 130 and/or the plurality of interconnects 131 may be configured as electrodes.
[0031] The at least one material layer 109 and a portion of the at least one dielectric layer 106 may define an acoustic mirror portion 190. The acoustic mirror portion 190 may be configured as a Bragg mirror, to help reduce the loss of acoustic energy. For example, the acoustic mirror portion 190 may be configured to reflect acoustic energy back towards the piezoelectric layer 108. The at least one dielectric layer 106 includes a first acoustic impedance (e.g., first acoustic impedance value, low acoustic impedance value) and the at least one material layer 109 includes a second acoustic impedance (e.g., second acoustic impedance value, high acoustic impedance value) that is different from the first acoustic impedance. For example, the at least one material layer 109 may have a higher acoustic impedance than the acoustic impedance of the at least one dielectric layer 106. In some implementations, the at least one dielectric layer 106 may include silicon dioxide (SiO.sub.2). In some implementations, the at least one material layer 109 may include tungsten. The at least one material layer 109 may include a different material from the plurality of interconnects 130, the plurality of interconnects 131 and/or the plurality of via interconnects 105. The at least one material layer 109 may be an acoustic mirror layer. The at least one material layer 109 may include multiple material layers (e.g., multiple acoustic mirror layers) that vertically overlap with the piezoelectric layer 108. Different implementations may have different numbers of material layers. In some implementations, the at least one material layer 109 may include several vertical stacks of acoustic mirror layers. The at least one material layer 109 may not be electrically coupled to the piezoelectric layer 108, the plurality of interconnects 130, the plurality of interconnects 131 and/or the plurality of via interconnects 105.
[0032] Some of via interconnects from the plurality of via interconnects are coupled to the plurality of interconnects 130 and/or the plurality of interconnects 131. Some of via interconnects from the plurality of via interconnects 105 may extend through the at least one dielectric layer 106 and/or the substrate 104. The substrate 104 may include silicon (Si). Some of via interconnects from the plurality of via interconnects 105 may extend through the substrate 104. Some of via interconnects from the plurality of via interconnects 105 may vertically overlap with the acoustic mirror portion 190. Some of the via interconnects from the plurality of via interconnects 105 may vertically overlap with the piezoelectric layer 108. The plurality of via interconnects 105 may include a via interconnect 105a, a via interconnect 105b, a via interconnect 105c and a via interconnect 105d. The via interconnect 105a is coupled to the plurality of interconnects 131. The via interconnect 105d is coupled to the plurality of interconnects 131. The via interconnect 105a extends through the substrate 104 and the at least one dielectric layer 106. The via interconnect 105d extends through the substrate 104 and the at least one dielectric layer 106. The via interconnect 105d is coupled to the plurality of interconnects 131. In some implementations, the via interconnect 105a and/or the via interconnect 105d may be configured to be electrically coupled to the plurality of interconnects 130, the plurality of interconnects 131 and/or the piezoelectric layer 108. Thus, the via interconnect 105a and/or the via interconnect 105d may be configured to provide an electrical path through the device base 107 of the device 100.
[0033] The via interconnect 105b extends through the substrate 104 and part of the at least one dielectric layer 106. The via interconnect 105b vertically overlaps with at least part of the acoustic mirror portion 190. The via interconnect 105b vertically overlaps with at least a portion of the piezoelectric layer 108. The via interconnect 105c extends through the substrate 104 and part of the at least one dielectric layer 106. The via interconnect 105c vertically overlaps with at least part of the acoustic mirror portion 190. The via interconnect 105c vertically overlaps with at least a portion of the piezoelectric layer 108. In some implementations, the via interconnect 105b and/or the via interconnect 105c may be free of any electrical connection with the piezoelectric layer 108. In some implementations, the via interconnect 105b and/or the via interconnect 105c may be configured to dissipate heat away from the piezoelectric layer 108. The via interconnect 105b and/or the via interconnect 105c may be examples of thermal via interconnects.
[0034] The plurality of interconnects 130, the plurality of interconnects 131 and/or the piezoelectric layer 108 are located on a first side of the device base 107. The plurality of interconnects 130, the plurality of interconnects 131 and/or the piezoelectric layer 108 may be located on a first surface of the at least one dielectric layer 106. The acoustic mirror portion 190 may be located between (i) the piezoelectric layer 108 and (ii) the via interconnect 105b and/or the via interconnect 105c. The plurality of metallization interconnects 150 are coupled to the plurality of via interconnects 105. The plurality of metallization interconnects 150 may be located in and/or on a second side of the device base 107. The second side of the device base 107 may be opposite to the first side of the device base 107. The plurality of metallization interconnects 150 are coupled to the plurality of solder interconnects 112. The plurality of metallization interconnects 150 may include a plurality of pad interconnects. The plurality of metallization interconnects 150 include a metallization interconnect 150a, a metallization interconnect 150bc and a metallization interconnect 150d. The metallization interconnect 150a is coupled to the via interconnect 105a. The metallization interconnect 150bc is coupled to the via interconnect 105b and the via interconnect 105c. The metallization interconnect 150bc may be one pad interconnect for the via interconnect 105b and the via interconnect 105c. The increase in lateral size of the metallization interconnect 150bc helps dissipate heat away from the piezoelectric layer 108. The metallization interconnect 150d is coupled to the via interconnect 105d.
[0035] A metal layer 121 is formed and/or coupled to a surface of the lid layer 102. The lid layer 102 may include glass, silicon, fused silica, ceramic, or a combination thereof. The lid layer 102 is coupled to the device base 107 through the metal layer 121. The metal layer 121 may be coupled to a metal layer (not shown) of the device base 107. The metal layer 121 helps provide a hermetic seal between the lid layer 102 and the device base 107. The metal layer 121 may also help provide shielding (e.g., electromagnetic interference shielding) for the acoustic layer 101. A cavity 120 is located between the lid layer 102 and the piezoelectric layer 108. The cavity 120 may be formed in the lid layer 102. The cavity 120 may be located between (i) the lid layer 102 and (ii) the plurality of interconnects 130 and/or the plurality of interconnects 131. A cavity may be at least one region that is free of a solid material. A cavity may be occupied by a gas (e.g., air).
[0036]
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[0038] The device 200 includes a plurality of via interconnects 105, a plurality of pad interconnects 205 and a plurality of metallization interconnects 150. The plurality of via interconnects 105 are coupled to the plurality of interconnects 130, the plurality of interconnects 131 and/or the piezoelectric layer 108. The plurality of via interconnects 105 includes a via interconnect 105a, a via interconnect 105b, a via interconnect 105c and a via interconnect 105d. The via interconnect 105a is coupled to the plurality of interconnects 130, the plurality of interconnects 131 and/or the piezoelectric layer 108. The via interconnect 105d is coupled to the plurality of interconnects 130, the plurality of interconnects 131 and/or the piezoelectric layer 108. The plurality of pad interconnects 205 may include a pad interconnect 205a, a pad interconnect 205b, a pad interconnect 205c and a pad interconnect 205d. The plurality of pad interconnects 205 may be located in the at least one dielectric layer 106.
[0039] The via interconnect 105a may include a via interconnect 105aa, a pad interconnect 205a and a via interconnect 105ab. The pad interconnect 205a may be located between the via interconnect 105aa and the via interconnect 105ab. The pad interconnect 205a may have a width that is greater than a width of the via interconnect 105aa and/or a width of the via interconnect 105ab. The via interconnect 105aa may be a first via interconnect portion of the via interconnect 105a. The via interconnect 105ab may be a second via interconnect portion of the via interconnect 105a. The via interconnect 105aa may extend through the at least one dielectric layer 106. The pad interconnect 205a may be located in the at least one dielectric layer 106. The via interconnect 105ab may extend through the substrate 104.
[0040] The via interconnect 105d may include a via interconnect 105da, a pad interconnect 205d and a via interconnect 105db. The pad interconnect 205d may be located between the via interconnect 105da and the via interconnect 105db. The pad interconnect 205d may have a width that is greater than a width of the via interconnect 105da and/or a width of the via interconnect 105db. The via interconnect 105da may be a first via interconnect portion of the via interconnect 105d. The via interconnect 105db may be a second via interconnect portion of the via interconnect 105d. The via interconnect 105da may extend through the at least one dielectric layer 106. The pad interconnect 205d may be located in the at least one dielectric layer 106. The via interconnect 105db may extend through the substrate 104.
[0041] The plurality of metallization interconnects 150 may include a plurality of pad interconnects. The plurality of metallization interconnects 150 may include a metallization interconnect 150a, a metallization interconnect 150b, a metallization interconnect 150c and a metallization interconnect 150d. The metallization interconnect 150a is coupled to the via interconnect 105ab. The metallization interconnect 150b is coupled to the via interconnect 105b. The metallization interconnect 150c is coupled to the via interconnect 105c. The metallization interconnect 150d is coupled to the via interconnect 105db.
[0042]
[0043] The plurality of pad interconnects 205 may be a byproduct of the process used to fabricate the device. Different implementations may have pad interconnects from the plurality of pad interconnects 205, with different shapes and/or sizes. In some implementations, the plurality of via interconnects 105, the plurality of pad interconnects 205, and/or the plurality of metallization interconnects 150 may include one or more seed layers. Examples of devices with interconnects with seed layers and/or other interconnects are described below.
[0044]
[0045] The device 300 include a plurality of via interconnects 105. The device 300 may include a plurality of pad interconnects 205. The plurality of via interconnects 105 may include a seed layer 305. The plurality of pad interconnects 205 may include a seed layer 305. The seed layer 305 may include one or more seed layers. The seed layer 305 may include titanium and/or copper. A metal layer 350 may be coupled to the plurality of metallization interconnects 150. The metal layer 350 may include a different material from the plurality of metallization interconnects 150. The seed layer 305 may be coupled to the plurality of interconnects 131. In some implementations, the seed layer 305 may not be distinguishable from the plurality of via interconnects 105, the plurality of pad interconnects 205 and/or the plurality of metallization interconnects 150. The seed layer 305 may be located on the side wall of the plurality of interconnects. In some implementations, there may be more than one metal layer 350. Each additional metal layer may include different materials.
[0046] The lid layer 102 may be coupled to the device base 107 through the metal layer 121, the metal layer 330 and a metal layer of the device base 107, and may help provide a hermetic seal between the lid layer 102 and the device base 107. The metal layer 121, the metal layer 330 and the metal layer of the device base 107 may include the same materials and/or different materials.
[0047]
[0048] The device 400 may be coupled to other components through the plurality of interconnects 403. For example, a substrate (e.g., laminated substrate) may be coupled to the plurality of interconnects 403 through solder interconnects. In another example, an integrated device may be coupled to the plurality of interconnects 403 through solder interconnects.
[0049] A plurality of metallization interconnects (e.g., 150) may include a plurality of redistribution interconnects. A redistribution interconnect may include portions that have a U-shape or V-shape. The terms U-shape and V-shape shall be interchangeable. The terms U-shape and V-shape may refer to the side profile shape of the interconnects, metallization interconnects and/or redistribution interconnects. The U-shape interconnect (e.g., U-shape side profile interconnect) and the V-shape interconnect (e.g., V-shape side profile interconnect) may have a top portion and a bottom portion. A bottom portion of a U-shape interconnect (or a V-shape interconnect) may be coupled to a top portion of another U-shape interconnect (or a V-shape interconnect). In some implementations, a process for fabricating redistribution interconnects may form the U-shape interconnect (or the V-shape interconnect).
[0050] As mentioned above, a device may be an integrated device. In some implementations, a device may be implemented to be electrically coupled to an integrated device. An integrated device may include a die (e.g., semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, power management processor, and/or combinations thereof. An integrated device may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc. . . . ). An integrated device may include an input/output (I/O) hub. An integrated device may include transistors. An integrated device may be an example of an electrical component and/or electrical device.
[0051] In some implementations, an integrated device may be a chiplet. A chiplet may be fabricated using a process that provides better yields compared to other processes used to fabricate other types of integrated devices, which can lower the overall cost of fabricating a chiplet. Different chiplets may have different sizes and/or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different width and/or spacing). In some implementations, several chiplets may be used to perform the functionalities of one or more chips (e.g., one more integrated devices). As mentioned above, using several chiplets that perform several functions may reduce the overall cost of a package relative to using a single chip to perform all of the functions of a package. In some implementations, one or more of the chiplets and/or one or more of integrated devices described in the disclosure may be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device may be fabricated using a first technology node, and a chiplet may be fabricated using a second technology node that is not as advanced as the first technology node. In such an example, the integrated device may include components (e.g., interconnects, transistors) that have a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) that have a second minimum size, where the second minimum size is greater than the first minimum size. In some implementations, a first integrated device and a second integrated device of a package, may be fabricated using the same technology node or different technology nodes. In some implementations, a chiplet and another chiplet of a package, may be fabricated using the same technology node or different technology nodes.
[0052] A technology node may refer to a specific fabrication process and/or technology that is used to fabricate an integrated device and/or a chiplet. A technology node may specify the smallest possible size (e.g., minimum size) that can be fabricated (e.g., size of a transistor, width of trace, gap width between two transistors). Different technology nodes may have different yield loss. Different technology nodes may have different costs. Technology nodes that produce components (e.g., trace, transistors) with fine details are more expensive and may have higher yield loss, than a technology node that produces components (e.g., trace, transistors) with details that are less fine. Thus, more advanced technology nodes may be more expensive and may have higher yield loss, than less advanced technology nodes. When all of the functions of a package are implemented in single integrated devices, the same technology node is used to fabricate the entire integrated device, even if some of the functions of the integrated devices do not need to be fabricated using that particular technology node. Thus, the integrated device is locked into one technology node. To optimize the cost of a package, some of the functions can be implemented in different integrated devices and/or chiplets, where different integrated devices and/or chiplets may be fabricated using different technology nodes to reduce overall costs. For example, functions that require the use of the most advanced technology node may be implemented in an integrated device, and functions that can be implemented using a less advanced technology node can be implemented in another integrated device and/or one or more chiplets. One example, would be an integrated device, fabricated using a first technology node (e.g., most advanced technology node), that is configured to provide compute applications, and at least one chiplet, that is fabricated using a second technology node, that is configured to provide other functionalities, where the second technology node is not as costly as the first technology node, and where the second technology node fabricates components with minimum sizes that are greater than the minimum sizes of components fabricated using the first technology node. Examples of compute applications may include high performance computing and/or high performance processing, which may be achieved by fabricating and packing in as many transistors as possible in an integrated device, which is why an integrated device that is configured for compute applications may be fabricated using the most advanced technology node available, while other chiplets may be fabricated using less advanced technology nodes, since those chiplets may not require as many transistors to be fabricated in the chiplets. Thus, the combination of using different technology nodes (which may have different associated yield loss) for different integrated devices and/or chiplets, can reduce the overall cost of a package, compared to using a single integrated device to perform all the functions of the package.
[0053] Another advantage of splitting the functions into several integrated devices and/or chiplets, is that it allows improvements in the performance of the package without having to redesign every single integrated device and/or chiplet. For example, if a configuration of a package uses a first integrated device and a first chiplet, it may be possible to improve the performance of the package by changing the design of the first integrated device, while keeping the design of the first chiplet the same. Thus, the first chiplet could be reused with the improved and/or different configured first integrated device. This saves cost by not having to redesign the first chiplet, when packages with improved integrated devices are fabricated.
[0054] The package may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. A package may be configured to provide Wireless Fidelity (WiFi) communication and/or cellular communication (e.g., 2G, 3G, 4G, 5G, 6G). The packages may be configured to support Global System for Mobile (GSM) Communications, Universal Mobile Telecommunications System (UMTS), and/or Long-Term Evolution (LTE). The packages may be configured to transmit and receive signals having different frequencies and/or communication protocols.
Exemplary Sequence for Fabricating a Device Comprising an Acoustic Layer and at Least One Via Interconnect
[0055] In some implementations, fabricating a device includes several processes.
[0056] It should be noted that the sequence of
[0057] Stage 1, as shown in
[0058] Stage 2 illustrates a state after a substrate 104, a plurality of interconnects 807, at least one seed layer 810 and a dielectric layer 806 are provided. The seed layer 810 may include one or more metal layers (e.g., a barrier layer and a seed layer). The plurality of interconnects 807 may include a plurality of via interconnects and a plurality of pad interconnects. An example of providing and/or fabricating a substrate with interconnects is shown and described below in at least
[0059] Stage 3 illustrates a state after a wafer (e.g., first wafer) that includes a carrier 901, a piezoelectric layer 108, at least one dielectric layer 106, at least one material layer 109, a plurality of interconnects 130, a seed layer 920 and a plurality of interconnects 950, is coupled to another wafer (e.g., second wafer) that includes a substrate 104, a plurality of interconnects 807, at least seed layer 810 (e.g., at least one barrier and seed layer) and a dielectric layer 806. A hybrid bonding process may be used to couple the first wafer to the second wafer. After the coupling process and/or the bonding process, stage 3 may illustrate the carrier 901, the piezoelectric layer 108, the dielectric layer 106, the at least one material layer 109, the plurality of via interconnects 105, the seed layer 305 and the substrate 104. The at least one dielectric layer 106 may represent the at least one dielectric layer 106 and the at least one dielectric layer 806. The plurality of via interconnects 105 may represent the combination of the plurality of interconnects 950 and the plurality of interconnects 807. Stage 3 illustrates a bond interface 260 that conceptually shows where the first wafer is coupled to the second wafer. The bond interface 260 may not be visible after the coupling of the first wafer to the second wafer.
[0060] Stage 4, as shown in
[0061] Stage 5 illustrates a state after the piezoelectric layer 108 is patterned, a plurality of interconnects 131 are formed and a metal layer 330 is formed. An etching process, an exposure process, a development process, sputtering process, evaporation process may be used to pattern the piezoelectric layer, form the plurality of interconnects 131 and/or form the metal layer 330.
[0062] Stage 6, as shown in
[0063] Stage 7, as shown in
[0064] Stage 8, as shown in
[0065] Stage 9, as shown in
[0066] Stage 10, as shown in
[0067] Stage 11 illustrates a state after a plurality of metallization interconnects 150 are formed and coupled to the plurality of via interconnects 105. A metal layer 350 and a metal layer 550 may also be formed. The metal layer 350 may be formed and coupled to a surface of the plurality of metallization interconnects 150. The metal layer 550 may be formed and coupled to a surface of the metal layer 350. The metal layer 550 may include a different material from the metal layer 350. The metal layer 350 may include a different material from the plurality of metallization interconnects 150. One or more plating processes may be used to form the plurality of metallization interconnects 150, the metal layer 350 and/or the metal layer 550. Different implementations may have different number of metal layers. Different implementations may have the metal layer 350 and/or the metal layer 550 located on different surfaces of the plurality of metallization interconnects 150. For example, in some implementations, the metal layer 350 and/or the metal layer 550 may be coupled to side surfaces of the plurality of metallization interconnects 150.
[0068] Stage 12, as shown in
[0069] Stage 13 illustrates a state after the lid layer 102 is thinned. For example, a portion of the lid layer 102 may be removed through a grinding process. With the thinning the lid layer may be separated into individual lid portions.
[0070] Different implementations may use different processes for forming the metal layer(s) and/or interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process (sputtering, evaporation)a spray coating process, and/or a plating process may be used to form the metal layer(s).
Exemplary Flow Diagram of a Method for Fabricating a Device Comprising an Acoustic Layer and at Least One Via Interconnect
[0071] In some implementations, fabricating a device includes several processes.
[0072] It should be noted that the method 600 of
[0073] The method provides (at 605) an acoustic layer comprising a mirror layer. Stage 1 of
[0074] The method provides (at 610) a substrate, at least one dielectric layer and a plurality of interconnects and couples (at 610) the substrate, the at least one dielectric layer and the plurality of interconnects to the acoustic layer. Stage 2 of
[0075] As mentioned above, the method couples (at 610) the substrate to an acoustic layer. Stage 3 of
[0076] The method removes (at 615) the carrier. Stage 4 of
[0077] The method patterns (at 620) a piezoelectric layer and forms a plurality of interconnects. Stage 5 of
[0078] The method couples (at 625) a lid layer to the acoustic layer. Stage 6 of
[0079] The method planarizes (at 630) the substrate, the dielectric layer and the plurality of via interconnects. Stage 7 of
[0080] Stage 7 of
[0081] Stage 8 of
[0082] Stage 9 of
[0083] Stage 10 of
[0084] The method forms (at 635) a plurality of metallization interconnects that are coupled to the plurality of via interconnects. Stage 11 of
[0085] The method forms and couples (at 640) a plurality of solder interconnects to the plurality of metallization interconnects. Stage 12 of
[0086] The method optionally (at 645) thins the lid layer. Stage 13 of
[0087] Different implementations may use different processes for forming the metal layer(s) and/or interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process (sputtering, evaporation) a spray coating process, and/or a plating process may be used to form the metal layer(s).
Exemplary Sequence for Fabricating a Lid Layer
[0088] In some implementations, fabricating a lid layer includes several processes.
[0089] It should be noted that the sequence of
[0090] Stage 1, as shown in
[0091] Stage 4, as shown in
[0092] Stage 8, as shown in
Exemplary Sequence for Fabricating a Substrate With Via Interconnects
[0093] In some implementations, fabricating a substrate with via interconnects includes several processes.
[0094] It should be noted that the sequence of
[0095] Stage 1, as shown in
[0096] Stage 4, as shown in
[0097] Stage 7, as shown in
[0098] Stage 10, as shown in
Exemplary Sequence for Fabricating an Acoustic Layer
[0099] In some implementations, fabricating an acoustic layer includes several processes.
[0100] It should be noted that the sequence of
[0101] Stage 1, as shown in
[0102] Stage 5 illustrates a state after an additional dielectric layer 106b is formed over the existing dielectric layer 106a and the material layer 109a. A deposition process may be used to form the additional dielectric layer 106b. The dielectric layer 106b may be the same or similar material as the dielectric layer 106a. Stage 6 illustrates a state after a material layer 109b is formed over the dielectric layer 106b. The material layer 109b may have a different acoustic impedance from the acoustic impedance of the dielectric layer 106b. The material layer 109b may include an acoustic mirror layer. A sputtering or evaporation process may be used to form the material layer 109b. The material layer 109b may be the same or similar material as the material layer 109a. Stage 7 illustrates a state after an additional dielectric layer 106c is formed over the existing dielectric layer 106b and the material layer 109b. A deposition process may be used to form the additional dielectric layer 106c. The dielectric layer 106c may be the same or similar material as the dielectric layer 106b. Stage 8 illustrates a state after planarization. A portion of the dielectric layer 106 may be removed or polished off and may expose one of the material layer 109 (e.g., 109b). The dielectric layer 106 may represent the dielectric layer 106a, the dielectric layer 106b and the dielectric layer 106c.
[0103] Stage 9, as shown in
[0104] Stage 13, as shown in
[0105] Stage 16 illustrates a state after planarization of the plurality of interconnects 950 and the dielectric layer 106. Portions of the plurality of interconnects 950 and portions of the dielectric layer 106 may be removed.
Exemplary Device Comprising an Acoustic Layer and at Least One Via Interconnect
[0106]
[0107]
Exemplary Sequence for Fabricating a Device Comprising an Acoustic Layer and at Least One Via Interconnect
[0108] In some implementations, fabricating a device includes several processes.
[0109] It should be noted that the sequence of
[0110] Stage 1, as shown in
[0111] Stage 2 illustrates a state after a substrate 104 and a dielectric layer 106 are provided. The substrate 104 may include a plurality of cavities 1102. An example of providing and/or fabricating a substrate is shown and described below in at least
[0112] Stage 3, as shown in
[0113] Stage 5, as shown in
[0114] Stage 6, as shown in
[0115] Stage 7, as shown in
[0116] Stage 8, illustrates a state after a seed layer 305 is provided. A sputtering process may be used to form the seed layer 305. The seed layer 305 may be formed in the plurality of cavities 1102.
[0117] Stage 9, as shown in
[0118] Stage 10, illustrates a state after planarization of the substrate 104 and the plurality of via interconnects 105. A grinding and/or polishing process may be used to remove portions of the plurality of via interconnects 105, portions of the seed layer 305 and portions of the substrate 104.
[0119] Stage 11, as shown in
[0120] Stage 12 illustrates a state after a dielectric layer 1106 is formed over a surface of the substrate 104 and the plurality of via interconnects 105. A deposition process may be used to provide the dielectric layer 1106. The dielectric layer 1106 may include a same material or a similar material as the dielectric layer 106.
[0121] Stage 13, as shown in
[0122] Stage 14 illustrates a state after a plurality of metallization interconnects 150 are formed and coupled to the plurality of via interconnects 105. The plurality of metallization interconnects 150 may include a seed layer. In some implementations, a deposition process, a lamination process, an etching process (e.g., photo etching process), a laser process, an exposure process, a development process, a lithography process, a plating process, and/or a strip process may be used to form the plurality of metallization interconnects 150. The plurality of metallization interconnects 150 may include a plurality of pad interconnects.
[0123] Stage 15, as shown in
[0124] Stage 16 illustrates a state after a plurality of solder interconnects 112 are formed and coupled to the plurality of metallization interconnects 150 and/or the metal layer 350. A solder reflow process may be used to form the plurality of solder interconnects 112. In some implementations, the lid layer 102 may be thinned after the plurality of solder interconnects 112 are coupled to the plurality of metallization interconnects 150 and/or the metal layer 350.
[0125] Different implementations may use different processes for forming the metal layer(s) and/or interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process (sputtering, evaporation), a spray coating process, and/or a plating process may be used to form the metal layer(s).
Exemplary Flow Diagram of a Method for Fabricating a Device Comprising an Acoustic Layer and at Least One Via Interconnect
[0126] In some implementations, fabricating a device includes several processes.
[0127] It should be noted that the method 1200 of
[0128] The method provides (at 1205) an acoustic layer. Stage 1 of
[0129] The method provides (at 1210) a substrate and a dielectric layer. Stage 2 of
[0130] The method couples (at 1215) the acoustic layer to a substrate and a dielectric layer. Stage 3 of
[0131] The method removes (at 1220) a carrier. Stage 4 of
[0132] The method patterns (at 1225) a piezoelectric layer and forms interconnects. Stage 5 of
[0133] The method couples (at 1230) a lid layer to the acoustic layer. Stage 6 of
[0134] The method forms (at 1235) a plurality of via interconnects in the substrate. Stage 7 of
[0135] Stage 8 of
[0136] Stage 9 of
[0137] Stage 10 of
[0138] Stage 11 of
[0139] Stage 12 of
[0140] Stage 13 of
[0141] The method forms (at 1240) a plurality of metallization interconnects that are coupled to the plurality of via interconnects. Stage 14 of
[0142] Stage 15 of
[0143] The method couples (at 1245) a plurality of solder interconnects to the plurality of metallization interconnects. Stage 16 of
[0144] In some implementations, the method is performed on a wafer, and the method may then singulate the wafer to fabricate individual devices. A saw process may be used to dice the wafer into individual devices comprising an acoustic layer.
[0145] Different implementations may use different processes for forming the metal layer(s) and/or interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process (sputtering, evaporation) a spray coating process, and/or a plating process may be used to form the metal layer(s).
Exemplary Device Comprising an Acoustic Layer and at Least One Via Interconnect
[0146]
[0147] The device 1300 may include a plurality of via interconnects 105 with a different design from the device 100, the device 200, the device 300, the device 400 and/or the device 1000. The plurality of via interconnects 105 include via interconnects with two portions with different widths. The via interconnect 105a includes a via interconnect 105aaa and a via interconnect 105aab. The via interconnect 105aaa may be a first via interconnect portion of the via interconnect 105a. The via interconnect 105aaa has a first width. The via interconnect 105aab may be a second via interconnect portion of the via interconnect 105a. The via interconnect 105aab has a second width. The second width may be greater than the first width. The via interconnect 105d includes a via interconnect 105daa and a via interconnect 105dab. The via interconnect 105daa may be a first via interconnect portion of the via interconnect 105d. The via interconnect 105daa has a first width. The via interconnect 105dab may be a second via interconnect portion of the via interconnect 105d. The via interconnect 105dab has a second width. The second width may be greater than the first width. The sequence and/or the process of
[0148]
[0149] The plurality of via interconnects 105 may include a via interconnect 105a, a via interconnect 105c, a via interconnect 105d, a via interconnect 105e, a via interconnect 105f and a via interconnect 105g. The via interconnect 105e, the via interconnect 105f and/or the via interconnect 105g may be either configured or designed as via interconnect arrays with a different width (or diameter) or as via interconnects with a larger width of the via interconnect 105c (either or). Different implementations may have different combinations of via interconnects with different widths and/or diameters. The via interconnect 105e, the via interconnect 105f, the via interconnect 105g and/or the via interconnect 105c may be coupled to the metallization interconnects 150ce.
[0150]
[0151] The device 1500 includes a lid layer 1502, a cavity 1510 and a plurality of lid interconnects 1501. The lid layer 1502 may include a polymer. The plurality of lid interconnects 1501 may include lid via interconnects and/or lid pad interconnects. The plurality of lid interconnects 1501 may extend through the lid layer 1502. The plurality of lid interconnects 1501 may be coupled to the plurality of interconnects 130, the plurality of interconnects 131, and/or the plurality of via interconnects 105. The cavity 1510 may be located in the lid layer 1502. The cavity 1510 may be one of several cavities in the lid layer 1502. The cavity 1510 may be located over the piezoelectric layer 108. The cavity 1510 may be located in the lid layer 1502 and the device base 107. The lid layer 1502 may be coupled to and touch the piezoelectric layer 108.
[0152]
[0153] The device 1600 includes a lid layer 102, the device base 107, the substrate 110 and an encapsulation layer 1602. The substrate 110 includes a plurality of interconnects 1610. The device base 107 is coupled to the substrate 110 through the plurality of metallization interconnects 150 and the plurality of interconnects 1610. The plurality of metallization interconnects 150 are coupled to the plurality of interconnects 1610 through hybrid bonding. The encapsulation layer 1602 may at least partially encapsulate the device base 107 and the lid layer 102. The encapsulation layer 1602 may include a mold, a resin, an epoxy and/or a filler. The encapsulation layer 1602 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 1602 may be coupled to the substrate 110. The substrate 110 may include a dielectric layer 1650. The dielectric layer 1650 may be coupled to the dielectric layer 106. The dielectric layer 106 may not be distinguishable from the dielectric layer 1650. The dielectric layer 1650 may include the same material or a similar material as the dielectric layer 106.
[0154]
[0155]
[0156] The device 1700 includes a lid layer 102, the device base 107, the substrate 110 and an encapsulation layer 1702. The substrate 110 includes a plurality of interconnects 1610. The device base 107 is coupled to the substrate 110 through the plurality of metallization interconnects 150, the plurality of solder interconnects 112 and the plurality of interconnects 1710. The plurality of metallization interconnects 150 are coupled to the plurality of interconnects 1710 through the plurality of solder interconnects 112. The encapsulation layer 1702 may at least partially encapsulate the device base 107 and the lid layer 102. The encapsulation layer 1702 may include a mold, a resin, an epoxy and/or a filler. The encapsulation layer 1702 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 1702 may be coupled to a surface of the substrate 110.
[0157] In some implementations, a package may include several devices with acoustic devices.
[0158] The first device 1801, the second device 1802, the third device 1803 and the fourth device 1804 may be coupled to the substrate 1810 through hybrid bonding. The first device 1801, the second device 1802, the third device 1803 and/or the fourth device 1804 may each be configured to operate as separate acoustic wave resonators for different frequencies.
[0159] The encapsulation layer 1809 may be coupled to a surface of the substrate 1810. The encapsulation layer 1809 may at least partially encapsulate the first device 1801, the second device 1802, the third device 1803 and/or the fourth device 1804. The encapsulation layer 1809 may include a mold, a resin, an epoxy and/or a filler. The encapsulation layer 1809 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.
[0160] As mentioned above, the different devices may have different configurations. As shown in
[0161]
[0162] The first device 1801 may be coupled to the plurality of interconnects 1812 of the substrate 1810 through a first plurality of solder interconnects 1910. The second device 1802 may be coupled to the plurality of interconnects 1812 of the substrate 1810 through a second plurality of solder interconnects 1920. The third device 1803 may be coupled to the plurality of interconnects 1812 of the substrate 1810 through a third plurality of solder interconnects 1930. The fourth device 1804 may be coupled to the plurality of interconnects 1812 of the substrate 1810 through a fourth plurality of solder interconnects 1940.
[0163] The encapsulation layer 1809 may be coupled to a surface of the substrate 1810. The encapsulation layer 1809 may at least partially encapsulate the first device 1801, the second device 1802, the third device 1803 and/or the fourth device 1804. The encapsulation layer 1809 may include a mold, a resin, an epoxy and/or a filler. The encapsulation layer 1809 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.
Exemplary Electronic Devices
[0164]
[0165] One or more of the components, processes, features, and/or functions illustrated in
[0166] It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.
[0167] The word exemplary is used herein to mean serving as an example, instance, or illustration. Any implementation or aspect described herein as exemplary is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term aspects does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term coupled is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one anothereven if they do not directly physically touch each other. An object A, that is coupled to an object B, may be coupled to at least part of object B. The term electrically coupled may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms first, second, third and fourth (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to a second component, may be the first component, the second component, the third component or the fourth component. The terms encapsulate, encapsulating and/or any derivation means that the object may partially encapsulate or completely encapsulate another object. The terms top and bottom are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located over a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term over as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. A first component that is located in a second component may be partially located in the second component or completely located in the second component. A value that is about X-XX, may mean a value that is between X and XX, inclusive of X and XX. The value(s) between X and XX may be discrete or continuous. The term about value X, or approximately value X, as used in the disclosure means within 10 percent of the value X. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1. A plurality of components may include all the possible components or only some of the components from all of the possible components. For example, if a device includes ten components, the use of the term the plurality of components may refer to all ten components or only some of the components from the ten components.
[0168] In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace (e.g., trace interconnect), a via (e.g., via interconnect), a pad (e.g., pad interconnect), a pillar, a metallization layer, a redistribution layer, and/or an under bump metallization (UBM) layer/interconnect. In some implementations, an interconnect may include an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process (sputtering, evaporation), a spray coating, and/or a plating process may be used to form the interconnects.
[0169] Also, it is noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.
[0170] In the following, further examples are described to facilitate the understanding of the invention.
[0171] Aspect 1: A device comprising a lid layer; an acoustic layer coupled to the lid layer, wherein the acoustic layer comprises: a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer; a cavity located between the lid layer and the piezoelectric layer; a substrate coupled to the dielectric layer of the acoustic layer; and at least one via interconnect coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate.
[0172] Aspect 2: The device of aspect 1, wherein the dielectric layer comprises a first acoustic impedance, and wherein the at least one material layer comprises a second acoustic impedance that is different from the first acoustic impedance.
[0173] Aspect 3: The device of aspects 1 through 2, wherein at least part of the dielectric layer and the at least one material layer are configured as an acoustic mirror.
[0174] Aspect 4: The device of aspects 1 through 3, wherein the at least one via interconnect is configured to provide an electrical path through the dielectric layer and the substrate.
[0175] Aspect 5: The device of aspects 1 through 4, wherein the lid layer further comprises a lid via interconnect that extends through the lid layer.
[0176] Aspect 6: The device of aspect 5, wherein the lid via interconnect is coupled to the plurality of interconnects of the acoustic layer.
[0177] Aspect 7: The device of aspects 1 through 6, further comprising a plurality of metallization interconnects coupled to the at least one via interconnect.
[0178] Aspect 8: The device of aspects 1 through 7, wherein the at least one via interconnect comprises: a first via interconnect that extends through the dielectric layer; a pad coupled to the first via interconnect; and a second via interconnect that extends through the substrate, wherein the second via interconnect is coupled to the pad.
[0179] Aspect 9: The device of aspects 1 through 8, wherein the lid layer is coupled to the acoustic layer such that a hermetic seal is provided between the lid layer and the acoustic layer.
[0180] Aspect 10: The device of aspects 1 through 9, wherein the lid layer comprises silicon, glass, fused silica, ceramic, polymer, or a combination thereof.
[0181] Aspect 11: The device of aspects 1 through 10, wherein the device includes an acoustic wave device.
[0182] Aspect 12: The device of aspects 1 through 11, further comprising at least one thermal via interconnect extending through the substrate, wherein the at least one thermal via interconnect is free of any electrical connection with the piezoelectric layer.
[0183] Aspect 13: The device of aspects 1 through 12, wherein the plurality of interconnects are configured as electrodes.
[0184] Aspect 14: The device of aspects 1 through 13, wherein the at least one material layer includes tungsten.
[0185] Aspect 15: The device of aspects 1 through 14, wherein the piezoelectric layer includes aluminum nitride (Aln) or aluminum scandium nitride (AlScN).
[0186] Aspect 16: A method for fabricating an acoustic device. The method provides a lid layer. The method couples an acoustic layer to the lid layer. The acoustic layer comprises a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer, wherein the acoustic layer is coupled to the lid layer such that a cavity is located between the lid layer and the piezoelectric layer. The method couples a substrate to the dielectric layer of the acoustic layer. The method forms at least one via interconnect that is coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate.
[0187] Aspect 17: The method of aspect 16, wherein the dielectric layer comprises a first acoustic impedance, and wherein the at least one material layer comprises a second acoustic impedance that is different from the first acoustic impedance.
[0188] Aspect 18: The method of aspects 16 through 17, wherein at least part of the dielectric layer and the at least one material layer are configured as an acoustic mirror.
[0189] Aspect 19: The method of aspects 16 through 18, wherein the at least one via interconnect is configured to provide an electrical path through the dielectric layer and the substrate.
[0190] Aspect 20: The method of aspects 16 through 19, wherein the at least one via interconnects comprises: a first via interconnect that extends through the dielectric layer; a pad coupled to the first via interconnect; and a second via interconnect that extends through the substrate, wherein the second via interconnect is coupled to the pad.
[0191] The various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.