EPITAXIAL WAFER, ß-Ga2O3-BASED DEVICE, AND METHOD FOR FABRICATING ß-Ga2O3-BASED DEVICE

Abstract

An epitaxial wafer 1 includes a Ga.sub.2O.sub.3-based substrate, a metal layer, and a -Ga.sub.2O.sub.3 layer. The Ga.sub.2O.sub.3-based substrate has a first principal surface and a second principal surface opposite from the first principal surface. The metal layer is formed on the first principal surface of the Ga.sub.2O.sub.3-based substrate. The metal layer has a plurality of openings. The -Ga.sub.2O.sub.3 layer covers the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer. The metal layer is made of a material such as a noble metal or a refractory metal. The thickness of the -Ga.sub.2O.sub.3 layer is smaller than the thickness of the Ga.sub.2O.sub.3-based substrate.

Claims

1. An epitaxial wafer comprising: a Ga.sub.2O.sub.3-based substrate having a first principal surface and a second principal surface opposite from the first principal surface; a metal layer formed on the first principal surface of the Ga.sub.2O.sub.3-based substrate and having a plurality of openings; and a -Ga.sub.2O.sub.3 layer covering the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer, the metal layer being made of a material such as a noble metal or a refractory metal, and a thickness of the -Ga.sub.2O.sub.3 layer being smaller than a thickness of the Ga.sub.2O.sub.3-based substrate.

2. The epitaxial wafer of claim 1, wherein the metal layer includes a plurality of metallic parts, each of the plurality of metallic parts is linear, and in the metal layer, the plurality of metallic parts and the plurality of openings are arranged alternately when viewed in plan in a thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate.

3. The epitaxial wafer of claim 1, wherein in the metal layer, the plurality of openings are arranged to form a two-dimensional array.

4. The epitaxial wafer of claim 1, wherein the Ga.sub.2O.sub.3-based substrate is a -Ga.sub.2O.sub.3 substrate.

5. The epitaxial wafer of claim 1, wherein the Ga.sub.2O.sub.3-based substrate includes: a sapphire substrate; and a -Ga.sub.2O.sub.3 layer formed on the sapphire substrate, and in the Ga.sub.2O.sub.3-based substrate, a surface of the -Ga.sub.2O.sub.3 layer forms the first principal surface of the Ga.sub.2O.sub.3-based substrate.

6. A -Ga.sub.2O.sub.3-based device comprising: a Ga.sub.2O.sub.3-based substrate having a first principal surface and a second principal surface opposite from the first principal surface; a metal layer formed selectively on the first principal surface of the Ga.sub.2O.sub.3-based substrate; a -Ga.sub.2O.sub.3 layer covering the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer; and a semiconductor element, the semiconductor element including at least a part of the -Ga.sub.2O.sub.3 layer, the metal layer being made of a material such as a noble metal or a refractory metal, and a thickness of the -Ga.sub.2O.sub.3 layer being smaller than a thickness of the Ga.sub.2O.sub.3-based substrate.

7. The -Ga.sub.2O.sub.3-based device of claim 6, wherein the metal layer includes a plurality of metallic parts, each of the plurality of metallic parts is linear, and in the metal layer, the plurality of metallic parts are arranged to be spaced from each other in a direction perpendicular to each of the plurality of metallic parts when viewed in plan in a thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate.

8. The -Ga.sub.2O.sub.3-based device of claim 7, wherein the semiconductor element is a MESFET including a drain region, a source region, a channel forming region, a drain electrode, a source electrode, and a gate electrode, the drain region, the source region, and the channel forming region are defined in the -Ga.sub.2O.sub.3 layer, and the channel forming region overlaps with one metallic part out of the plurality of metallic parts when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate.

9. The -Ga.sub.2O.sub.3-based device of claim 8, wherein the Ga.sub.2O.sub.3-based substrate is a semi-insulating -Ga.sub.2O.sub.3 substrate, the -Ga.sub.2O.sub.3 layer is an n-type -Ga.sub.2O.sub.3 layer, the drain region has a comb shape and is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined within the n-type -Ga.sub.2O.sub.3 layer, the source region has a comb shape and is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined within the n-type -Ga.sub.2O.sub.3 layer, the drain electrode is formed on the drain region and has a shape of a comb overlapping with the drain region when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate, the source electrode is formed on the source region and has a shape of a comb overlapping with the source region when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate, the gate electrode is formed on the n-type -Ga.sub.2O.sub.3 layer and has a shape of a comb when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate, the drain electrode includes: a drain electrode comb backbone; and a plurality of drain electrode comb teeth extending from the drain electrode comb backbone, the source electrode includes: a source electrode comb backbone; and a plurality of source electrode comb teeth extending from the source electrode comb backbone, the gate electrode includes: a gate electrode comb backbone; and a plurality of gate electrode comb teeth extending from the gate electrode comb backbone, the drain electrode comb backbone and the source electrode comb backbone face each other in a first direction, the plurality of drain electrode comb teeth, the plurality of gate electrode comb teeth, and the plurality of source electrode comb teeth are arranged side by side in a second direction perpendicular to both the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate and the first direction, and each of the plurality of gate electrode comb teeth overlaps with any one metallic part out of the plurality of metallic parts when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate.

10. The -Ga.sub.2O.sub.3-based device of claim 9, wherein each of the plurality of gate electrode comb teeth is arranged to be offset in the second direction to avoid overlapping with a center of the one metallic part in the second direction when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate.

11. The -Ga.sub.2O.sub.3-based device of claim 6, wherein the metal layer has a plurality of openings which are arranged to form a two-dimensional array.

12. The -Ga.sub.2O.sub.3-based device of claim 6, wherein the semiconductor element is a Schottky barrier diode, the Ga.sub.2O.sub.3-based substrate is a semi-insulating -Ga.sub.2O.sub.3 substrate, the -Ga.sub.2O.sub.3 layer includes: an n.sup.+-type -Ga.sub.2O.sub.3 layer covering the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer and making ohmic contact with the metal layer; and an n-type -Ga.sub.2O.sub.3 layer formed on the n.sup.+-type -Ga.sub.2O.sub.3 layer, the semiconductor element includes: a first metal electrode layer formed out of the metal layer; the n.sup.+-type -Ga.sub.2O.sub.3 layer; the n-type -Ga.sub.2O.sub.3 layer; and a second metal electrode layer formed on, and making Schottky contact with, the n-type -Ga.sub.2O.sub.3 layer, and in the semiconductor element, at least a part of the second metal electrode layer and at least a part of the first metal electrode layer overlap with each other when viewed in plan in a thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate, and the second metal electrode layer serves as an anode electrode and the n.sup.+-type -Ga.sub.2O.sub.3 layer and the first metal electrode layer serve as a cathode electrode.

13. The -Ga.sub.2O.sub.3-based device of claim 7, wherein the semiconductor element is a MOSFET including a drain region, a source region, a channel forming region, a gate insulating film, a drain electrode, a source electrode, and a gate electrode, and the drain region, the source region, and the channel forming region are formed in the -Ga.sub.2O.sub.3 layer.

14. The -Ga.sub.2O.sub.3-based device of claim 13, wherein the Ga.sub.2O.sub.3-based substrate is a semi-insulating -Ga.sub.2O.sub.3 substrate, the -Ga.sub.2O.sub.3 layer is an n-type -Ga.sub.2O.sub.3 layer, the plurality of metallic parts includes a first metallic part and a second metallic part which are adjacent to each other in a direction in which the plurality of metallic parts are arranged side by side, the drain region is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined on the first metallic part in the -Ga.sub.2O.sub.3 layer, the source region is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined on the second metallic part in the -Ga.sub.2O.sub.3 layer, the first metallic part serves as the drain electrode, the second metallic part serves as the source electrode, the gate insulating film is formed on the -Ga.sub.2O.sub.3 layer, the gate electrode is formed on the gate insulating film and is located between the drain region and the source region when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate, and the -Ga.sub.2O.sub.3 layer is formed in such a shape as to expose a part of the first metallic part and a part of the second metallic part.

15. The -Ga.sub.2O.sub.3-based device of claim 13, wherein the -Ga.sub.2O.sub.3 layer includes: a semi-insulating -Ga.sub.2O.sub.3 layer in contact with the metal layer; and an n-type -Ga.sub.2O.sub.3 layer formed on the semi-insulating -Ga.sub.2O.sub.3 layer, the drain region is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer, the source region is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer, the gate insulating film is formed on the n-type -Ga.sub.2O.sub.3 layer, the gate electrode is formed on the gate insulating film and located between the drain region and the source region when viewed in plan in the thickness direction defined with respect to the Ga.sub.2O.sub.3-based substrate, the drain electrode is formed on the drain region, and the source electrode is formed on the source region.

16. The -Ga.sub.2O.sub.3-based device of claim 15, further comprising a heat sink, wherein the metal layer has an exposed part not covered with the -Ga.sub.2O.sub.3 layer, and the heat sink is disposed on the exposed part of the metal layer.

17. The -Ga.sub.2O.sub.3-based device of claim 6, further comprising: a heat dissipating layer formed on the semiconductor element and having electrical insulation properties; and a heat sink disposed on the heat dissipating layer, wherein the heat dissipating layer contains an AlN filler.

18. A method for fabricating a -Ga.sub.2O.sub.3-based device, the method comprising: a substrate providing process step including providing a Ga.sub.2O.sub.3-based substrate having a first principal surface and a second principal surface opposite from the first principal surface; a metal layer forming process step including forming a metal layer having a plurality of openings on the first principal surface of the Ga.sub.2O.sub.3-based substrate; and an epitaxial growing process step including forming a -Ga.sub.2O.sub.3 layer that covers the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer by epitaxial lateral overgrowth using a mist CVD method, the metal layer being made of a material such as a noble metal or a refractory metal, and a thickness of the -Ga.sub.2O.sub.3 layer being smaller than a thickness of the Ga.sub.2O.sub.3-based substrate.

19. The method of claim 18, further comprising: a laser liftoff process step including stripping the Ga.sub.2O.sub.3-based substrate from the metal layer and the -Ga.sub.2O.sub.3 layer by irradiating the Ga.sub.2O.sub.3-based substrate with a laser beam through the second principal surface of the Ga.sub.2O.sub.3-based substrate; and a bonding process step including bonding a heat sink onto an exposed surface of the metal layer and an exposed surface of the -Ga.sub.2O.sub.3 layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0010] The figures depict one or more implementations in accordance with the present teaching, by way of example only, not by way of limitations. In the figures, like reference numerals refer to the same or similar elements.

[0011] FIG. 1 is a cross-sectional view illustrating a main part of an epitaxial wafer according to a first embodiment;

[0012] FIG. 2 is a plan view illustrating the main part of the epitaxial wafer;

[0013] FIG. 3 is a partially cutaway perspective view of the epitaxial wafer, of which a -Ga.sub.2O.sub.3 layer is not shown there;

[0014] FIG. 4A-4E are cross-sectional views illustrating main process steps of a method for fabricating the epitaxial wafer;

[0015] FIG. 5 illustrates the epitaxial wafer;

[0016] FIG. 6 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to the first embodiment;

[0017] FIG. 7 is a plan view of the -Ga.sub.2O.sub.3-based device;

[0018] FIG. 8 is a cross-sectional view illustrating a main part of an epitaxial wafer according to a variation of the first embodiment;

[0019] FIG. 9 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to a second embodiment;

[0020] FIG. 10 is a plan view of the -Ga.sub.2O.sub.3-based device;

[0021] FIG. 11 is a cross-sectional view illustrating a main process step of a method for fabricating the -Ga.sub.2O.sub.3-based device;

[0022] FIG. 12 is a plan view illustrating a main process step of the method for fabricating the -Ga.sub.2O.sub.3-based device;

[0023] FIG. 13 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to a third embodiment;

[0024] FIG. 14 is a plan view of the -Ga.sub.2O.sub.3-based device;

[0025] FIG. 15 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to a fourth embodiment;

[0026] FIG. 16 is a plan view of the -Ga.sub.2O.sub.3-based device;

[0027] FIG. 17 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to a fifth embodiment;

[0028] FIG. 18 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to a sixth embodiment;

[0029] FIG. 19 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to a seventh embodiment;

[0030] FIG. 20 is a plan view of the -Ga.sub.2O.sub.3-based device;

[0031] FIG. 21 is a cross-sectional view of a -Ga.sub.2O.sub.3-based device according to an eighth embodiment;

[0032] FIG. 22 is a plan view illustrating a metal layer of the -Ga.sub.2O.sub.3-based device;

[0033] FIG. 23A-23C are cross-sectional views illustrating main process steps of a method for fabricating the -Ga.sub.2O.sub.3-based device; and

[0034] FIG. 24 is a plan view illustrating a metal layer of a -Ga.sub.2O.sub.3-based device according to a variation of the eighth embodiment.

DETAILED DESCRIPTION

[0035] FIG. 1-24 to be referred to in the following description of first to eighth embodiments and their variations are all schematic representations. Thus, the ratio of the dimensions (including thicknesses) of respective constituent elements illustrated on the drawings does not always reflect their actual dimensional ratio.

First Embodiment

(1) Epitaxial Wafer and Method for Fabricating the Same

[0036] An epitaxial wafer 1 according to a first embodiment and a method for fabricating the epitaxial wafer 1 will now be described with reference to FIG. 1-5.

(1.1) Epitaxial Wafer

[0037] An epitaxial wafer 1 according to the first embodiment includes a Ga.sub.2O.sub.3-based substrate 2, a metal layer 3, and a -Ga.sub.2O.sub.3 layer 4 as shown in FIG. 1. The Ga.sub.2O.sub.3-based substrate 2 has a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21. The metal layer 3 is formed on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2. The metal layer 3 has a plurality of openings 32. Thus, the metal layer 3 is formed selectively on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2. The -Ga.sub.2O.sub.3 layer 4 covers the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3. The epitaxial wafer 1 is a -Ga.sub.2O.sub.3 epitaxial wafer. The -Ga.sub.2O.sub.3 epitaxial wafer is a wafer formed by epitaxially growing the -Ga.sub.2O.sub.3 layer 4 on the Ga.sub.2O.sub.3-based substrate 2 which is a wafer including -Ga.sub.2O.sub.3 crystals.

[0038] In the epitaxial wafer 1 according to the first embodiment, the Ga.sub.2O.sub.3-based substrate 2 is a -Ga.sub.2O.sub.3 substrate 20. The -Ga.sub.2O.sub.3 substrate 20 is made up of -Ga.sub.2O.sub.3 single crystals. The crystal structure of the -Ga.sub.2O.sub.3 single crystals is a monoclinic crystal system. The first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 may be, but does not have to be, a (010) plane or a (001) plane of -Ga.sub.2O.sub.3 single crystals, for example. As used herein, each of the (010) and (001) planes is a crystallographic plane expressed by three Miller indices placed in parentheses. Optionally, the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 may also be a crystallographic plane that forms an off-axis angle with respect to the (010) or (001) plane of -Ga.sub.2O.sub.3 single crystals. Also, in the epitaxial wafer 1 according to the first embodiment, the -Ga.sub.2O.sub.3 substrate 20 is a semi-insulating -Ga.sub.2O.sub.3 substrate. The semi-insulating -Ga.sub.2O.sub.3 substrate is a -Ga.sub.2O.sub.3 substrate having a resistivity equal to or higher than 110.sup.8 cm and equal to or lower than 110.sup.12 cm.

[0039] The Ga.sub.2O.sub.3-based substrate 2 has a substantially circular shape when viewed in plan in a thickness direction D10 defined with respect to the Ga.sub.2O.sub.3-based substrate 2. The Ga.sub.2O.sub.3-based substrate 2 may have a diameter equal to or greater than 50 mm and equal to or less than 150 mm, for example. The Ga.sub.2O.sub.3-based substrate 2 may have a thickness T1 equal to or greater than 400 m and equal to or less than 800 m, for example.

[0040] The metal layer 3 may be made of a material such as a noble metal or a refractory metal. If a noble metal is used as a material for the metal layer 3, the noble metal may be Pt or Au, for example, but may also be any noble metal other than Pt and Au. If a refractory metal is used as a material for the metal layer 3, the refractory metal may be Ta or W, for example, but may also be any refractory metal other than Ta and W.

[0041] The metal layer 3 includes a plurality of metallic parts 31. Each of the plurality of metallic parts 31 has a linear (elongate) shape. In the following description, the longitudinal axis of each of the plurality of metallic parts 31 is herein defined to be a first direction D11 (refer to FIG. 2) and a direction perpendicular to both the thickness direction D10 defined with respect to the Ga.sub.2O.sub.3-based substrate 2 and the first direction D11 is herein defined to be a second direction D12. As used herein, the elongate shape refers to a shape which is elongate in one direction, i.e., a shape which is longer in the one direction than in any other direction intersecting with the one direction. Thus, each of the plurality of metallic parts 31 is longer in the first direction D11 than in the second direction D12.

[0042] In the metal layer 3, the plurality of metallic parts 31 are arranged to be spaced from each other in the second direction D12 when viewed in plan in the thickness direction D10 defined with respect to the Ga.sub.2O.sub.3-based substrate 2 (refer to FIG. 2). That is to say, in the metal layer 3, the plurality of metallic parts 31 are arranged to be spaced from each other in a direction perpendicular to the plurality of metallic parts 31 when viewed in plan in the thickness direction D10 defined with respect to the Ga.sub.2O.sub.3-based substrate 2. In other words, in the metal layer 3, the plurality of metallic parts 31 are arranged in stripes when viewed in plan in the thickness direction D10 defined with respect to the Ga.sub.2O.sub.3-based substrate 2. Each of the plurality of metallic parts 31 may, but does not have to, have a thickness of 50 nm, for example.

[0043] In the metal layer 3, the plurality of metallic parts 31 and the plurality of openings 32 are arranged alternately (refer to FIG. 3). Each of the plurality of openings 32 is open on both sides in the first direction D11. Alternatively, each of the plurality of openings 32 may also have a shape which is open on neither side in the first direction D11.

[0044] The -Ga.sub.2O.sub.3 layer 4 is an epitaxial layer which has been grown epitaxially on the Ga.sub.2O.sub.3-based substrate 2 as a base member. More specifically, the -Ga.sub.2O.sub.3 layer 4 is a -Ga.sub.2O.sub.3 epitaxial layer which has been grown epitaxially on the -Ga.sub.2O.sub.3 substrate 20. In the epitaxial wafer 1 according to the first embodiment, the -Ga.sub.2O.sub.3 layer 4 is an n-type -Ga.sub.2O.sub.3 layer. The n-type -Ga.sub.2O.sub.3 layer contains an n-type impurity (such as Sn, Si, or Ge).

[0045] The -Ga.sub.2O.sub.3 layer 4 covers the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3. More specifically, the -Ga.sub.2O.sub.3 layer 4 covers not only multiple parts 211, not covered with the metal layer 3, of the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 but also the metal layer 3.

[0046] The thickness T2 of the -Ga.sub.2O.sub.3 layer 4 is smaller than the thickness T1 of the Ga.sub.2O.sub.3-based substrate 2. The thickness T2 of the -Ga.sub.2O.sub.3 layer 4 may be, for example, equal to or greater than 200 nm and equal to or less than 500 nm but may also be greater than 500 nm.

(1.2) Method for Fabricating Epitaxial Wafer

[0047] Next, a method for fabricating the epitaxial wafer 1 according to the first embodiment will be described with reference to FIG. 4A-4E.

[0048] A method for fabricating the epitaxial wafer 1 includes a substrate providing process step, a metal layer forming process step, and an epitaxial growing process step.

[0049] The substrate providing process step includes providing a Ga.sub.2O.sub.3-based substrate 2 having a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21 (refer to FIG. 4A).

[0050] The metal layer forming process step includes forming a metal layer 3 having a plurality of metallic parts 31 and a plurality of openings 32 on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 (refer to FIG. 4B). That is to say, the metal layer forming process step includes forming a metal layer 3 in a predetermined pattern. The metal layer forming process step may include, for example, forming a metallic material layer, which will be patterned into the metal layer 3, by evaporation, for example, on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2, and then patterning the metallic material layer by, for example, photolithographic and etching techniques, thereby forming a metal layer 3 as respective parts of the metallic material layer. Alternatively, the metal layer forming process step may include forming the metal layer 3 by evaporation, for example, using a metal mask.

[0051] The epitaxial growing process step includes forming a -Ga.sub.2O.sub.3 layer 4 by epitaxial lateral overgrowth (ELO) using a mist chemical vapor deposition (CVD) process to cover the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3 (refer to FIG. 4E). The epitaxial lateral overgrowth is a crystal growing technique as a combination of an epitaxial growth and a lateral overgrowth. That is to say, some parts of the -Ga.sub.2O.sub.3 layer 4 are formed by epitaxial growth directly on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2, while the other parts of the -Ga.sub.2O.sub.3 layer 4 are formed by lateral overgrowth on the metal layer 3. Those parts, formed directly on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2, of the -Ga.sub.2O.sub.3 layer 4 include a plurality of first parts 401 (refer to FIG. 5) corresponding one to one to a plurality of areas 211, not covered with the metal layer 3, of the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2. On the other hand, those parts, formed on the metal layer 3, of the -Ga.sub.2O.sub.3 layer 4 include a plurality of parts 402 (refer to FIG. 5) corresponding one to one to the plurality of metallic parts 31. FIG. 4C illustrates a -Ga.sub.2O.sub.3 layer 4C made up of respective parts of the -Ga.sub.2O.sub.3 layer 4 while -Ga.sub.2O.sub.3 crystals are growing epitaxially. FIG. 4D illustrates a -Ga.sub.2O.sub.3 layer 4D made up of respective parts of the -Ga.sub.2O.sub.3 layer 4 while -Ga.sub.2O.sub.3 crystals are growing epitaxially. The -Ga.sub.2O.sub.3 layer 4D is a -Ga.sub.2O.sub.3 layer that has grown to an increased degree compared with the -Ga.sub.2O.sub.3 layer 4C. That is to say, the -Ga.sub.2O.sub.3 layer 4D is thicker than the -Ga.sub.2O.sub.3 layer 4C and has a higher coverage with respect to each of the metallic parts 31 than the -Ga.sub.2O.sub.3 layer 4C does. FIG. 4E illustrates a -Ga.sub.2O.sub.3 layer 4 which covers the respective metallic parts 31 by combining respective -Ga.sub.2O.sub.3 crystals that have overgrown laterally from both sides of each of the metallic parts 31 in the width direction (i.e., a direction parallel to the second direction D12). In the epitaxial growing process step, a mist CVD system is used as an epitaxial growing system. Optionally, in this epitaxial growing process step, a molecular beam epitaxy (MBE) method or a hydride vapor phase epitaxy (HVPE) method may be adopted instead of the mist CVD method.

[0052] As shown in FIG. 5, threading dislocations A1 of the Ga.sub.2O.sub.3-based substrate 2 are inherited as threading dislocations A2 of the -Ga.sub.2O.sub.3 layer 4 in the plurality of first parts 401 of the -Ga.sub.2O.sub.3 layer 4 in the epitaxial wafer 1, while the threading dislocations A1 of the Ga.sub.2O.sub.3-based substrate 2 are not inherited to the plurality of second parts 402. In the -Ga.sub.2O.sub.3 layer 4, the dislocation density of each of the plurality of second parts 402 is lower than the dislocation density of any of the plurality of first parts 401. The dislocation density is a value obtained based on a cross-sectional transmission electron microscope (TEM) image.

(2) -Ga.SUB.2.O.SUB.3.-Based Device and Method for Fabricating the Same

(2.1) -Ga.SUB.2.O.SUB.3.-Based Device

[0053] Next, a -Ga.sub.2O.sub.3-based device 10 according to the first embodiment will be described with reference to FIGS. 6 and 7.

[0054] The -Ga.sub.2O.sub.3-based device 10 according to the first embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5 as shown in FIG. 6. The -Ga.sub.2O.sub.3-based device 10 is a chip (also called a die). The Ga.sub.2O.sub.3-based substrate 2a is, for example, a fragment of the Ga.sub.2O.sub.3-based substrate 2 of the epitaxial wafer 1 (refer to FIG. 1). In this embodiment, the thickness T11 of the Ga.sub.2O.sub.3-based substrate 2a is equal to the thickness T1 of the Ga.sub.2O.sub.3-based substrate 2. Alternatively, the thickness T11 of the Ga.sub.2O.sub.3-based substrate 2a may be smaller than the thickness T1 of the Ga.sub.2O.sub.3-based substrate 2.

[0055] The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a.

[0056] The Ga.sub.2O.sub.3-based substrate 2a is a -Ga.sub.2O.sub.3 substrate 20a. The -Ga.sub.2O.sub.3 substrate 20a is made up of -Ga.sub.2O.sub.3 single crystals. The crystal structure of the -Ga.sub.2O.sub.3 single crystals is a monoclinic crystal system. The first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a may be, but does not have to be, a (010) plane or a (001) plane of -Ga.sub.2O.sub.3 single crystals, for example. In the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, the -Ga.sub.2O.sub.3 substrate 20a is a semi-insulating -Ga.sub.2O.sub.3 substrate. The semi-insulating -Ga.sub.2O.sub.3 substrate is a -Ga.sub.2O.sub.3 substrate having a resistivity equal to or higher than 110.sup.8 cm and equal to or lower than 110.sup.12 cm. The Ga.sub.2O.sub.3-based substrate 2a has a rectangular shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The Ga.sub.2O.sub.3-based substrate 2a may have a thickness T11 equal to or greater than 400 m and equal to or less than 800 m, for example.

[0057] The metal layer 3a may be made of a material such as a noble metal or a refractory metal. If a noble metal is used as a material for the metal layer 3a, the noble metal may be Pt or Au, for example, but may also be any noble metal other than Pt and Au. If a refractory metal is used as a material for the metal layer 3a, the refractory metal may be Ta or W, for example, but may also be any refractory metal other than Ta and W.

[0058] The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a.

[0059] The -Ga.sub.2O.sub.3 layer 4a covers the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and the metal layer 3a. More specifically, the -Ga.sub.2O.sub.3 layer 4a covers not only multiple parts 211a, not covered with the metal layer 3a, of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a but also the metal layer 3a.

[0060] The semiconductor element 5 includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The semiconductor element 5 will be described later.

[0061] In the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, the metal layer 3a includes a plurality of metallic parts 31a. Each of the plurality of metallic parts 31a has a linear shape. In the following description, the longitudinal axis of each of the plurality of metallic parts 31a is herein defined to be a first direction D21 and a direction perpendicular to both the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a and the first direction D21 is herein defined to be a second direction D22. In the metal layer 3a, the plurality of metallic parts 31a are arranged to be spaced from each other in the second direction D22 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. That is to say, in the metal layer 3a, the plurality of metallic parts 31a are arranged to be spaced from each other in a direction perpendicular to the plurality of metallic parts 31a (i.e., in the second direction D22) when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. In other words, in the metal layer 3a, the plurality of metallic parts 31a are arranged in stripes when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. Each of the plurality of metallic parts 31a may, but does not have to, have a thickness of 50 nm, for example.

[0062] In the metal layer 3a, the plurality of metallic parts 31a and the plurality of openings 32a are arranged alternately. Each of the plurality of openings 32a is open on both sides in the first direction D21. Alternatively, each of the plurality of openings 32a may also have a shape which is open on neither side in the first direction D21.

[0063] The -Ga.sub.2O.sub.3 layer 4a is an epitaxial layer which has been grown epitaxially on the Ga.sub.2O.sub.3-based substrate 2a as a base member. More specifically, the -Ga.sub.2O.sub.3 layer 4a is a -Ga.sub.2O.sub.3 epitaxial layer which has been grown epitaxially on the -Ga.sub.2O.sub.3 substrate 20a. In the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, the -Ga.sub.2O.sub.3 layer 4a is an n-type -Ga.sub.2O.sub.3 layer. The n-type -Ga.sub.2O.sub.3 layer contains an n-type impurity (such as Sn, Si, or Ge). In the following description, the -Ga.sub.2O.sub.3 layer 4a will be hereinafter sometimes referred to as an n-type -Ga.sub.2O.sub.3 layer 4a.

[0064] The thickness T12 of the -Ga.sub.2O.sub.3 layer 4a is smaller than the thickness T11 of the Ga.sub.2O.sub.3-based substrate 2a. The thickness T12 of the -Ga.sub.2O.sub.3 layer 4a may be, for example, equal to or greater than 200 nm and equal to or less than 500 nm but may also be greater than 500 nm.

[0065] In the -Ga.sub.2O.sub.3 layer 4a, the dislocation density of its parts overlapping with the metallic parts 31a in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a (i.e., its parts formed on the metallic parts 31a) is smaller than the dislocation density of its parts not overlapping with the metallic parts 31a in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a (i.e., its parts formed directly on the Ga.sub.2O.sub.3-based substrate 2a).

[0066] In the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, the semiconductor element 5 is a metal semiconductor field effect transistor (MESFET).

[0067] The semiconductor element 5 includes a drain region 51, a source region 52, a drain electrode 55, a source electrode 56, and a gate electrode 57 as shown in FIGS. 6 and 7. Note that although the source electrode 56 and the gate electrode 57 are shaded by dotted hatching in FIG. 7, the hatching does not indicate a cross section but is adopted to make the elements on the drawing easily recognizable.

[0068] The drain region 51 is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer 4a. The drain region 51 has a comb shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The drain region 51 includes: a drain region comb backbone having an elongate shape and a longitudinal axis defined by the second direction D22; and a plurality of drain region comb teeth 512 extending in the first direction D21 from the drain region comb backbone. The carrier concentration in the n.sup.+-type -Ga.sub.2O.sub.3 region serving as the drain region 51 is higher than the carrier concentration in the n-type -Ga.sub.2O.sub.3 layer 4a.

[0069] The source region 52 is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer 4a. The source region 52 has a comb shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The source region 52 includes: a source region comb backbone having an elongate shape and a longitudinal axis defined by the second direction D22; and a plurality of source region comb teeth 522 extending in the first direction D21 from the source region comb backbone. The carrier concentration in the n.sup.+-type -Ga.sub.2O.sub.3 region serving as the source region 52 is higher than the carrier concentration in the n-type -Ga.sub.2O.sub.3 layer 4a.

[0070] The channel forming region 53 is defined in a region, located between the drain region 51 and the source region 52, of the n-type -Ga.sub.2O.sub.3 layer 4a. More specifically, the channel forming region 53 is defined between the drain region comb tooth 512 and the source region comb tooth 522 which are adjacent to each other in the second direction D22.

[0071] The drain electrode 55 is formed on the drain region 51. The drain electrode 55 overlaps with the drain region 51 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The drain electrode 55 has a comb shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a (refer to FIG. 7). The drain electrode 55 includes: a drain electrode comb backbone 551 having an elongate shape and a longitudinal axis defined by the second direction D22; and a plurality of drain electrode comb teeth 552 extending in the first direction D21 from the drain electrode comb backbone 551 as shown in FIG. 7. The plurality of drain electrode comb teeth 552 correspond one to one to the plurality of drain region comb teeth 512. Each of the plurality of drain electrode comb teeth 552 overlaps with a corresponding one of the plurality of drain region comb teeth 512 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. A material for the drain electrode 55 may be Au or Pt, for example, but may also be a metal other than Au and Pt or an alloy. The drain electrode 55 is electrically connected to the drain region 51. As used herein, the expression the drain electrode 55 is electrically connected to the drain region 51 means that the drain electrode 55 and the drain region 51 make ohmic contact with each other.

[0072] The source electrode 56 is formed on the source region 52. The source electrode 56 overlaps with the source region 52 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The source electrode 56 has a comb shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a (refer to FIG. 7). The source electrode 56 includes: a source electrode comb backbone 561 having an elongate shape and a longitudinal axis defined by the second direction D22; and a plurality of source electrode comb teeth 562 extending in the first direction D21 from the source electrode comb backbone 561. The plurality of source electrode comb teeth 562 correspond one to one to the plurality of source region comb teeth 522. Each of the plurality of source electrode comb teeth 562 overlaps with a corresponding one of the plurality of source region comb teeth 522 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. A material for the source electrode 56 may be Au or Pt, for example, but may also be a metal other than Au and Pt or an alloy. The source electrode 56 is electrically connected to the source region 52. As used herein, the expression the source electrode 56 is electrically connected to the source region 52 means that the source electrode 56 and the source region 52 make ohmic contact with each other.

[0073] In the semiconductor element 5, the drain electrode comb backbone 551 and the source electrode comb backbone 561 face each other in the first direction D21. Also, in the semiconductor element 5, the plurality of drain electrode comb teeth 552 and the plurality of source electrode comb teeth 562 are arranged to be spaced from each other in the second direction D22.

[0074] The gate electrode 57 is formed on the n-type -Ga.sub.2O.sub.3 layer 4a. The gate electrode 57 has a comb shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a (refer to FIG. 7). The gate electrode 57 includes: a gate electrode comb backbone 571 having an elongate shape and a longitudinal axis defined by the second direction D22; and a plurality of gate electrode comb teeth 572 extending in the first direction D21 from the gate electrode comb backbone 571. A material for the gate electrode 57 may be Au or Pt, for example. Alternatively, the material for the gate electrode 57 may also be a metal other than Au or Pt or an alloy.

[0075] In the semiconductor element 5, the plurality of drain electrode comb teeth 552, the plurality of gate electrode comb teeth 572, and the plurality of source electrode comb teeth 562 are arranged side by side in the second direction D22. Thus, each gate electrode comb tooth 572 is located between a drain electrode comb tooth 552 and a source electrode comb tooth 562 which are adjacent to each other in the second direction D22. The plurality of gate electrode comb teeth 572 correspond one to one to the plurality of channel forming regions 53 in the n-type -Ga.sub.2O.sub.3 layer 4a. Each of the plurality of channel forming regions 53 is a region between a drain region comb tooth 512 and a source region comb tooth 522 which are adjacent to each other in the second direction D22 inside the n-type -Ga.sub.2O.sub.3 layer 4a. Each of the plurality of gate electrode comb teeth 572 overlaps with a corresponding one of the plurality of channel forming regions 53 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The semiconductor element 5 includes an interlevel dielectric film interposed between the gate electrode comb backbone 571 and the plurality of drain electrode comb teeth 552 to prevent the gate electrode 57 from making contact with the drain electrode 55.

[0076] Each of the plurality of gate electrode comb teeth 572 overlaps with any one metallic part 31a out of the plurality of metallic parts 31a when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. None of the plurality of gate electrode comb teeth 572 overlap with any of the plurality of parts 211a of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. In the semiconductor element 5 according to the first embodiment, the plurality of gate electrode comb teeth 572 correspond one to one to the plurality of metallic parts 31a. However, this is only an example and should not be construed as limiting. The plurality of gate electrode comb teeth 572 does not have to correspond one to one to the plurality of metallic parts 31a. Each of the plurality of channel forming regions 53 overlaps with any one metallic part 31a out of the plurality of metallic parts 31a but none of the plurality of channel forming regions 53 overlap with any of the plurality of parts 211a of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0077] Each of the plurality of gate electrode comb teeth 572 is arranged to be offset in the second direction D22 to avoid overlapping with the center of a corresponding one of the plurality of metallic parts 31a in the second direction D22 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. In the semiconductor element 5, the shortest distance between a gate electrode comb tooth 572 and a drain electrode comb tooth 552 which are adjacent to each other in the second direction D22 is shorter than the distance between the gate electrode comb tooth 572 and a source electrode comb tooth 562 which are adjacent to each other in the second direction D22.

(2.2) Method for Fabricating -Ga.SUB.2.O.SUB.3.-Based Device

[0078] Next, an exemplary method for fabricating the -Ga.sub.2O.sub.3-based device 10 will be described briefly with reference to FIG. 4A-4E. As for the same process steps as those of the method for fabricating the epitaxial wafer 1, the description thereof will be omitted as appropriate herein.

[0079] The method for fabricating the -Ga.sub.2O.sub.3-based device 10 includes a substrate providing process step, a metal layer forming process step, an epitaxial growing process step, a drain/source region forming process step, an electrode forming process step, and a dicing process step.

[0080] The substrate providing process step includes providing a Ga.sub.2O.sub.3-based substrate 2 having a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21 (refer to FIG. 4A). The Ga.sub.2O.sub.3-based substrate 2 is a wafer configured as a -Ga.sub.2O.sub.3 substrate 20 and is a wafer as a prototype of the Ga.sub.2O.sub.3-based substrate 2a.

[0081] The metal layer forming process step includes forming a metal layer 3 having a plurality of metallic parts 31 and a plurality of openings 32 on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 (refer to FIG. 4B). The plurality of metallic parts 31 and the plurality of opening 32 will be the plurality of metallic parts 31a and the plurality of openings 32a, respectively. The width of each of the plurality of metallic parts 31 as measured in the second direction D12 is equal to the width of a corresponding one of the plurality of metallic parts 31a as measured in the second direction D22. On the other hand, the length of each of the plurality of metallic parts 31 as measured in the first direction D11 is greater than the length of a corresponding one of the plurality of metallic parts 31a as measured in the first direction D21. The width of each of the plurality of openings 32 as measured in the second direction D12 is equal to the width of a corresponding one of the plurality of openings 32a as measured in the second direction D22. On the other hand, the length of each of the plurality of openings 32 as measured in the first direction D11 is greater than the length of a corresponding one of the plurality of openings 32a as measured in the first direction D21.

[0082] The epitaxial growing process step includes forming a -Ga.sub.2O.sub.3 layer 4 by epitaxial lateral overgrowth using a mist CVD method to cover the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3 (refer to FIG. 4E). In this embodiment, the -Ga.sub.2O.sub.3 layer 4 is an n-type -Ga.sub.2O.sub.3 layer, which is a prototype of the -Ga.sub.2O.sub.3 layer 4a. Alternatively, in the epitaxial growing process step, an MBE method or an HVPE method, for example, may be adopted instead of the mist CVD method.

[0083] The drain/source region forming process step includes forming a plurality of drain regions 51 (refer to FIG. 6) and a plurality of source regions 52 (refer to FIG. 6) in the -Ga.sub.2O.sub.3 layer 4 by, for example, ion implantation and diffusion techniques.

[0084] The electrode forming process step includes forming the drain electrode 55, the source electrode 56, and the gate electrode 57 by evaporation, for example.

[0085] According to this method for fabricating the -Ga.sub.2O.sub.3-based device 10, a wafer including a plurality of -Ga.sub.2O.sub.3-based devices 10 may be obtained by performing the respective process steps from the substrate providing process step through the electrode forming process step. According to the method for fabricating the -Ga.sub.2O.sub.3-based device 10, a plurality of -Ga.sub.2O.sub.3-based devices 10 may be obtained by cutting off, in the dicing process step, the wafer including a plurality of -Ga.sub.2O.sub.3-based devices 10 using a dicing saw or a laser dicing device, for example.

(3) Advantages

[0086] An epitaxial wafer 1 according to the first embodiment includes a Ga.sub.2O.sub.3-based substrate 2, a metal layer 3, and a -Ga.sub.2O.sub.3 layer 4. The Ga.sub.2O.sub.3-based substrate 2 has a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21. The metal layer 3 is formed on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2. The metal layer 3 has a plurality of openings 32. The -Ga.sub.2O.sub.3 layer 4 covers the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3. The metal layer 3 is made of a material such as a noble metal or a refractory metal. The thickness T2 of the -Ga.sub.2O.sub.3 layer 4 is smaller than the thickness T1 of the Ga.sub.2O.sub.3-based substrate 2.

[0087] The epitaxial wafer 1 according to the first embodiment, having such a configuration, may contribute to improving the characteristics of a -Ga.sub.2O.sub.3-based device 10. More specifically, in the epitaxial wafer 1 according to the first embodiment, the dislocation density of each of a plurality of second parts 402, corresponding one to one to the plurality of metallic parts 31, of the -Ga.sub.2O.sub.3 layer 4 is smaller than the dislocation density of each of a plurality of first parts 401, formed directly on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2, of the -Ga.sub.2O.sub.3 layer 4. Thus, as for the -Ga.sub.2O.sub.3-based device 10 to be fabricated using the epitaxial wafer 1, laying out functional regions, which are easily subject to the effect of dislocations, of the -Ga.sub.2O.sub.3-based device 10 on those parts, covering the metal layer 3, of the -Ga.sub.2O.sub.3 layer 4 allows for contributing to improving the characteristics of the -Ga.sub.2O.sub.3-based device 10. Those functional regions may be, for example, channel forming regions 53 which are important in determining the characteristics of MESFETs serving as semiconductor elements 5.

[0088] In addition, in the epitaxial wafer 1 according to the first embodiment, the threading dislocations A1 of the Ga.sub.2O.sub.3-based substrate 2 are unlikely to be inherited to those parts (i.e., the respective second parts 402), covering the metal layer 3, of the -Ga.sub.2O.sub.3 layer 4, thus allowing a less expensive -Ga.sub.2O.sub.3 substrate 20 to be used as the Ga.sub.2O.sub.3-based substrate 2 and thereby contributing to cutting down the cost.

[0089] Furthermore, in the epitaxial wafer 1 according to the first embodiment, the -Ga.sub.2O.sub.3 layer 4 covers the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3. Thus, in the epitaxial wafer 1, the metal layer 3 is interposed between parts of the -Ga.sub.2O.sub.3 layer 4 and the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2. This allows for reducing the effect on those parts, formed on the metal layer 3, of the -Ga.sub.2O.sub.3 layer 4 when the Ga.sub.2O.sub.3-based substrate 2 is polished from the second principal surface 22 to have its thickness reduced. Thus, the epitaxial wafer 1 makes it easier to reduce the thickness T1 of the Ga.sub.2O.sub.3-based substrate 2. Consequently, this enables the thermal resistance of the -Ga.sub.2O.sub.3-based device 10 fabricated using the epitaxial wafer 1 to be reduced, thus allowing for improving the characteristics of the -Ga.sub.2O.sub.3-based device 10.

[0090] A -Ga.sub.2O.sub.3-based device 10 according to the first embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5. The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a. The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a. The -Ga.sub.2O.sub.3 layer 4a covers the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and the metal layer 3a. The semiconductor element 5 includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The metal layer 3a is made of a material such as a noble metal or a refractory metal. The thickness T12 of the -Ga.sub.2O.sub.3 layer 4a is smaller than the thickness T11 of the Ga.sub.2O.sub.3-based substrate 2a.

[0091] The -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, having such a configuration, may contribute to improving the characteristics.

[0092] In the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, the semiconductor element 5 is a MESFET including a drain region 51, a source region 52, a channel forming region 53, a drain electrode 55, a source electrode 56, and a gate electrode 57. The drain region 51, the source region 52, and the channel forming region 53 are defined in the -Ga.sub.2O.sub.3 layer 4a. The channel forming region 53 overlaps with one metallic part 31a out of the plurality of metallic parts 31a when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0093] The -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, having such a configuration, may contribute to improving the characteristics of the MESFET.

[0094] A method for fabricating a -Ga.sub.2O.sub.3-based device 10 according to the first embodiment includes a substrate providing process step, a metal layer forming process step, and an epitaxial growing process step. The substrate providing process step includes providing a Ga.sub.2O.sub.3-based substrate 2 having a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21. The metal layer forming process step includes forming a metal layer 3 having a plurality of openings 32 on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2. The epitaxial growing process step includes forming a -Ga.sub.2O.sub.3 layer 4 that covers the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3 by epitaxial lateral overgrowth using a mist CVD method. The metal layer 3 is made of a material such as a noble metal or a refractory metal. The thickness T2 of the -Ga.sub.2O.sub.3 layer 4 is smaller than the thickness T1 of the Ga.sub.2O.sub.3-based substrate 2.

[0095] This method for fabricating a -Ga.sub.2O.sub.3-based device 10 according to the first embodiment may contribute to improving the characteristics of the -Ga.sub.2O.sub.3-based device 10.

Variation of First Embodiment

[0096] An epitaxial wafer 1A according to a variation of the first embodiment will be described with reference to FIG. 8. In the following description, any constituent element of the epitaxial wafer 1A according to this variation, having the same function as a counterpart of the epitaxial wafer 1 (refer to FIGS. 1 and 2) according to the first embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

(1) Epitaxial Wafer

[0097] The epitaxial wafer 1A according to this variation includes a Ga.sub.2O.sub.3-based substrate 2A instead of the Ga.sub.2O.sub.3-based substrate 2 of the epitaxial wafer 1 according to the first embodiment, which is a difference from the epitaxial wafer 1 according to the first embodiment described above.

[0098] The Ga.sub.2O.sub.3-based substrate 2A includes a sapphire substrate 24 and a -Ga.sub.2O.sub.3 layer 25 formed on the sapphire substrate 24. In the Ga.sub.2O.sub.3-based substrate 2A, the surface 251 of the -Ga.sub.2O.sub.3 layer 25 serves as the first principal surface 21A of the Ga.sub.2O.sub.3-based substrate 2A. The Ga.sub.2O.sub.3-based substrate 2A has a substantially circular shape when viewed in plan in the thickness direction D10 defined with respect to the Ga.sub.2O.sub.3-based substrate 2A.

[0099] In the Ga.sub.2O.sub.3-based substrate 2A, the thickness of the -Ga.sub.2O.sub.3 layer 25 is smaller than the thickness of the sapphire substrate 24. The sapphire substrate 24 may have a thickness equal to or greater than 430 m and equal to or less than 1300 m, for example. The -Ga.sub.2O.sub.3 layer 25 may have a thickness equal to or greater than 0.2 m and equal to or less than 3 m, for example.

[0100] The sapphire substrate 24 has a first principal surface 241 and a second principal surface 242 opposite from the first principal surface 241. The first principal surface 241 of the sapphire substrate 24 may be, but does not have to be, a c-plane. Alternatively, the first principal surface 241 of the sapphire substrate 24 may also be an m-plane. The c-plane is a (0001) plane. The m-plane may be a (1010) plane, for example. As used herein, each of the (0001) and (1010) planes is a crystallographic plane expressed by four Miller indices placed in parentheses. In the Ga.sub.2O.sub.3-based substrate 2A, the second principal surface 242 of the sapphire substrate 24 serves as the second principal surface 22A of the Ga.sub.2O.sub.3-based substrate 2A.

[0101] In the epitaxial wafer 1A, the thickness T2 of the -Ga.sub.2O.sub.3 layer 4 is smaller than the thickness T1 of the Ga.sub.2O.sub.3-based substrate 2A.

[0102] In the -Ga.sub.2O.sub.3 layer 4 of the epitaxial wafer 1A according to the first variation, the dislocation density of each of a plurality of second parts 402, corresponding one to one to the plurality of metallic parts 31, of the -Ga.sub.2O.sub.3 layer 4 is smaller in the thickness direction D10 defined with respect to the Ga.sub.2O.sub.3-based substrate 2A than the dislocation density of any of a plurality of first parts 401, formed directly on the plurality of parts 211 of the first principal surface 21A of the Ga.sub.2O.sub.3-based substrate 2A, of the -Ga.sub.2O.sub.3 layer 4.

(2) Method for Fabricating Epitaxial Wafer

[0103] A method for fabricating the epitaxial wafer 1A, as well as the method for fabricating the epitaxial wafer 1, also includes a substrate providing process step, a metal layer forming process step, and an epitaxial growing process step.

[0104] In the method for fabricating the epitaxial wafer 1A, the substrate providing process step includes providing a sapphire substrate 24, epitaxially growing an -Ga.sub.2O.sub.3 layer thereafter on the first principal surface 241 of the sapphire substrate 24 by a mist CVD method, and then annealing the -Ga.sub.2O.sub.3 layer, thereby changing the crystal structure of the -Ga.sub.2O.sub.3 layer to form a -Ga.sub.2O.sub.3 layer 25. That is to say, the -Ga.sub.2O.sub.3 layer is transformed into the -Ga.sub.2O.sub.3 layer 25. In this manner, a Ga.sub.2O.sub.3-based substrate 2A is obtained. Alternatively, the substrate providing process step may include epitaxially growing a -Ga.sub.2O.sub.3 layer 25 on the first principal surface 241 of the sapphire substrate 24 by a mist CVD method, of which the growing temperature is set at higher temperature than in a situation where the -Ga.sub.2O.sub.3 layer is epitaxially grown on the first principal surface 241 of the sapphire substrate 24 by a mist CVD method.

[0105] The metal layer forming process step includes forming a metal layer 3 having a plurality of metallic parts 31 and a plurality of openings 32 on the first principal surface 21A of the Ga.sub.2O.sub.3-based substrate 2A.

[0106] The epitaxial growing process step includes forming a -Ga.sub.2O.sub.3 layer 4 by epitaxial lateral overgrowth using a mist CVD method to cover the first principal surface 21A of the Ga.sub.2O.sub.3-based substrate 2A and the metal layer 3. Optionally, in the epitaxial growing process step, an MBE method or an HVPE method may be adopted instead of the mist CVD method.

(3) -Ga.SUB.2.O.SUB.3.-Based Device

[0107] The -Ga.sub.2O.sub.3-based device according to this variation has substantially the same configuration as the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment described above. In the -Ga.sub.2O.sub.3-based device according to this variation, the Ga.sub.2O.sub.3-based substrate 2a of the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment is made up of a sapphire substrate which forms part of the sapphire substrate 24 and a -Ga.sub.2O.sub.3 layer formed on the sapphire substrate which forms part of the -Ga.sub.2O.sub.3 layer 25, which is a difference from the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment.

(4) Method for Fabricating -Ga.SUB.2.O.SUB.3.-Based Device

[0108] A method for fabricating the -Ga.sub.2O.sub.3-based device according to this variation is substantially the same as the method for fabricating the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment but is different from the latter method in that the substrate providing process step includes providing the epitaxial wafer 1A instead of the epitaxial wafer 1.

(5) Advantages

[0109] The epitaxial wafer 1A according to this variation, as well as the epitaxial wafer 1 according to the first embodiment, may contribute to improving the characteristics of the -Ga.sub.2O.sub.3-based device 10.

[0110] In addition, the epitaxial wafer 1A according to this variation may use the sapphire substrate 24 which is less expensive than the -Ga.sub.2O.sub.3 substrate 20 of the epitaxial wafer 1, thus contributing to cutting down the cost compared to the epitaxial wafer 1.

Second Embodiment

[0111] Next, a -Ga.sub.2O.sub.3-based device 10B according to a second embodiment and a method for fabricating the -Ga.sub.2O.sub.3-based device 10B will be described with reference to FIG. 9-12. In the following description, any constituent element of the -Ga.sub.2O.sub.3-based device 10B according to this second embodiment, having the same function as a counterpart of the -Ga.sub.2O.sub.3-based device 10 (refer to FIGS. 6 and 7) according to the first embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

(1) -Ga.SUB.2.O.SUB.3.-Based Device

[0112] A -Ga.sub.2O.sub.3-based device 10B according to the second embodiment will be described with reference to FIGS. 9 and 10.

[0113] The -Ga.sub.2O.sub.3-based device 10B according to the second embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5B.

[0114] The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a.

[0115] The Ga.sub.2O.sub.3-based substrate 2a is a -Ga.sub.2O.sub.3 substrate 20a. Also, the -Ga.sub.2O.sub.3 substrate 20a is a semi-insulating -Ga.sub.2O.sub.3 substrate. The Ga.sub.2O.sub.3-based substrate 2a has a rectangular shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0116] The metal layer 3a may be made of a material such as a noble metal or a refractory metal. If a noble metal is used as a material for the metal layer 3a, the noble metal may be Pt or Au, for example, but may also be any noble metal other than Pt and Au. If a refractory metal is used as a material for the metal layer 3a, the refractory metal may be Ta or W, for example, but may also be any refractory metal other than Ta and W.

[0117] The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a.

[0118] The -Ga.sub.2O.sub.3 layer 4a covers a part of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and a part of the metal layer 3a. More specifically, the -Ga.sub.2O.sub.3 layer 4a covers not only each of two parts 211a, not covered with the metal layer 3a, of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a partially but also the metal layer 3a partially.

[0119] The semiconductor element 5B includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The semiconductor element 5B will be described later.

[0120] In the -Ga.sub.2O.sub.3-based device 10B, the metal layer 3a includes one metallic part 31a. The metallic part 31a has a linear (elongate) shape. In the following description, the longitudinal axis of the metallic part 31a is herein defined to be a first direction D21 (refer to FIG. 10) and a direction perpendicular to both the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a and the first direction D21 is herein defined to be a second direction D22.

[0121] The metallic part 31a is located between the two parts 211a of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The metallic part 31a has a first end 310a and a second end 310b in the first direction D21. In the -Ga.sub.2O.sub.3-based device 10B, neither the first end 310a nor the second end 310b of the metallic part 31a is covered with the -Ga.sub.2O.sub.3 layer 4a.

[0122] The -Ga.sub.2O.sub.3 layer 4a is an epitaxial layer which has been grown epitaxially on the Ga.sub.2O.sub.3-based substrate 2a as a base member.

[0123] The -Ga.sub.2O.sub.3 layer 4a includes: an n.sup.+-type -Ga.sub.2O.sub.3 layer 41a that covers a part of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and a part of the metal layer 3a; and an n-type -Ga.sub.2O.sub.3 layer 42a formed on the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a.

[0124] Each of the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a and the n-type -Ga.sub.2O.sub.3 layer 42a contains an n-type impurity (such as Sn, Si, or Ge). The carrier concentration in the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a is higher than the carrier concentration in the n-type -Ga.sub.2O.sub.3 layer 42a. The n.sup.+-type -Ga.sub.2O.sub.3 layer 41a makes an ohmic contact with the metal layer 3a.

[0125] The semiconductor element 5B is a Schottky barrier diode.

[0126] The semiconductor element 5B includes: a first metal electrode layer 58 formed out of the metal layer 3a; the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a; the n-type -Ga.sub.2O.sub.3 layer 42a; and a second metal electrode layer 59. The second metal electrode layer 59 is formed on, and makes a Schottky contact with, the n-type -Ga.sub.2O.sub.3 layer 42a.

[0127] In the semiconductor element 5B, the entire second metal electrode layer 59 overlaps with a part of the first metal electrode layer 58 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0128] In the semiconductor element 5B, the second metal electrode layer 59 serves as an anode electrode, while the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a and the first metal electrode layer 58 serve as a cathode electrode. In the semiconductor element 5B, the first end 310a and second end 310b of the metallic part 31a serving as the first metal electrode layer 58 may be used as electrode pads of the cathode electrode.

(2) Method for Fabricating -Ga.SUB.2.O.SUB.3.-Based Device

[0129] Next, an exemplary method for fabricating the -Ga.sub.2O.sub.3-based device 10B will be described briefly with reference to FIGS. 4A, 4B, 11, and 12. As for the same process steps as those of the method for fabricating the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, the description thereof will be omitted as appropriate herein.

[0130] The method for fabricating the -Ga.sub.2O.sub.3-based device 10B includes a substrate providing process step, a metal layer forming process step, an epitaxial growing process step, an electrode layer forming process step, a patterning process step, and a dicing process step.

[0131] The substrate providing process step includes providing a Ga.sub.2O.sub.3-based substrate 2 having a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21 (refer to FIG. 4A). The Ga.sub.2O.sub.3-based substrate 2 is a wafer configured as a -Ga.sub.2O.sub.3 substrate 20 and is a wafer as a prototype of the Ga.sub.2O.sub.3-based substrate 2a.

[0132] The metal layer forming process step includes forming a metal layer 3 having a plurality of metallic parts 31 and a plurality of openings 32 on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 (refer to FIG. 4B). Each of the plurality of metallic parts 31 will be the metallic part 31a. The width of each of the plurality of metallic parts 31 is equal to the width of the metallic part 31a as measured in the second direction D22 (refer to FIG. 10). On the other hand, the length of each of the plurality of metallic parts 31 is greater than the length of the metallic part 31a as measured in the first direction D21 (refer to FIG. 10).

[0133] The epitaxial growing process step includes forming an n.sup.+-type -Ga.sub.2O.sub.3 layer 41 (refer to FIG. 11) by epitaxial lateral overgrowth using a mist CVD method to cover the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3 and forming an n-type -Ga.sub.2O.sub.3 layer 42 (refer to FIG. 11) by a mist CVD method to cover the n.sup.+-type -Ga.sub.2O.sub.3 layer 41. The n.sup.+-type -Ga.sub.2O.sub.3 layer 41 is a prototype of the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a. The n-type -Ga.sub.2O.sub.3 layer 42 is a prototype of the n-type -Ga.sub.2O.sub.3 layer 42a. An epitaxial wafer 1B (refer to FIG. 11) is fabricated by performing the substrate providing process step, the metal layer forming process step, and the epitaxial growing process step. Alternatively, in the epitaxial growing process step, an MBE method or an HVPE method, for example, may be adopted instead of the mist CVD method. In this embodiment, the n.sup.+-type -Ga.sub.2O.sub.3 layer 41 and the n-type -Ga.sub.2O.sub.3 layer 42 form the -Ga.sub.2O.sub.3 layer 4.

[0134] The electrode layer forming process step includes forming a plurality of second metal electrode layers 59 (refer to FIG. 11) by evaporation, for example. Note that the electrode layer forming process step includes forming a plurality of second metal electrode layers 59 on the -Ga.sub.2O.sub.3 layer 4.

[0135] The patterning process step includes patterning the -Ga.sub.2O.sub.3 layer 4 by, for example, photolithographic and etching techniques, thereby exposing each of the plurality of metallic parts 31 partially and the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 partially (refer to FIG. 12).

[0136] According to this method for fabricating the -Ga.sub.2O.sub.3-based device 10B, a wafer 100B (refer to FIGS. 11 and 12) including a plurality of -Ga.sub.2O.sub.3-based devices 10B may be obtained by performing the respective process steps from the substrate providing process step through the patterning process step.

[0137] According to the method for fabricating the -Ga.sub.2O.sub.3-based device 10B, a plurality of -Ga.sub.2O.sub.3-based devices 10B may be obtained by cutting off, in the dicing process step, the wafer 100B including a plurality of -Ga.sub.2O.sub.3-based devices 10B using a dicing saw or a laser dicing device, for example. Note that the one-dot chains shown in FIG. 12 indicate dicing lines.

(3) Advantages

[0138] A -Ga.sub.2O.sub.3-based device 10B according to the second embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5B. The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a. The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a. The -Ga.sub.2O.sub.3 layer 4a covers the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and the metal layer 3a. The semiconductor element 5B includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The metal layer 3a is made of a material such as a noble metal or a refractory metal. The thickness T12 of the -Ga.sub.2O.sub.3 layer 4a is smaller than the thickness T11 of the Ga.sub.2O.sub.3-based substrate 2a.

[0139] The -Ga.sub.2O.sub.3-based device 10B according to the second embodiment has such a configuration, and therefore, shortens the distance between the first metal electrode layer 58 and the second metal electrode layer 59, and cuts down the loss, compared to a situation where the first metal electrode layer 58 is provided on the second principal surface 22a, not on the first principal surface 21a, of the Ga.sub.2O.sub.3-based substrate 2a, thus contributing to improving the characteristics.

[0140] In the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment, the semiconductor element 5B is a Schottky barrier diode. In the semiconductor element 5B, the entire second metal electrode layer 59 overlaps with a part of the first metal electrode layer 58 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a, the second metal electrode layer 59 serves as an anode electrode, and the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a and the first metal electrode layer 58 serve as a cathode electrode. This allows the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment to contribute to improving the characteristics of a Schottky barrier diode.

[0141] In the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment, the semiconductor element 5B may improve the characteristics of the Schottky barrier diode as long as at least a part of the second metal electrode layer 59 overlaps with at least a part of the first metal electrode layer 58 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

Third Embodiment

[0142] Next, a -Ga.sub.2O.sub.3-based device 10C according to a third embodiment and a method for fabricating the -Ga.sub.2O.sub.3-based device 10C will be described with reference to FIGS. 13 and 14. In the following description, any constituent element of the -Ga.sub.2O.sub.3-based device 10C according to this third embodiment, having the same function as a counterpart of the -Ga.sub.2O.sub.3-based device 10 (refer to FIGS. 6 and 7) according to the first embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

(1) -Ga.SUB.2.O.SUB.3.-Based Device

[0143] The -Ga.sub.2O.sub.3-based device 10C according to the third embodiment will be described with reference to FIGS. 13 and 14.

[0144] The -Ga.sub.2O.sub.3-based device 10C according to the third embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5C.

[0145] The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a.

[0146] The Ga.sub.2O.sub.3-based substrate 2a is a -Ga.sub.2O.sub.3 substrate 20a. Also, the -Ga.sub.2O.sub.3 substrate 20a is a semi-insulating -Ga.sub.2O.sub.3 substrate. The Ga.sub.2O.sub.3-based substrate 2a has a rectangular shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0147] The metal layer 3a may be made of a material such as a noble metal or a refractory metal. If a noble metal is used as a material for the metal layer 3a, the noble metal may be Pt or Au, for example, but may also be any noble metal other than Pt and Au. If a refractory metal is used as a material for the metal layer 3a, the refractory metal may be Ta or W, for example, but may also be any refractory metal other than Ta and W.

[0148] The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a.

[0149] The -Ga.sub.2O.sub.3 layer 4a covers the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a partially and the metal layer 3a partially. More specifically, the -Ga.sub.2O.sub.3 layer 4a covers not only each of three parts 211a, not covered with the metal layer 3a, of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a partially but also the metal layer 3a partially.

[0150] The semiconductor element 5C includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The semiconductor element 5C will be described later.

[0151] In the -Ga.sub.2O.sub.3-based device 10C, the metal layer 3a includes two metallic parts 31a. Each of the two metallic parts 31a has a linear shape. In the following description, the longitudinal axis of the two metallic parts 31a is herein defined to be a first direction D21 (refer to FIG. 14) and a direction perpendicular to both the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a and the first direction D21 is herein defined to be a second direction D22.

[0152] The semiconductor element 5C is a MOSFET, and includes a drain region 51, a source region 52, a channel forming region 53, a gate insulating film 54, a drain electrode 55, a source electrode 56, and a gate electrode 57 as shown in FIG. 13. The drain region 51, the source region 52, and the channel forming region 53 are defined in the -Ga.sub.2O.sub.3 layer 4a.

[0153] In the -Ga.sub.2O.sub.3-based device 10C, the Ga.sub.2O.sub.3-based substrate 2a is a semi-insulating -Ga.sub.2O.sub.3 substrate.

[0154] The -Ga.sub.2O.sub.3 layer 4a is an n-type -Ga.sub.2O.sub.3 layer. The n-type -Ga.sub.2O.sub.3 layer contains an n-type impurity (such as Sn, Si, or Ge). The -Ga.sub.2O.sub.3 layer 4a is an epitaxial layer which has been grown epitaxially on the Ga.sub.2O.sub.3-based substrate 2a as a base member. In the following description, the -Ga.sub.2O.sub.3 layer 4a will be hereinafter sometimes referred to as an n-type -Ga.sub.2O.sub.3 layer 4a.

[0155] The plurality of metallic parts 31a includes a first metallic part 311 and a second metallic part 312 which are adjacent to each other in the direction (second direction D22) in which the plurality of metallic parts 31a are arranged side by side. As shown in FIG. 14, the first metallic part 311 has a first end 311a and a second end 311b in the first direction D21, and the second metallic part 312 has a first end 312a and a second end 312b in the first direction D21.

[0156] As shown in FIG. 13, the drain region 51 is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer 4a to be located on the first metallic part 311. The carrier concentration in the n.sup.+-type -Ga.sub.2O.sub.3 region serving as the drain region 51 is higher than the carrier concentration in the n-type -Ga.sub.2O.sub.3 layer 4a. The drain region 51 overlaps with the first metallic part 311 in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The drain region 51 is in contact with the first metallic part 311. In this embodiment, the drain region 51 is electrically connected to the first metallic part 311. In other words, the first metallic part 311 makes an ohmic contact with the drain region 51. In the -Ga.sub.2O.sub.3-based device 10C, the first metallic part 311 serves as the drain electrode 55.

[0157] The source region 52 is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer 4a to be located on the second metallic part 312. The carrier concentration in the n.sup.+-type -Ga.sub.2O.sub.3 region serving as the source region 52 is higher than the carrier concentration in the n-type -Ga.sub.2O.sub.3 layer 4a. The source region 52 overlaps with the second metallic part 312 in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. The source region 52 is in contact with the second metallic part 312. In this embodiment, the source region 52 is electrically connected to the source electrode 56. In other words, the second metallic part 312 makes an ohmic contact with the source region 52. In the -Ga.sub.2O.sub.3-based device 10C, the second metallic part 312 serves as the source electrode 56.

[0158] The channel forming region 53 is defined between the drain region 51 and the source region 52 in the n-type -Ga.sub.2O.sub.3 layer 4a.

[0159] The gate insulating film 54 is formed over the n-type -Ga.sub.2O.sub.3 layer 4a, the drain region 51, and the source region 52. Examples of materials for the gate insulating film 54 include silicon oxide, hafnium oxide, aluminum nitride, silicon nitride, and aluminum oxide.

[0160] The gate electrode 57 is formed on the gate insulating film 54. The gate electrode 57 is located between the drain region 51 and the source region 52 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. A material for the gate electrode 57 may be Au or Pt, for example, but may also be a metal other than Au and Pt or an alloy.

[0161] The -Ga.sub.2O.sub.3 layer 4a is formed in such a shape that exposes the first metallic part 311 partially and the second metallic part 312 partially. In the -Ga.sub.2O.sub.3-based device 10C, the -Ga.sub.2O.sub.3 layer 4a is formed in such a shape that exposes a first end 311a and second end 311b of the first metallic part 311 and a first end 312a and second end 312b of the second metallic part 312. The -Ga.sub.2O.sub.3 layer 4a has a rectangular shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. When measured in the second direction D22, the length of the -Ga.sub.2O.sub.3 layer 4a is equal to the length of the Ga.sub.2O.sub.3-based substrate 2a. When measured in the first direction D21, the length of the -Ga.sub.2O.sub.3 layer 4a is less than the length of the Ga.sub.2O.sub.3-based substrate 2a.

[0162] In the semiconductor element 5C, the first end 311a and second end 311b of the first metallic part 311 serving as the drain electrode 55 may be used as electrode pads of the drain electrode 55. Also, in the semiconductor element 5C, the first end 312a and second end 312b of the second metallic part 312 serving as the source electrode 56 may be used as electrode pads of the source electrode 56.

(2) Method for Fabricating -Ga.SUB.2.O.SUB.3.-Based Device

[0163] Next, an exemplary method for fabricating the -Ga.sub.2O.sub.3-based device 10C will be described briefly with reference to FIGS. 4A, 4B, 4E, 13, and 14. As for the same process steps as those of the method for fabricating the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, the description thereof will be omitted as appropriate herein.

[0164] The method for fabricating the -Ga.sub.2O.sub.3-based device 10C includes a substrate providing process step, a metal layer forming process step, an epitaxial growing process step, a drain/source region forming process step, an insulating film forming process step, an electrode forming process step, a patterning process step, and a dicing process step.

[0165] The substrate providing process step includes providing a Ga.sub.2O.sub.3-based substrate 2 having a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21 (refer to FIG. 4A). The Ga.sub.2O.sub.3-based substrate 2 is a wafer configured as a -Ga.sub.2O.sub.3 substrate 20 and is a wafer as a prototype of the Ga.sub.2O.sub.3-based substrate 2a.

[0166] The metal layer forming process step includes forming a metal layer 3 having a plurality of metallic parts 31 and a plurality of openings 32 on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 (refer to FIG. 4B). Each of the plurality of metallic parts 31 will be the metallic part 31a. The width of each of the plurality of metallic parts 31 is equal to the width of a corresponding one of the plurality of metallic parts 31a as measured in the second direction D22 (refer to FIGS. 13 and 14). On the other hand, the length of each of the plurality of metallic parts 31 is greater than the length of a corresponding one of the plurality of metallic parts 31a as measured in the first direction D21 (refer to FIG. 14).

[0167] The epitaxial growing process step includes forming a -Ga.sub.2O.sub.3 layer 4 by epitaxial lateral overgrowth using a mist CVD method to cover the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3 (refer to FIG. 4E). In this embodiment, the -Ga.sub.2O.sub.3 layer 4 is an n-type -Ga.sub.2O.sub.3 layer, which is a prototype of the -Ga.sub.2O.sub.3 layer 4a. The -Ga.sub.2O.sub.3 layer 4 is a prototype of the n-type -Ga.sub.2O.sub.3 layer 4a. An epitaxial wafer 1 is fabricated by performing the substrate providing process step, the metal layer forming process step, and the epitaxial growing process step. Alternatively, in the epitaxial growing process step, an MBE method or an HVPE method, for example, may be adopted instead of the mist CVD method.

[0168] The drain/source region forming process step includes forming a plurality of drain regions 51 (refer to FIG. 13) and a plurality of source regions 52 (refer to FIG. 13) in the -Ga.sub.2O.sub.3 layer 4 by, for example, ion implantation and diffusion techniques.

[0169] The insulating film forming process step includes forming a gate insulating film 54 by CVD method, for example.

[0170] The electrode forming process step includes forming a plurality of gate electrodes 57 by evaporation process, for example.

[0171] The patterning process step includes patterning the -Ga.sub.2O.sub.3 layer 4 by, for example, photolithographic and etching techniques, thereby exposing each of the plurality of metallic parts 31 partially and the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 partially.

[0172] According to this method for fabricating the -Ga.sub.2O.sub.3-based device 10C, a wafer including a plurality of -Ga.sub.2O.sub.3-based devices 10C may be obtained by performing the respective process steps from the substrate providing process step through the patterning process step.

[0173] According to the method for fabricating the -Ga.sub.2O.sub.3-based device 10C, a plurality of -Ga.sub.2O.sub.3-based devices 10C may be obtained by cutting off, in the dicing process step, the wafer including a plurality of -Ga.sub.2O.sub.3-based devices 10C using a dicing saw or a laser dicing device, for example.

(3) Advantages

[0174] A -Ga.sub.2O.sub.3-based device 10C according to the third embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5C. The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a. The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a. The -Ga.sub.2O.sub.3 layer 4a covers the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and the metal layer 3a. The semiconductor element 5C includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The metal layer 3a is made of a material such as a noble metal or a refractory metal. The thickness T12 of the -Ga.sub.2O.sub.3 layer 4a is smaller than the thickness T11 of the Ga.sub.2O.sub.3-based substrate 2a.

[0175] The -Ga.sub.2O.sub.3-based device 10C according to the third embodiment, having such a configuration, allows for contributing to improving the characteristics.

[0176] In the -Ga.sub.2O.sub.3-based device 10C according to the third embodiment, the semiconductor element 5C is a MOSFET. The drain region 51, source region 52, and channel forming region 53 of the MOSFET are defined in the -Ga.sub.2O.sub.3 layer 4a. This allows the -Ga.sub.2O.sub.3-based device 10C according to the third embodiment to contribute to improving the characteristics of a MOSFET serving as the semiconductor element 5C.

Fourth Embodiment

[0177] Next, a -Ga.sub.2O.sub.3-based device 10D according to a fourth embodiment and a method for fabricating the -Ga.sub.2O.sub.3-based device 10D will be described with reference to FIGS. 15 and 16. In the following description, any constituent element of the -Ga.sub.2O.sub.3-based device 10D according to this fourth embodiment, having the same function as a counterpart of the -Ga.sub.2O.sub.3-based device 10 (refer to FIGS. 6 and 7) according to the first embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

(1) -Ga.SUB.2.O.SUB.3.-Based Device

[0178] The -Ga.sub.2O.sub.3-based device 10D according to the fourth embodiment will be described with reference to FIGS. 15 and 16.

[0179] The -Ga.sub.2O.sub.3-based device 10D according to the fourth embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5D.

[0180] The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a.

[0181] The Ga.sub.2O.sub.3-based substrate 2a is a -Ga.sub.2O.sub.3 substrate 20a. Also, the -Ga.sub.2O.sub.3 substrate 20a is a semi-insulating -Ga.sub.2O.sub.3 substrate. The Ga.sub.2O.sub.3-based substrate 2a has a rectangular shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0182] The metal layer 3a may be made of a material such as a noble metal or a refractory metal. If a noble metal is used as a material for the metal layer 3a, the noble metal may be Pt or Au, for example, but may also be any noble metal other than Pt and Au. If a refractory metal is used as a material for the metal layer 3a, the refractory metal may be Ta or W, for example, but may also be any refractory metal other than Ta and W.

[0183] The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a.

[0184] The -Ga.sub.2O.sub.3 layer 4a covers the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a partially and the metal layer 3a partially. More specifically, the -Ga.sub.2O.sub.3 layer 4a covers not only each of three parts 211a, not covered with the metal layer 3a, of the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a partially but also the metal layer 3a partially.

[0185] The semiconductor element 5D includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The semiconductor element 5D will be described later.

[0186] In the -Ga.sub.2O.sub.3-based device 10D, the metal layer 3a includes two metallic parts 31a and two more metallic parts 31b (refer to FIG. 16). Each of the two metallic parts 31a and the two more metallic parts 31b has a linear (elongate) shape. One end of each of the two metallic parts 31a is connected to one of the two metallic parts 31b, while the other end of each of the two metallic parts 31a is connected to the other of the two metallic parts 31b. In the following description, the longitudinal axis of the two metallic parts 31a is herein defined to be a first direction D21 (refer to FIG. 16) and a direction perpendicular to both the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a and the first direction D21 is herein defined to be a second direction D22.

[0187] The semiconductor element 5D is a MOSFET, and includes a drain region 51, a source region 52, a channel forming region 53, a gate insulating film 54, a drain electrode 55, a source electrode 56, and a gate electrode 57 as shown in FIG. 15. The drain region 51, the source region 52, and the channel forming region 53 are defined in the -Ga.sub.2O.sub.3 layer 4a.

[0188] In the -Ga.sub.2O.sub.3-based device 10D, the Ga.sub.2O.sub.3-based substrate 2a is a semi-insulating -Ga.sub.2O.sub.3 substrate.

[0189] In the -Ga.sub.2O.sub.3-based device 10D, the -Ga.sub.2O.sub.3 layer 4a includes: a semi-insulating -Ga.sub.2O.sub.3 layer 43a in contact with the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and the metal layer 3a; and an n-type -Ga.sub.2O.sub.3 layer 44a formed on the semi-insulating -Ga.sub.2O.sub.3 layer 43a.

[0190] The drain region 51 is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer 44a. Each of the n-type -Ga.sub.2O.sub.3 layer 44a and the n.sup.+-type -Ga.sub.2O.sub.3 region serving as the drain region 51 contains an n-type impurity (such as Sn, Si, or Ge). The drain region 51 overlaps with one of the two metallic parts 31a in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0191] The source region 52 is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer 44a. Each of the n-type -Ga.sub.2O.sub.3 layer 44a and the n.sup.+-type -Ga.sub.2O.sub.3 region serving as the source region 52 contains an n-type impurity (such as Sn, Si, or Ge). The source region 52 overlaps with the other of the two metallic parts 31a in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a.

[0192] The channel forming region 53 is defined between the drain region 51 and the source region 52 in the n-type -Ga.sub.2O.sub.3 layer 4a.

[0193] The gate insulating film 54 is formed over the n-type -Ga.sub.2O.sub.3 layer 4a, the drain region 51, and the source region 52. Examples of materials for the gate insulating film 54 include silicon oxide, hafnium oxide, aluminum nitride, silicon nitride, and aluminum oxide.

[0194] The gate electrode 57 is formed on the gate insulating film 54. The gate electrode 57 is located between the drain region 51 and the source region 52 when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. A material for the gate electrode 57 may be Au or Pt, for example, but may also be a metal other than Au and Pt or an alloy.

[0195] The drain electrode 55 is formed on the drain region 51. The drain electrode 55 is electrically connected to the drain region 51.

[0196] The source electrode 56 is formed on the source region 52. The source electrode 56 is electrically connected to the source region 52.

[0197] The metal layer 3a has exposed parts which are not covered with the -Ga.sub.2O.sub.3 layer 4a. In the -Ga.sub.2O.sub.3-based device 10D, the -Ga.sub.2O.sub.3 layer 4a is formed in such a shape that exposes the two metallic parts 31b. The -Ga.sub.2O.sub.3 layer 4a has a rectangular shape when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. When measured in the second direction D22, the length of the -Ga.sub.2O.sub.3 layer 4a is equal to the length of the Ga.sub.2O.sub.3-based substrate 2a. When measured in the first direction D21, the length of the -Ga.sub.2O.sub.3 layer 4a is less than the length of the Ga.sub.2O.sub.3-based substrate 2a and less than the length of each metallic part 31a.

[0198] The -Ga.sub.2O.sub.3-based device 10D further includes two heat sinks 6. The two heat sinks 6 are arranged on the exposed parts of the metal layer 3a. More specifically, the two heat sinks 6 correspond one to one to the two metallic parts 31b of the metal layer 3a. Each of the two heat sinks 6 is disposed on a corresponding one of the two metallic parts 31b. Each of the two heat sinks 6 has a plate shape. Each of the two heat sinks 6 has the shape of a rectangle, of which the longitudinal axis is defined by the second direction D22, when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. Examples of materials for the two heat sinks 6 include aluminum, copper, an aluminum alloy, and a copper alloy.

(2) Method for Fabricating -Ga.SUB.2.O.SUB.3.-Based Device

[0199] Next, an exemplary method for fabricating the -Ga.sub.2O.sub.3-based device 10D will be described briefly with reference to FIGS. 4A, 15, and 16. As for the same process steps as those of the method for fabricating the -Ga.sub.2O.sub.3-based device 10 according to the first embodiment, description thereof will be omitted as appropriate herein.

[0200] The method for fabricating the -Ga.sub.2O.sub.3-based device 10D includes a substrate providing process step, a metal layer forming process step, an epitaxial growing process step, a drain/source region forming process step, an insulating film forming process step, an electrode forming process step, a patterning process step, a dicing process step, and a bonding process step.

[0201] The substrate providing process step includes providing a Ga.sub.2O.sub.3-based substrate 2 having a first principal surface 21 and a second principal surface 22 opposite from the first principal surface 21 (refer to FIG. 4A). The Ga.sub.2O.sub.3-based substrate 2 is a wafer configured as a -Ga.sub.2O.sub.3 substrate 20 and is a wafer as a prototype of the Ga.sub.2O.sub.3-based substrate 2a.

[0202] The metal layer forming process step includes forming, on the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2, a metal layer 3 as a prototype of the metal layer 3a.

[0203] The epitaxial growing process step includes forming a semi-insulating -Ga.sub.2O.sub.3 layer by epitaxial lateral overgrowth using a mist CVD method to cover the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3 and forming an n-type -Ga.sub.2O.sub.3 layer by a mist CVD method to cover the semi-insulating -Ga.sub.2O.sub.3 layer. The semi-insulating -Ga.sub.2O.sub.3 layer is a prototype of the semi-insulating -Ga.sub.2O.sub.3 layer 43a. The n-type -Ga.sub.2O.sub.3 layer is a prototype of the n-type -Ga.sub.2O.sub.3 layer 44a. Alternatively, in the epitaxial growing process step, an MBE method or an HVPE method, for example, may be adopted instead of the mist CVD method.

[0204] The drain/source region forming process step includes forming a plurality of drain regions 51 (refer to FIG. 15) and a plurality of source regions 52 (refer to FIG. 15) in the n-type -Ga.sub.2O.sub.3 layer by, for example, ion implantation and diffusion techniques.

[0205] The insulating film forming process step includes forming a plurality of gate insulating films 54 by CVD method, for example.

[0206] The electrode forming process step includes forming a plurality of drain electrodes 55, a plurality of source electrodes 56, and a plurality of gate electrodes 57 by evaporation process, for example.

[0207] The patterning process step includes patterning the -Ga.sub.2O.sub.3 layer by, for example, photolithographic and etching techniques, thereby exposing the metal layer 3 partially and the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 partially.

[0208] According to this method for fabricating the -Ga.sub.2O.sub.3-based device 10D, the dicing process step is performed after the patterning process step, and then the two heat sinks 6 are bonded to the exposed parts of the metal layer 3a.

(3) Advantages

[0209] A -Ga.sub.2O.sub.3-based device 10D according to the fourth embodiment includes a Ga.sub.2O.sub.3-based substrate 2a, a metal layer 3a, a -Ga.sub.2O.sub.3 layer 4a, and a semiconductor element 5D. The Ga.sub.2O.sub.3-based substrate 2a has a first principal surface 21a and a second principal surface 22a opposite from the first principal surface 21a. The metal layer 3a is formed selectively on the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a. The -Ga.sub.2O.sub.3 layer 4a covers the first principal surface 21a of the Ga.sub.2O.sub.3-based substrate 2a and the metal layer 3a. The semiconductor element 5D includes at least a part of the -Ga.sub.2O.sub.3 layer 4a. The metal layer 3a is made of a material such as a noble metal or a refractory metal. The thickness T12 of the -Ga.sub.2O.sub.3 layer 4a is smaller than the thickness T11 of the Ga.sub.2O.sub.3-based substrate 2a.

[0210] The -Ga.sub.2O.sub.3-based device 10D according to the fourth embodiment, having such a configuration, allows for contributing to improving the characteristics.

[0211] In the -Ga.sub.2O.sub.3-based device 10D according to the fourth embodiment, the semiconductor element 5D is a MOSFET. The drain region 51, source region 52, and channel forming region 53 of the MOSFET are defined in the -Ga.sub.2O.sub.3 layer 4a. The -Ga.sub.2O.sub.3-based device 10D according to the fourth embodiment includes the heat sinks 6 arranged on exposed parts of the metal layer 3a, thus allowing for improving the heat dissipation properties and thereby contributing to improving the characteristics of a MOSFET serving as the semiconductor element 5D.

Fifth Embodiment

[0212] Next, a -Ga.sub.2O.sub.3-based device 10E according to a fifth embodiment will be described with reference to FIG. 17. In the following description, any constituent element of the -Ga.sub.2O.sub.3-based device 10E according to this fifth embodiment, having the same function as a counterpart of the -Ga.sub.2O.sub.3-based device 10B (refer to FIGS. 9 and 10) according to the second embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

[0213] The -Ga.sub.2O.sub.3-based device 10E according to the fifth embodiment includes two semiconductor elements 5B and further includes a heat dissipating layer 7 and a heat sink 8, which is a difference from the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment.

[0214] The heat dissipating layer 7 is formed on the semiconductor elements 5B and has electrical insulation properties. The heat dissipating layer 7 partially covers the second metal electrode layer 59 of each of the two semiconductor elements 5B and also covers the -Ga.sub.2O.sub.3 layer 4a. The heat dissipating layer 7 contains an AlN filler. Note that the heat dissipating layer 7 is formed by, for example, applying a material including the AlN filler by spin coating or any other technique and then curing the material thus applied.

[0215] The heat sink 8 is disposed on the heat dissipating layer 7. The heat sink 8 has a plate shape. The heat sink 8 has the shape of a rectangle, of which the longitudinal axis is defined by the second direction D22, when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. Examples of materials for the heat sink 8 include aluminum, copper, an aluminum alloy, and a copper alloy.

[0216] The -Ga.sub.2O.sub.3-based device 10E according to the fifth embodiment includes the heat dissipating layer 7 and the heat sink 8, thus allowing for improving the heat dissipation properties.

Sixth Embodiment

[0217] Next, a -Ga.sub.2O.sub.3-based device 10F according to a sixth embodiment will be described with reference to FIG. 18. In the following description, any constituent element of the -Ga.sub.2O.sub.3-based device 10F according to this sixth embodiment, having the same function as a counterpart of the -Ga.sub.2O.sub.3-based device 10D (refer to FIGS. 15 and 16) according to the fourth embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

[0218] The -Ga.sub.2O.sub.3-based device 10F according to the sixth embodiment further includes a heat dissipating layer 7 and a heat sink 8, which is a difference from the -Ga.sub.2O.sub.3-based device 10D according to the fourth embodiment.

[0219] The heat dissipating layer 7 is formed on the semiconductor element 5D and has electrical insulation properties. The heat dissipating layer 7 partially covers the drain electrode 55, the source electrode 56, and the gate electrode 57 of the semiconductor elements 5D. The heat dissipating layer 7 contains an AlN filler. Note that the heat dissipating layer 7 is formed by, for example, applying a material including the AlN filler by spin coating or any other technique and then curing the material thus applied.

[0220] The heat sink 8 is disposed on the heat dissipating layer 7. The heat sink 8 has a plate shape. The heat sink 8 has the shape of a rectangle, of which the longitudinal axis is defined by the second direction D22, when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. Examples of materials for the heat sink 8 include aluminum, copper, an aluminum alloy, and a copper alloy.

[0221] The -Ga.sub.2O.sub.3-based device 10F according to the sixth embodiment includes the heat dissipating layer 7 and the heat sink 8, thus allowing for improving the heat dissipation properties.

Seventh Embodiment

[0222] Next, a -Ga.sub.2O.sub.3-based device 10G according to a seventh embodiment will be described with reference to FIGS. 19 and 20. In the following description, any constituent element of the -Ga.sub.2O.sub.3-based device 10G according to this seventh embodiment, having the same function as a counterpart of the -Ga.sub.2O.sub.3-based device 10C (refer to FIGS. 13 and 14) according to the third embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

[0223] The -Ga.sub.2O.sub.3-based device 10G according to the seventh embodiment includes a semiconductor element 5G instead of the semiconductor element 5C according to the third embodiment, which is a difference from the -Ga.sub.2O.sub.3-based device 10C according to the third embodiment described above.

[0224] In the -Ga.sub.2O.sub.3-based device 10G according to the seventh embodiment, the metal layer 3a includes three metallic parts 31a which are arranged side by side in the second direction D22 and the central one (31a) of the three metallic parts 31a in the second direction D22 serves as the gate electrode 57, which is a difference from the -Ga.sub.2O.sub.3-based device 10C according to the third embodiment described above.

[0225] In addition, the -Ga.sub.2O.sub.3-based device 10G according to the seventh embodiment further includes a gate insulating film 54 that covers the gate electrode 57. Examples of materials for the gate insulating film 54 include silicon oxide, hafnium oxide, aluminum nitride, silicon nitride, and aluminum oxide.

[0226] In the -Ga.sub.2O.sub.3-based device 10G according to the seventh embodiment, the -Ga.sub.2O.sub.3 layer 4a covers the gate insulating film 54 as well.

[0227] The -Ga.sub.2O.sub.3-based device 10G according to the seventh embodiment further includes a heat dissipating layer 7 and a heat sink 8, which is a difference from the -Ga.sub.2O.sub.3-based device 10C according to the third embodiment described above. Note that illustration of the heat dissipating layer 7 and the heat sink 8 is omitted in FIG. 20.

[0228] The heat dissipating layer 7 is formed on the semiconductor element 5G and has electrical insulation properties. The heat dissipating layer 7 covers the drain region 51, the source region 52, and the channel forming region 53 of the semiconductor element 5G and the -Ga.sub.2O.sub.3 layer 4a. The heat dissipating layer 7 contains an AlN filler. Note that the heat dissipating layer 7 is formed by, for example, applying a material including the AlN filler by spin coating or any other technique and then curing the material thus applied.

[0229] The heat sink 8 is disposed on the heat dissipating layer 7. The heat sink 8 has a plate shape. The heat sink 8 has the shape of a rectangle, of which the longitudinal axis is defined by the second direction D22, when viewed in plan in the thickness direction D20 defined with respect to the -Ga.sub.2O.sub.3-based substrate 2a. Examples of materials for the heat sink 8 include aluminum, copper, an aluminum alloy, and a copper alloy.

[0230] The -Ga.sub.2O.sub.3-based device 10G according to the seventh embodiment includes the heat dissipating layer 7 and the heat sink 8, thus allowing for improving the heat dissipation properties.

Eighth Embodiment

[0231] Next, a -Ga.sub.2O.sub.3-based device 10H according to an eighth embodiment and a method for fabricating the -Ga.sub.2O.sub.3-based device 10H will be described with reference to FIGS. 21, 22, 23A, 23B, and 23C. In the following description, any constituent element of the -Ga.sub.2O.sub.3-based device 10H according to this eighth embodiment, having the same function as a counterpart of the -Ga.sub.2O.sub.3-based device 10B (refer to FIGS. 9 and 10) according to the second embodiment described above, will be designated by the same reference numeral as that counterpart's, and description thereof will be omitted as appropriate herein.

(1) -Ga.SUB.2.O.SUB.3.-Based Device

[0232] The -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment will be described with reference to FIG. 21.

[0233] The -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment includes a heat sink 9 instead of the Ga.sub.2O.sub.3-based substrate 2a of the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment, which is a difference from the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment described above.

[0234] In addition, in the -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment, the shape of the metal layer 3a is different from that of the metal layer 3a of the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment.

[0235] The heat sink 9 has a plate shape. The heat sink 9 has the shape of a rectangle, of which the longitudinal axis is defined by the second direction D22, when viewed in plan in the thickness direction D20 defined with respect to the Ga.sub.2O.sub.3-based substrate 2a. Examples of materials for the heat sink 9 include aluminum, copper, an aluminum alloy, and a copper alloy.

(2) Method for Fabricating -Ga.SUB.2.O.SUB.3.-Based Device

[0236] Next, a method for fabricating the -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment will be described with reference to FIGS. 22, 23B, and 23C.

[0237] The method for fabricating the -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment, as well as the method for fabricating the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment, also includes a substrate providing process step, a metal layer forming process step, an epitaxial growing process step, an electrode layer forming process step, a patterning process step, and a dicing process step.

[0238] The method for fabricating the -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment further includes a laser liftoff process step and a bonding process step, which is a difference from the method for fabricating the -Ga.sub.2O.sub.3-based device 10B according to the second embodiment. The laser liftoff process step and the bonding process step are performed, for example, between the patterning process step and the dicing process step.

[0239] The substrate providing process step, the metal layer forming process step, the epitaxial growing process step, the electrode layer forming process step, and the patterning process step are substantially the same as those of the second embodiment described above, and description thereof will be omitted herein. The metal layer forming process step includes forming a metal layer 3, having a plurality of openings 32 which are arranged to form a two-dimensional array as shown in FIG. 22, on the Ga.sub.2O.sub.3-based substrate 2 (refer to FIG. 4A). The metal layer 3 is a prototype of the metal layer 3a. Each of the plurality of openings 32 has a square shape. The metal layer 3 has a grid shape.

[0240] The epitaxial growing process step includes forming an n.sup.+-type -Ga.sub.2O.sub.3 layer 41 (refer to FIG. 11) by epitaxial lateral overgrowth using a mist CVD method to cover the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2 and the metal layer 3 and forming an n-type -Ga.sub.2O.sub.3 layer 42 (refer to FIG. 11) by a mist CVD method to cover the n.sup.+-type -Ga.sub.2O.sub.3 layer 41. The n.sup.+-type -Ga.sub.2O.sub.3 layer 41 is a prototype of the n.sup.+-type -Ga.sub.2O.sub.3 layer 41a. The n-type -Ga.sub.2O.sub.3 layer 42 is a prototype of the n-type -Ga.sub.2O.sub.3 layer 42a. An epitaxial wafer 1B (refer to FIG. 11) is fabricated by performing the substrate providing process step, the metal layer forming process step, and the epitaxial growing process step. Alternatively, in the epitaxial growing process step, an MBE method or an HVPE method, for example, may be adopted instead of the mist CVD method. In this embodiment, the n.sup.+-type -Ga.sub.2O.sub.3 layer 41 and the n-type -Ga.sub.2O.sub.3 layer 42 form the -Ga.sub.2O.sub.3 layer 4.

[0241] The electrode layer forming process step includes forming a metal electrode layer 590 (refer to FIG. 23A) by evaporation, for example. Note that the electrode layer forming process step includes forming the metal electrode layer 590 on the -Ga.sub.2O.sub.3 layer 4. The metal electrode layer 590 is a prototype of the second metal electrode layer 59.

[0242] The patterning process step includes patterning the -Ga.sub.2O.sub.3 layer 4 by, for example, photolithographic and etching techniques, thereby exposing a part of the metal layer 3 and a part of the first principal surface 21 of the Ga.sub.2O.sub.3-based substrate 2.

[0243] The laser liftoff process step includes stripping the Ga.sub.2O.sub.3-based substrate 2 from the metal layer 3 and the -Ga.sub.2O.sub.3 layer 4 (refer to FIG. 23B) by irradiating the Ga.sub.2O.sub.3-based substrate 2 with a laser beam LB1 (refer to FIG. 23A) from the second principal surface 22 thereof.

[0244] The bonding process step includes bonding the heat sink 9 onto the exposed surface of the metal layer 3 and the exposed surface of the -Ga.sub.2O.sub.3 layer 4 (refer to FIG. 23C).

[0245] In the method for fabricating the -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment, the dicing process step is performed after the bonding process step, thereby obtaining a plurality of -Ga.sub.2O.sub.3-based devices 10H.

[0246] The method for fabricating the -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment allows for improving the heat dissipation properties of the -Ga.sub.2O.sub.3-based device 10H. 224 In the metal layer 3 formed by the method for fabricating the -Ga.sub.2O.sub.3-based device 10H according to the eighth embodiment, each of the plurality of openings 32 arranged to form a two-dimensional array may have a circular shape as shown in FIG. 24.

Variations

[0247] Note that the first to eighth embodiments and their variations described above are only exemplary ones of various embodiments of the present disclosure and their variations and should not be construed as limiting. Rather, the first to eighth embodiments and their variations may be readily modified in various manners depending on a design choice or any other factor without departing from the scope of the present disclosure.

[0248] For example, in the epitaxial wafers 1, 1A, the plurality of openings 32 of the metal layer 3 may be arranged to form a two-dimensional array as shown in FIG. 22 or 24. This makes it easier to further reduce the thickness of the Ga.sub.2O.sub.3-based substrate 2, 2A while the Ga.sub.2O.sub.3-based substrate 2, 2A is being polished from the second principal surface 22, 22A of the Ga.sub.2O.sub.3-based substrate 2, 2A.

[0249] Also, in the -Ga.sub.2O.sub.3-based devices 10, 10D, 10E, 10F, the metal layer 3 may have a plurality of openings 32 arranged to form a two-dimensional array as shown in FIG. 22 or 24. This makes it easier to further reduce the thickness of the Ga.sub.2O.sub.3-based substrate 2a, thus allowing the heat dissipation properties to be further improved.

[0250] Furthermore, the Ga.sub.2O.sub.3-based substrate 2 does not have to be the -Ga.sub.2O.sub.3 substrate 20 but may also be a -(Ga.sub.x, Al.sub.1-x).sub.2O.sub.3 substrate (where 0<x<1), for example. Furthermore, the Ga.sub.2O.sub.3-based substrate 2 does not have to be the -Ga.sub.2O.sub.3 substrate 20 but may also be an -Ga.sub.2O.sub.3 substrate or an -(Ga.sub.x, Al.sub.1-x).sub.2O.sub.3 substrate (where 0<x<1), for example. Optionally, the Ga.sub.2O.sub.3-based substrate 2 may contain Fe or Al as an impurity.

[0251] Furthermore, in the -Ga.sub.2O.sub.3-based device 10, the semiconductor element 5 is a MESFET. Alternatively, the semiconductor element 5 may also have a configuration including, instead of the -Ga.sub.2O.sub.3 layer 4a, a -Ga.sub.2O.sub.3 layer and a -(Ga.sub.x, Al.sub.1-x).sub.2O.sub.3 layer (where 0<x<1) formed on the -Ga.sub.2O.sub.3 layer. In that case, a high electron mobility transistor (HEMT) may be formed as the semiconductor element 5 instead of the MESFET.

[0252] The transistor serving as the semiconductor element included in the -Ga.sub.2O.sub.3-based device does not have to be the MESFET or the MOSFET but may also be a HEMT.

[0253] Furthermore, the FET serving as the semiconductor element included in the -Ga.sub.2O.sub.3-based device does not have to be a transverse FET in which a drain electrode and a source electrode are formed on the -Ga.sub.2O.sub.3 layer but may also be a longitudinal FET in which a drain electrode and a source electrode are arranged to be stacked one on top of the other in the thickness direction defined with respect to the -Ga.sub.2O.sub.3 layer.

[0254] Optionally, according to the method for fabricating the -Ga.sub.2O.sub.3-based device 10H, the Ga.sub.2O.sub.3-based substrate 2A may be used instead of the Ga.sub.2O.sub.3-based substrate 2.

Aspects

[0255] The foregoing description provides specific implementations for the following aspects of the present disclosure.

[0256] An epitaxial wafer (1; 1A) according to a first aspect includes a Ga.sub.2O.sub.3-based substrate (2; 2A), a metal layer (3), and a -Ga.sub.2O.sub.3 layer (4). The Ga.sub.2O.sub.3-based substrate (2; 2A) has a first principal surface (21; 21A) and a second principal surface (22; 22A) opposite from the first principal surface (21; 21A). The metal layer (3) is formed on the first principal surface (21; 21A) of the Ga.sub.2O.sub.3-based substrate (2; 2A). The metal layer (3) has a plurality of openings (32). The -Ga.sub.2O.sub.3 layer (4) covers the first principal surface (21; 21A) of the Ga.sub.2O.sub.3-based substrate (2; 2A) and the metal layer (3). The metal layer (3) is made of a material such as a noble metal or a refractory metal. The thickness (T2) of the -Ga.sub.2O.sub.3 layer (4) is smaller than the thickness (T1) of the Ga.sub.2O.sub.3-based substrate (2; 2A).

[0257] This aspect may contribute to improving the characteristics of a -Ga.sub.2O.sub.3-based device.

[0258] In an epitaxial wafer (1; 1A) according to a second aspect, which may be implemented in conjunction with the first aspect, the metal layer (3) includes a plurality of metallic parts (31). Each of the plurality of metallic parts (31) is linear. In the metal layer (3), the plurality of metallic parts (31) and the plurality of openings (32) are arranged alternately when viewed in plan in a thickness direction (D10) defined with respect to the Ga.sub.2O.sub.3-based substrate (2; 2A).

[0259] This aspect makes it easier to make the Ga.sub.2O.sub.3-based substrate (2; 2A) even thinner when the Ga.sub.2O.sub.3-based substrate (2; 2A) is polished from the second principal surface (22; 22A) of the Ga.sub.2O.sub.3-based substrate (2; 2A).

[0260] In an epitaxial wafer (1; 1A) according to a third aspect, which may be implemented in conjunction with the first aspect, in the metal layer (3), the plurality of openings (32) are arranged to form a two-dimensional array.

[0261] This aspect makes it easier to make the Ga.sub.2O.sub.3-based substrate (2; 2A) even thinner when the Ga.sub.2O.sub.3-based substrate (2; 2A) is polished from the second principal surface (22; 22A) of the Ga.sub.2O.sub.3-based substrate (2; 2A).

[0262] In an epitaxial wafer (1) according to a fourth aspect, which may be implemented in conjunction with any one of the first to third aspects, the Ga.sub.2O.sub.3-based substrate (2) is a -Ga.sub.2O.sub.3 substrate (2; 2A).

[0263] This aspect makes it easier to provide the Ga.sub.2O.sub.3-based substrate (2).

[0264] In an epitaxial wafer (1A) according to a fifth aspect, which may be implemented in conjunction with any one of the first to third aspects, the Ga.sub.2O.sub.3-based substrate (2A) includes: a sapphire substrate (24); and a -Ga.sub.2O.sub.3 layer (25) formed on the sapphire substrate (24). In the Ga.sub.2O.sub.3-based substrate (2A), a surface (251) of the -Ga.sub.2O.sub.3 layer (25) forms the first principal surface (21A) of the Ga.sub.2O.sub.3-based substrate (2A).

[0265] This aspect may contribute to cutting down the cost.

[0266] A -Ga.sub.2O.sub.3-based device (10; 10B; 10C; 10D; 10E; 10F; 10G) according to a sixth aspect includes a Ga.sub.2O.sub.3-based substrate (2a), a metal layer (3a), a -Ga.sub.2O.sub.3 layer (4a), and a semiconductor element (5; 5B; 5C; 5D; 5G). The Ga.sub.2O.sub.3-based substrate (2a) has a first principal surface (21a) and a second principal surface (22a) opposite from the first principal surface (21a). The metal layer (3a) is formed selectively on the first principal surface (21a) of the Ga.sub.2O.sub.3-based substrate (2a). The -Ga.sub.2O.sub.3 layer (4a) covers the first principal surface (21a) of the Ga.sub.2O.sub.3-based substrate (2a) and the metal layer (3a). The semiconductor element (5; 5B; 5C; 5D; 5G) includes at least a part of the -Ga.sub.2O.sub.3 layer (4a). The metal layer (3a) is made of a material such as a noble metal or a refractory metal. The thickness (T12) of the -Ga.sub.2O.sub.3 layer (4a) is smaller than the thickness (T11) of the Ga.sub.2O.sub.3-based substrate (2a).

[0267] This aspect may contribute to improving the characteristics of the -Ga.sub.2O.sub.3-based device (10; 10B; 10C; 10D; 10E; 10F; 10G).

[0268] In a -Ga.sub.2O.sub.3-based device (10; 10C; 10D; 10E; 10F; 10G) according to a seventh aspect, which may be implemented in conjunction with the sixth aspect, the metal layer (3a) includes a plurality of metallic parts (31a). Each of the plurality of metallic parts (31a) is linear. In the metal layer (3a), the plurality of metallic parts (31a) are arranged to be spaced from each other in a direction perpendicular to each of the plurality of metallic parts (31a) when viewed in plan in a thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a).

[0269] This aspect allows for improving the heat dissipation properties.

[0270] In a -Ga.sub.2O.sub.3-based device (10) according to an eighth aspect, which may be implemented in conjunction with the seventh aspect, the semiconductor element (5) is a MESFET including a drain region (51), a source region (52), a channel forming region (53), a drain electrode (55), a source electrode (56), and a gate electrode (57). The drain region (51), the source region (52), and the channel forming region (53) are defined in the -Ga.sub.2O.sub.3 layer (4a). The channel forming region (53) overlaps with one metallic part (31a) out of the plurality of metallic parts (31a) when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a).

[0271] This aspect may contribute to improving the characteristics of a MESFET serving as the semiconductor element (5).

[0272] In a -Ga.sub.2O.sub.3-based device (10) according to a ninth aspect, which may be implemented in conjunction with the eighth aspect, the Ga.sub.2O.sub.3-based substrate (2a) is a semi-insulating -Ga.sub.2O.sub.3 substrate. The -Ga.sub.2O.sub.3 layer (4a) is an n-type -Ga.sub.2O.sub.3 layer. The drain region (51) is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined within the n-type -Ga.sub.2O.sub.3 layer (4a). The drain region (51) has a comb shape. The source region (52) is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined within the n-type -Ga.sub.2O.sub.3 layer (4a). The source region (52) has a comb shape. The drain electrode (55) is formed on the drain region (51). The drain electrode (55) has a shape of a comb overlapping with the drain region (51) when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a). The source electrode (56) is formed on the source region (52). The source electrode (56) has a shape of a comb overlapping with the source region (52) when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a). The gate electrode (57) is formed on the n-type -Ga.sub.2O.sub.3 layer (4a). The gate electrode (57) has a shape of a comb when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a). The drain electrode (55) includes: a drain electrode comb backbone (551); and a plurality of drain electrode comb teeth (552) extending from the drain electrode comb backbone (551). The source electrode (56) includes: a source electrode comb backbone (561); and a plurality of source electrode comb teeth (562) extending from the source electrode comb backbone (561). The gate electrode (57) includes: a gate electrode comb backbone (571); and a plurality of gate electrode comb teeth (572) extending from the gate electrode comb backbone (571). The drain electrode comb backbone (551) and the source electrode comb backbone (561) face each other in a first direction (D21). The plurality of drain electrode comb teeth (552), the plurality of gate electrode comb teeth (572), and the plurality of source electrode comb teeth (562) are arranged side by side in a second direction (D22) perpendicular to both the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a) and the first direction (D21). Each of the plurality of gate electrode comb teeth (572) overlaps with any one metallic part (31a) out of the plurality of metallic parts (31a) when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a).

[0273] This aspect may not only improve the stability of operation of a MEFET serving as the semiconductor element (5) but also increase the breakdown voltage thereof as well.

[0274] In a -Ga.sub.2O.sub.3-based device (10) according to a tenth aspect, which may be implemented in conjunction with the ninth aspect, each of the plurality of gate electrode comb teeth (572) is arranged to be offset in the second direction (D22) to avoid overlapping with a center of the one metallic part (31a) in the second direction (D22) when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a).

[0275] This aspect may further improve the characteristics of the semiconductor element (5).

[0276] In a -Ga.sub.2O.sub.3-based device (10; 10D; 10E; 10F) according to an eleventh aspect, which may be implemented in conjunction with the sixth aspect, the metal layer (3) has a plurality of openings (32) which are arranged to form a two-dimensional array.

[0277] This aspect makes it easier to further reduce the thickness of the Ga.sub.2O.sub.3-based substrate (2a) and improve the heat dissipation properties thereof.

[0278] In a -Ga.sub.2O.sub.3-based device (10B) according to a twelfth aspect, which may be implemented in conjunction with the sixth aspect, the semiconductor element (5B) is a Schottky barrier diode. The Ga.sub.2O.sub.3-based substrate (2a) is a semi-insulating -Ga.sub.2O.sub.3 substrate. The -Ga.sub.2O.sub.3 layer (4a) includes: an n.sup.+-type -Ga.sub.2O.sub.3 layer (41a) covering the first principal surface (21a) of the Ga.sub.2O.sub.3-based substrate (2a) and the metal layer (3a); and an n-type -Ga.sub.2O.sub.3 layer (42a) formed on the n.sup.+-type -Ga.sub.2O.sub.3 layer (41a). The n.sup.+-type -Ga.sub.2O.sub.3 layer (41a) makes ohmic contact with the metal layer (3a). The semiconductor element (5B) includes: a first metal electrode layer (58) formed out of the metal layer (3a); the n.sup.+-type -Ga.sub.2O.sub.3 layer (41a); the n-type -Ga.sub.2O.sub.3 layer (42a); and a second metal electrode layer (59). The second metal electrode layer (59) is formed on, and makes Schottky contact with, the n-type -Ga.sub.2O.sub.3 layer (42a). In the semiconductor element (5B), at least a part of the second metal electrode layer (59) and at least a part of the first metal electrode layer (58) overlap with each other when viewed in plan in a thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a). In the semiconductor element (5B), the second metal electrode layer (59) serves as an anode electrode and the n.sup.+-type -Ga.sub.2O.sub.3 layer (41) and the first metal electrode layer (58) serve as a cathode electrode.

[0279] This aspect may improve the characteristics of a Schottky barrier diode serving as the semiconductor element (5B).

[0280] In a -Ga.sub.2O.sub.3-based device (10C; 10D; 10F; 10G) according to a thirteenth aspect, which may be implemented in conjunction with the seventh aspect, the semiconductor element (5C; 5D; 5G) is a MOSFET including a drain region (51), a source region (52), a channel forming region (53), a gate insulating film (54), a drain electrode (55), a source electrode (56), and a gate electrode (57). The drain region (51), the source region (52), and the channel forming region (53) are defined in the -Ga.sub.2O.sub.3 layer (4a).

[0281] This aspect may contribute to improving the characteristics of a MOSFET serving as the semiconductor element (5C; 5D; 5G).

[0282] In a -Ga.sub.2O.sub.3-based device (10C) according to a fourteenth aspect, which may be implemented in conjunction with the thirteenth aspect, the Ga.sub.2O.sub.3-based substrate (2a) is a semi-insulating -Ga.sub.2O.sub.3 substrate. The -Ga.sub.2O.sub.3 layer (4a) is an n-type -Ga.sub.2O.sub.3 layer. The plurality of metallic parts (31a) includes a first metallic part (311) and a second metallic part (312) which are adjacent to each other in a direction in which the plurality of metallic parts (31a) are arranged side by side. The drain region (51) is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined on the first metallic part (311) in the -Ga.sub.2O.sub.3 layer (4a). The source region (52) is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined on the second metallic part (312) in the -Ga.sub.2O.sub.3 layer (4a). The first metallic part (311) serves as the drain electrode (55). The second metallic part (312) serves as the source electrode (56). The gate insulating film (54) is formed on the -Ga.sub.2O.sub.3 layer (4a). The gate electrode (57) is formed on the gate insulating film (54). The gate electrode (57) is located between the drain region (51) and the source region (52) when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a). The -Ga.sub.2O.sub.3 layer (4a) is formed in such a shape as to expose a part of the first metallic part (311) and a part of the second metallic part (312).

[0283] In a -Ga.sub.2O.sub.3-based device (10D) according to a fifteenth aspect, which may be implemented in conjunction with the thirteenth aspect, the -Ga.sub.2O.sub.3 layer (4a) includes: a semi-insulating -Ga.sub.2O.sub.3 layer (43a) in contact with the metal layer (3a); and an n-type -Ga.sub.2O.sub.3 layer (44a) formed on the semi-insulating -Ga.sub.2O.sub.3 layer (43a). The drain region (51) is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer (44a). The source region (52) is configured as an n.sup.+-type -Ga.sub.2O.sub.3 region defined in the n-type -Ga.sub.2O.sub.3 layer (44a). The gate insulating film (54) is formed on the n-type -Ga.sub.2O.sub.3 layer (44a). The gate electrode (57) is formed on the gate insulating film (54). The gate electrode (57) is located between the drain region (51) and the source region (52) when viewed in plan in the thickness direction (D20) defined with respect to the Ga.sub.2O.sub.3-based substrate (2a). The drain electrode (55) is formed on the drain region (51). The source electrode (56) is formed on the source region (52).

[0284] A -Ga.sub.2O.sub.3-based device (10D) according to a sixteenth aspect, which may be implemented in conjunction with the fifteenth aspect, further includes a heat sink (6). The metal layer (3a) has an exposed part not covered with the -Ga.sub.2O.sub.3 layer (4a). The heat sink (6) is disposed on the exposed part of the metal layer (3a).

[0285] This aspect allows for improving the heat dissipation properties.

[0286] A -Ga.sub.2O.sub.3-based device (10E; 10F; 10G) according to a seventeenth aspect, which may be implemented in conjunction with the sixth aspect, further includes a heat dissipating layer (7) and a heat sink (8). The heat dissipating layer (7) is formed on the semiconductor element (5B; 5D; 5G) and has electrical insulation properties. The heat sink (8) is disposed on the heat dissipating layer (7). The heat dissipating layer (7) contains an AlN filler.

[0287] This aspect allows for improving the heat dissipation properties.

[0288] A method for fabricating a -Ga.sub.2O.sub.3-based device (10; 10B; 10C; 10D; 10E; 10F; 10G; 10H) according to an eighteenth aspect includes a substrate providing process step, a metal layer forming process step, and an epitaxial growing process step. The substrate providing process step includes providing a Ga.sub.2O.sub.3-based substrate (2; 2A) having a first principal surface (21) and a second principal surface (22) opposite from the first principal surface (21). The metal layer forming process step includes forming a metal layer (3) having a plurality of openings (32) on the first principal surface (21; 21A) of the Ga.sub.2O.sub.3-based substrate (2; 2A). The epitaxial growing process step includes forming a -Ga.sub.2O.sub.3 layer (4) that covers the first principal surface (21; 21A) of the Ga.sub.2O.sub.3-based substrate (2; 2A) and the metal layer (3) by epitaxial lateral overgrowth using a mist CVD method. The metal layer (3) is made of a material such as a noble metal or a refractory metal. The thickness (T12) of the -Ga.sub.2O.sub.3 layer (4) is smaller than the thickness (T11) of the Ga.sub.2O.sub.3-based substrate (2; 2A).

[0289] This aspect may contribute to improving the characteristics of the -Ga.sub.2O.sub.3-based device (10; 10B; 10C; 10D; 10E; 10F; 10G; 10H).

[0290] A method for fabricating a -Ga.sub.2O.sub.3-based device (10H) according to a nineteenth aspect, which may be implemented in conjunction with the eighteenth aspect, further includes a laser liftoff process step and a bonding process step. The laser liftoff process step includes stripping the Ga.sub.2O.sub.3-based substrate (2; 2A) from the metal layer (3) and the -Ga.sub.2O.sub.3 layer (4) by irradiating the Ga.sub.2O.sub.3-based substrate (2; 2A) with a laser beam (LB1) through the second principal surface (22; 22A) of the Ga.sub.2O.sub.3-based substrate (2; 2A). The bonding process step includes bonding a heat sink (9) onto an exposed surface of the metal layer (3) and an exposed surface of the -Ga.sub.2O.sub.3 layer (4).

[0291] This aspect may contribute to improving the heat dissipation properties of the -Ga.sub.2O.sub.3-based device (10H).

[0292] While the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that they may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all modifications and variations that fall within the true scope of the present teachings.