Diffractive optical elements and master tools for producing the diffractive optical elements

Abstract

The present disclosure describes diffractive optical elements (DOEs) and master tools for producing the DOEs. In one aspect, the disclosure describes a method that includes modifying a first pixel layout design for diffractive optical elements to obtain a modified pixel layout design. The first pixel layout design comprises pixels, each of which has a shape of a regular polygon (e.g., a rectangular shape). Modifying the first pixel layout design includes approximating a shape contour of a cluster of pixels in the first pixel layout design by a single polygon that reduces a total number of edges relative to the shape contour of the cluster of pixels in the first pixel layout design. The method also includes using the modified pixel layout design to form a master tool for production of the diffractive optical elements.

Claims

1. A method comprising: modifying a first pixel layout design for diffractive optical elements to obtain a modified pixel layout design, wherein the first pixel layout design comprises pixels, each of which has a rectangular shape, and wherein modifying the first pixel layout design includes approximating a contour of a cluster of pixels in the first pixel layout design by a single polygon that reduces a total number of edges relative to the contour of the cluster of pixels in the first pixel layout design; and using the modified pixel layout design to form a master tool for production of the diffractive optical elements.

2. The method of claim 1 including performing the modifying with respect to one or more clusters of pixels in each of different levels of the first pixel layout design.

3. The method of claim 1 wherein modifying the first pixel layout design includes approximating the contour of the cluster of pixels in the first pixel layout design by a single polygon that shortens an overall length of the edges relative to the contour of the cluster of pixels in the first pixel layout design.

4. The method of claim 1 wherein approximating the contour of the cluster of pixels includes replacing a zig-zag portion of a contour of the cluster of pixels with a straight line.

5. The method of claim 4 including determining the straight line by minimizing a difference between (i) a first area of the pixels in the cluster, wherein the first area is beyond a boundary of the approximated contour defined in part by the straight line and (ii) a second area that is not part of the pixels in the cluster and that is within the boundary.

6. The method of claim 1 wherein approximating the contour of the cluster of pixels includes replacing each corner node in the cluster with a respective pair of nodes.

7. The method of claim 6 wherein approximating the contour of the cluster of pixels includes replacing each corner node in the cluster with a respective pair of nodes, each of which is displaced relative to the corner node.

8. The method of claim 1 including: merging a plurality of clusters of pixels, whose contour coincides in at least one point, in the first pixel layout design to obtain a merged cluster of pixels, and approximating a contour of the merged cluster of pixels by replacing each corner node in the contour of the merged cluster with a respective pair of nodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A-1C illustrate an example of replacing a portion of an original pixel layout design with a modified pixel layout design.

(2) FIGS. 2A-2D illustrate another example of replacing a portion of an original pixel layout design with a modified pixel layout design.

(3) FIG. 3A is an example of a portion of an original pixel layout design.

(4) FIG. 3B is a modified pixel layout design for the original pixel layout design of FIG. 3A.

(5) FIGS. 4A-4I illustrate an example of a process of fabricating a master tool based on a modified pixel layout design.

(6) FIGS. 5A-5C are an example of how line edge roughness in a pixel layout design can be reduced in some implementations.

(7) FIGS. 6A and 6B are images of portions of a master tool.

DETAILED DESCRIPTION

(8) One of the initial tasks in fabricating DOEs is to determine a pixel layout design based on the desired optical performance and design criteria of the optical elements. In this context, a pixel refers to the smallest building block used when making the optical design. Typically, each pixel in the design has a regular polygonal shape (e.g., rectangular or square) whose sides may have dimensions on the order of several hundred nanometers (nm) or less. The layout design can include the pixel layout corresponding to an individual DOE, as well as the overall layout for wafer-level production. The depth of the pixels in the DOE structure may differ from one another. Thus, the pixel layout design may include two or more levels, each of which corresponds to a different depth. In some instances there may be as many four or sixteen different levels, although the particular number of levels will depend on the optical performance and functionality needed for the particular application. The pixel layout design includes a respective pattern or other layout of pixels for each level, and can include, for example, microstructures and/or nanostructures. A master tool then is prepared based on the pixel layout design. Thus, the master tool can include a multi-level structured surface that corresponds to the pixel layout design. The structured surface can be transferred (e.g., by replication) to other materials.

(9) The inventor(s) of the present disclosure recognized that various advantages may be obtained in some cases by approximating the contour of a cluster of pixels in a particular level of the original layout design in which each of the individual pixels has the contour of a regular polygon (e.g., a rectangle or square). The overall contour of a particular cluster of original regular polygonal pixels can be approximated, for example, by a single polygon that reduces the total number of edges and shortens the total length of the edges relative to the contour of the cluster of pixels in the original layout design. The contour of the replacement polygon may have fewer corners and/or less zig-zag than the corresponding cluster of pixels in the original design. This technique may be applied to some or all clusters of pixels at each level of the pixel layout design. The approximated contours of the clusters of pixels (i.e., the replacement polygons) then can be used in a replacement layout design to form the master tool for the DOEs as described in greater detail below.

(10) FIGS. 1A and 1B illustrate an example in which part of the zig-zag contour (i.e., the edges) of a cluster 20 of pixels 22 in an original pixel layout design (FIG. 1A) is approximated by a straight line 24 (FIG. 1B). In some instances, determination of the straight line 24 can be achieved by minimizing the difference between (i) the area of the original pixels that would be outside the contour defined in part by the straight line 24 (i.e., areas 26, 28, 30, 32, 34 in FIG. 1B) and (ii) the area that would be within the contour defined in part by the straight line 24 and that was not part of the area of the original pixels (i.e., areas 36, 38, 40, 42, 44 in FIG. 1B). The foregoing technique also can be applied to one or more other portions of the contour of the cluster 20 of original pixels. The contour of the cluster 20 of original pixels (FIG. 1A) then would be replaced with a contour having an edge defined by the straight line 24, as shown in FIG. 1C. Other portions of the zig-zag contour of the cluster 20 of pixels 22 in the original pixel layout design can be approximated by straight lines in a similar manner.

(11) In minimizing the difference between (i) and (ii) as set forth above, further constraints also may be used in some instances. For example, the difference between (i) and (ii) can be minimized while the number of nodes (i.e., corners of the original pixels 22) required to define the line 24 is reduced by at least a specified amount (e.g., 40% or 60%) relative to the number of nodes that define the edge in the original pixel design. Thus, in the example of FIGS. 1A-1C, there are fourteen nodes (corners) that define the edge 38 in the original cluster 20 of pixels 22, whereas only two nodes are needed to define the straight line 24.

(12) Using the foregoing technique to approximate the contour of a cluster of pixels in a particular level of the original layout design can result, in some instances, in the contour of the replacement polygon having less zig-zag than the contour of the original cluster of pixels. For example, assuming the contour of the original cluster of pixels is only along the x or y axes, portions of the contour of the replacement polygon may be inclined or slanted in the x-y plane (see FIG. 1C). Thus, the contour of the cluster of pixels in the modified layout design may change direction at an angle of ninety degrees, as well as at angles of more or less than ninety degrees (e.g., 0<<90 or 90<<180). In some cases, the contour may change direction by an angle , where 2<<88 or 92<<178. Further, in some cases, the contour may change direction by an angle , where 5<<85 or 95<<175.

(13) FIGS. 2A though 2D illustrate another technique for approximating the contour of one or more clusters of pixels in a particular level of the original layout design. FIG. 2A shows an example of two clusters 120A, 120B of pixels 122 in the original optical design. Each cluster 120A, 120B includes a respective set of contiguous pixels, each of which has at least one edge in contact with an edge of another pixel in the same cluster. In the illustrated example, no edge of a pixel in the first cluster 120A contacts an edge of a pixel in the second cluster 120B. On the other hand, a corner of at least one pixel 122A in the first cluster 120A is in with contact a corner of a pixel 122B in the second cluster 120B. In such a situation, it may be desirable to merge the two clusters 120A, 120B into a single larger merged cluster, as discussed below.

(14) In some implementations, to obtain the merged cluster, a sizing modification is performed in which a dimension (e.g., length of the edges) of each pixel 122 in both clusters 120A, 120B is increased slightly. For example, if the size of each pixel in the original design is 500 nm.sup.2, the edges of each pixel can be increased, e.g., by 1 nm. As shown in FIG. 2B, the enlarged pixels 122X overlap one another somewhat (i.e., overlapping regions 122Y). The clusters containing the enlarged pixels 122X then can be merged into a single merged cluster 120C, as shown in FIG. 2C.

(15) The contour of the merged cluster 120C of pixels then can be approximated by a polygon that has fewer corners and/or less zig-zag than the corresponding cluster(s) of pixels in the original design (FIG. 2A). This approximation can be accomplished, for example, by replacing a node at each corner of the merged cluster 120C with two nodes, each of which is displaced relative to the corner node and then removing duplicate nodes. FIG. 2D illustrates an example, in which the contour 124 of the replacement polygon (dashed line) is overlaid on the merged cluster 120C (solid line).

(16) The corner node replacement can be implemented, for example, as follows. The position of each corner node of the merged cluster can be stored in memory. The information for the corner nodes can be stored sequentially, for example, in a clockwise or counterclockwise direction along the contour of the merged cluster. Each corner node is replaced by two new nodes in a manner that depends on whether the algorithm proceeds from one corner node to the next in the clockwise direction or counterclockwise direction. For example, if movement proceeds in the clockwise direction, then each corner node can be replaced as indicated in the following Table, in which each node may be referred to as a point, and where pixel/2 is half the length of a pixel edge.

(17) TABLE-US-00001 TABLE 1 New Clock- replacement New replacement wise Conditions node #1 node #2 Sit- X coordinate for point Point 1: i + 1 Point 2: i + 2 uation i + 1 > X coordinate for New X New X coordinate: 1 point i + 2 coordinate: X X value for point AND value for point i + 1 pixel/2 Y coordinate for point i > Y i + 1 New Y coordinate: coordinate for point i + 1 New Y Y value for point coordinate: Y i + 1 value for point i + 1 + pixel/2 Sit- Y coordinate for point Point 1: i + 1 Point 2: i + 2 uation i + 2 > Y coordinate for New X New X coordinate: 2 point i + 1 coordinate: X X value for point AND value for point i + 1 X coordinate for point i > X i + 1 + pixel/2 New Y coordinate: coordinate for point i + 1 New Y Y value for point coordinate: Y i + 1 value for point i + 1 + pixel/2 Sit- X coordinate for point Point 1: i + 1 Point 2: i + 2 uation i + 1 > X coordinate New X New X coordinate: 3 for point i coordinate: X X value for point AND value for point i + 1 Y coordinate for point i + 1 pixel/2 New Y coordinate: i + 1 > Y coordinate for New Y Y value for point point i + 2 coordinate: Y i + 1 pixel/2 value for point i + 1 Sit- Y coordinate for point Point 1: i + 1 Point 2: i + 2 uation i + 1 > Y coordinate New X New X coordinate: 4 for point i coordinate: X X value for point AND value for point i + 1 + pixel/2 X coordinate for i + 1 New Y coordinate: point i + 2 > New Y Y value for point X coordinate for point i + 1 coordinate: Y i + 1 value for point i + 1 pixel/2

(18) On the other hand, if movement proceeds in the counterclockwise direction, then each corner node can be replaced as indicated in the following Table, in which each node may be referred to as a point, and where pixel/2 is half the length of a pixel edge.

(19) TABLE-US-00002 TABLE 2 Coun- ter New clock- replacement New replacement wise Conditions node #1 node #2 Sit- X coordinate for point Point 1: i + 1 Point 2: i + 2 uation i + 1 > X coordinate New X New X coordinate: 1 for point i coordinate: X X value for point AND value for point i + 1 Y coordinate for point i + 1 pixel/2 New Y coordinate: i + 2 > Y coordinate for New Y Y value for point point i + 1 coordinate: Y i + 1 + pixel/2 value for point i + 1 Sit- Y coordinate for point i > Y Point 1: i + 1 Point 2: i + 2 uation coordinate for point i + 1 New X New X coordinate: 2 AND coordinate: X X value for point X coordinate for point value for point i + 1 + pixel/2 i + 2 > X coordinate i + 1 New Y coordinate: for point i + 1 New Y Y value for point coordinate: Y i + 1 value for point i + 1 + pixel/2 Sit- X coordinate for point Point 1: i + 1 Point 2: i + 2 uation i + 1 > X coordinate for New X New X 3 point i + 2 coordinate: X coordinate: X value AND value for point for point i + 1 Y coordinate for point i + 1 pixel/2 i + 1 > Y coordinate New Y New Y for point i coordinate: Y coordinate: Y value value for point for point i + 1 i + 1 pixel/2 Sit- X coordinate for point i > X Point 1: i + 1 Point 2: i + 2 uation coordinate for point i + 1 New X New X coordinate: 4 AND coordinate: X X value for point Y coordinate for point value for point i + 1 i +1 > Y coordinate for i + 1 + pixel/2 New Y coordinate: point i + 2 New Y Y value for point coordinate: Y i + 1 pixel/2 value for point i + 1

(20) In some instances, a correction may be applied to the positions of the replacement nodes to compensate for the sizing operation that was described in connection with FIG. 2B.

(21) Further, in some instances, the sizing and merging operations may be omitted. For example, if different clusters of pixels in the original design do not have respective corners in contact with one another (i.e., as shown in the example of FIG. 2A), the cluster sizing and merging operations need not be performed. In such cases, the contour approximation operations (e.g., FIG. 2D) can be performed with respect to a cluster of pixels in the original layout design rather than a merged cluster.

(22) FIG. 3A illustrates another example of a portion of an original pixel layout design. FIG. 3B illustrates a corresponding example in which the contours of the original pixel layout design of FIG. 3A are replaced by new contours that approximate, respectively, the contours of the original layout design in accordance with the techniques described above. The replacement contours in FIG. 3B may have fewer corners and/or less zig-zag than the contours of the corresponding clusters of pixels in the original layout design of FIG. 3A. In general, as noted above, the straight portions of the contour can have a length that is greater than then the pixel size (i.e., greater than the center-to-center distance between two adjacent pixels having a common corner).

(23) The contours of the original pixel clusters at each level of the original layout design may be replaced by new contours that approximate, respectively, the contours of the original layout design in accordance with the techniques described above to obtain a modified pixel design layout. The modified pixel layout design then can be used to fabricate a master tool (e.g., having a multi-level structured surface corresponding to the modified pixel layout design) for the DOEs. In general, the contour delineates, at least in part, the area of the optical element having an optical function.

(24) FIGS. 4A-4I illustrate an example of a process of fabricating a master tool based on a modified pixel layout design.

(25) As shown, for example, in FIG. 4A, a substrate, such as a wafer 200, is provided. The wafer 200 can be composed, for example, of a layer of polysilicon, pure single-crystalline silicon or amorphous silicon on glass or sapphire. Other materials for the wafer 200 may be appropriate in some implementations. An additive lithography process, for example, can be used to form the different levels for the design of the master tool. An additive lithographic technique allows for careful control of the resist exposure and reflow processes for fabricating the master tool for complex, multi-level optical elements. The optical design can be transformed into a multilevel diffractive structure which then can be split into multiple masking patterns. An example is described below.

(26) For example, as part of the process of fabricating the master tool, a first layer of resist 202 is deposited (e.g., by spin coating) onto the upper surface of the wafer 200 and, using a first mask, the resist layer 202 is exposed selectively by lithographic techniques, e.g., electron beam lithography (EBL). The exposed portions of the resist layer 202 then are developed and removed such that selected regions of the wafer surface are no longer covered by the resist (see FIG. 4B). Next, as indicated in FIG. 2B, the wafer 200 is etched, from the wafer surface, in the regions not covered by the resist 202 to form openings 216 down to a first depth d1. The remaining portions of the resist 202 then can be removed. The resulting first level pattern 216 is shown in FIG. 4C.

(27) Next, as shown in FIG. 4D, in preparation for a second etch into the wafer, a second resist layer 218 is deposited over the wafer 200 (e.g., by spin coating). The resist 218 is present in the previously-formed openings 216. The second resist layer 218 then is exposed selectively by lithographic techniques (e.g., EBL) and developed so that particular regions of the wafer are no longer covered by the second resist layer 218 (see FIG. 4E). A second lithographic mask can be used during the foregoing exposure. In the illustrated example, following exposure and development of the second resist layer 218, the resist only partially fills the previously-formed openings 216 and only partially covers the upper surface of the substrate 200. Next, the wafer 200 is etched in the regions not covered by the resist 218 (see FIG. 4E). The remaining resist layer 218 then can be removed. The resulting second level pattern 219 is shown in FIG. 4F.

(28) Next, as shown in FIG. 4G, in preparation for a third etch into the wafer, a third resist layer 220 is deposited over the wafer 200 (e.g., by spin coating). The resist 220 is present in the previously-formed openings 216. The second resist layer 218 then is exposed selectively by lithographic techniques (e.g., EBL) and developed so that particular regions of the wafer are no longer covered by the third resist layer 220 (see FIG. 4H). A third lithographic mask can be used during the foregoing exposure. In the illustrated example, following exposure and development of the third resist layer 220, the resist only selectively fills the openings previously etched into the wafer during the first and second etch steps and only partially covers the upper surface of the substrate 200. Next, the wafer 200 is etched in the regions not covered by the resist 220 (see FIG. 4H). The remaining resist layer 220 then can be removed. The resulting third level pattern 221 is shown in FIG. 4I.

(29) The combination of the various lithographic and etch processes results in regions at multiple different depths (see FIG. 4I), which correspond to the different levels needed for the master tool. Details of the various masks used for the lithography and etch steps can be specified based on the modified pixel layout design. In this manner, a multi-level master tool can be fabricated. Although FIGS. 4A-4I illustrate an example of a process of fabricating an eight-level master tool based on a modified pixel layout design, similar processes can be used to fabricate master tools having fewer of more than eight levels based on a modified pixel layout design. Some or all of the operations illustrated in FIGS. 4A-4I may be part of an automated process. In some implementations, other techniques can be used to fabricate the master tool.

(30) Using a modified pixel layout design as described in connection with the foregoing examples can result in one or more advantages in some cases. For example, as the number of nodes associated with each cluster of pixels decreases, the amount of memory needed to store the information becomes smaller, which can make production easier (e.g., less computing required for EBL proximity correction; increased e-beam writing speed).

(31) Further, in some cases, optical performance of DOEs that are manufactured from a master tool obtained using a pixel layout design can be improved. If the pixel size is small, it is, in general, possible to make a higher performing design compared to a situation in which the pixel size is larger. However, such small pixel sizes can result in line edge roughness in the resulting DOEs (see FIG. 5B). The line edge roughness in the DOE structures tends to increase optical scattering, which can decrease optical performance. On the other hand, in some implementations, DOEs manufactured based on a master tool obtained using a modified pixel layout design as described above can have less line edge roughness (see FIG. 5C), and thus better optical performance.

(32) A further advantage that can be obtained in some cases is the avoidance of the formation of pointy tips 601 at the pixel corners in the master tool that sometimes occur in prior techniques (see FIG. 6A). Such pointy tips 601 need to be removed; otherwise they will be present in the replication tools and/or DOEs made from the master tool. Using the modified pixel layout designaccording to which the overall contour of a particular cluster of original regular polygonal pixels can be approximated by a single polygon that reduces the total number of edges and shortens the total length of the edges relative to the contour of the cluster of pixels in the original layout designcan help avoid occurrence of such pointy tips (see FIG. 6B).

(33) After the master tool is fabricated based on the modified pixel layout design, the master tool can be used to manufacture one or more (negative) sub-masters or replicas, which in turn can be used directly or indirectly to replicate DOEs, for example, as part of a mass production manufacturing process. Manufacturing the DOEs may take place in some instances at a wafer-level in which tens, hundreds, or even thousands of DOEs are replicated in parallel using the same sub-master or other tool derived from the master.

(34) In some instances, a structured element of the master (or a sub-master) is replicated into liquid or plastically deformable material, then hardened to make it dimensionally stable, and the structured element (e.g., the DOE) is removed. These replicating, hardening and removing steps are repeated over different parts of a substrate to form replicas of the same structured element.

(35) In general, each diffractive optical element can include a multi-level structured surface, at least a portion of which has a contour having straight lines, each of which has a length larger than a pixel size in the optical element, wherein the pixel size is a center-to-center distance between two adjacent pixels having a common center. In some instances, the straight lines change direction at least once at an angle other than 90 or 180. For example, in some instances, the straight lines change direction at least once at an angle , where 2<<88 or 92<<178. Further, in some instances, the straight lines change direction at least once at an angle , where 5<<85 or 95<<175.

(36) Examples of diffractive optical elements that can be manufactured using the master tool include diffraction and other gratings, beam splitters, beam shapers, collimators, diffractive diffusers, as well as other optical elements.

(37) Various aspects of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Thus, aspects of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware.

(38) A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

(39) The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

(40) Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

(41) While this specification contains many specifics, these should not be construed as limitations on the scope of the invention or of what may be claimed, but rather as descriptions of features specific to particular embodiments of the invention. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

(42) Various modifications may be made within the spirit of this disclosure. Accordingly, other implementations are within the scope of the claims.