METAL NANOSHEET, METHOD FOR MANUFACTURING SAME, AND ALL-METAL THREE-TERMINAL ELECTRICAL SWITCHING DEVICE HAVING NOVEL STRUCTURE INCLUDING SAME

Abstract

An embodiment relates to a method for manufacturing a metal nanosheet, including: providing a template having a two-dimensional layered structure with a limited interlayer height; and electroplating metal in an interlayer space of the template, wherein nucleation occurs in the interlayer space of the template, and the interlayer height is fixed.

Claims

1. A method for manufacturing a metal nanosheet having in-plane electrical anisotropy, comprising: providing a template having a two-dimensional layered structure with a interlayer height; and electroplating metal in an interlayer space of the template, wherein nucleation occurs in the interlayer space of the template, and the interlayer height is fixed.

2. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 1, wherein the providing the template comprises: forming a pair of glass layers on upper and lower surfaces of the template; and sealing three of side surfaces of the template with epoxy resin.

3. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 1, wherein the providing the template comprises: attaching a negative electrode to one end of the template; and connecting a wire to the negative electrode.

4. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 3, wherein in the electroplating the metal, the nucleation occurs on a surface of the negative electrode, and ion diffusion proceeds through the interlayer space of the template, resulting in unidirectional crystal growth.

5. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 1, wherein a grain boundary of the metal plated through the electroplating of the metal is aligned parallel to upper and lower surfaces of the template.

6. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 1, wherein the interlayer height of the template is greater than an ion size of the metal to be plated, but smaller than an ion size of the metal in a hydrated state.

7. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 1, wherein the interlayer height of the template is in a range of 2.5 to 7.5 .

8. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 1, wherein the template is an insulator having a two-dimensional van der Waals gap, and is composed of at least one selected from a group consisting of graphene oxide (GO), vermiculite, and boron nitride (hBN).

9. The method for manufacturing the metal nanosheet having the in-plane electrical anisotropy of claim 1, wherein the metal comprises at least one selected from a group consisting of Mg, Al, Cr, Mn, Fe, Co, Ni, Cu, Zn, Rb, Sr, Ag, Cd, Cs, Ba, La, and Pb.

10. A metal nanosheet formed by the method of claim 1, wherein the metal nanosheet has the in-plane electrical anisotropy.

11. The metal nanosheet of claim 10, wherein the metal comprises at least one selected from a group consisting of Mg, Al, Cr, Mn, Fe, Co, Ni, Cu, Zn, Rb, Sr, Ag, Cd, Cs, Ba, La, and Pb.

12. An all-metal three-terminal electrical switching device, comprising: a metal nanosheet having in-plane electrical anisotropy; and a plurality of electrodes connected to the metal nanosheet, wherein the plurality of electrodes comprises a source electrode, a first drain electrode (), and a second drain electrode ().

13. The all-metal three-terminal electrical switching device of claim 12, wherein the metal nanosheet has higher electrical conductivity in a direction parallel to a grain alignment axis than in a direction perpendicular to the grain alignment axis.

14. The all-metal three-terminal electrical switching device of claim 12, wherein the first drain electrode () is connected in a direction parallel to a grain alignment axis of the metal nanosheet, and the second drain electrode () is connected in a direction perpendicular to the grain alignment axis of the metal nanosheet.

15. The all-metal three-terminal electrical switching device of claim 12, wherein an on/off ratio of the all-metal three-terminal electrical switching device is determined by formula 1: $\begin{array}{cc}1+\frac{\mathrm{Rxx}Vd}{\mathrm{Ryy}V||d}.& \left[\mathrm{Equation}1\right]\end{array}$

16. The all-metal three-terminal electrical switching device of claim 12, wherein an on/off ratio of the all-metal three-terminal electrical switching device is 10.sup.7 or more.

17. The all-metal three-terminal electrical switching device of claim 12, wherein a magnitude of a current (I.sub.s) flowing through the all-metal three-terminal electrical switching device changes according to a voltage applied to the first drain electrode () and the second drain electrode (), and wherein if the magnitude of the current (I.sub.s) is less than a predetermined threshold, it is defined as an off state, and if the magnitude of the current exceeds the predetermined threshold, it is defined as an on state.

18. The all-metal three-terminal electrical switching device of claim 16, wherein a predetermined threshold is set within a range of 10.sup.9 A to 10.sup.6 A.

19. The all-metal three-terminal electrical switching device of claim 17, wherein in the all-metal three-terminal electrical switching device, by setting application conditions of a first drain voltage (V.sub.d.sup.) and a second drain voltage (V.sub.d.sup.), one of a plurality of logical operations selected from a group consisting of AND, OR, NAND, NOR, XOR, and XNOR is implementable.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0038] FIG. 1 is a schematic view illustrating a manufacturing process of a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure, compared to a conventional method;

[0039] FIG. 2 is a schematic view illustrating the manufacturing principle of a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure, compared to a conventional method;

[0040] FIG. 3 is a schematic view illustrating the overall structure of a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure;

[0041] FIG. 4 is an actual photograph of a template applied in a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure;

[0042] FIG. 5 is a graph illustrating the ion sizes of different metal types, the ion sizes of the metals in their hydrated state, and the interlayer spacing of graphene oxide (GO);

[0043] FIG. 6 shows images of a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure and a typical metal nanosheet, each with electrodes attached in 12 directions;

[0044] FIG. 7 shows data obtained by measuring the electrical conductivity of a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure in FIG. 6 and a typical metal nanosheet in each direction;

[0045] FIG. 8 shows STEM images of the y-z plane (Zones 1 to 3) and x-z plane (Zones 4 to 6) at various magnifications of a cross-section of a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure;

[0046] FIG. 9 shows (a) an image and (b) a schematic view of an all-metal three-terminal electrical switching device according to an embodiment of the disclosure;

[0047] FIGS. 10A and 10B show experimental data analyzing the characteristics of an all-metal three-terminal electrical switching device according to an embodiment of the disclosure;

[0048] FIG. 11 is a graph showing that the mathematical prediction of the device's on/off ratio according to the applied voltage matches experimental data, and that the on/off ratio can be increased by up to 10.sup.7 times or more depending on the driving voltage;

[0049] FIG. 12 is a graph showing the current (I.sub.s) value according to the first drain voltage (V.sub.d.sup.) and second drain voltage (V.sub.d.sup.); and

[0050] FIGS. 13A to 13F include a graph illustrating the relationship between the input voltage (V.sub.d.sup., V.sub.d.sup.) and the output current (I.sub.s) for each of the six rectangular areas indicated in FIG. 12, and examples of implementing each logical operation based on this relationship, wherein

[0051] FIG. 13A shows the AND logic circuit and its output characteristics, FIG. 13B shows the input signal variation over time for an AND logic circuit and the resulting output waveform,

[0052] FIG. 13C shows the OR logic circuit and its output characteristics, FIG. 13D shows the input signal variation over time for an OR logic circuit and the resulting output waveform,

[0053] FIG. 13E shows the NAND logic circuit and its output characteristics, FIG. 13F shows the input signal variation over time for a NAND logic circuit and the resulting output waveform,

[0054] FIG. 13G shows the NOR logic circuit and its output characteristics, FIG. 13H shows the input signal variation over time for a NOR logic circuit and the resulting output waveform,

[0055] FIG. 13I shows the XNOR logic circuit and its output characteristics, FIG. 13J shows the input signal variation over time for an XNOR logic circuit and the resulting output waveform,

[0056] FIG. 13K shows the XOR logic circuit and its output characteristics, and FIG. 13L shows the input signal variation over time for an XOR logic circuit and the resulting output waveform.

DETAILED DESCRIPTION

[0057] Hereinafter, the disclosure will be described with reference to the accompanying drawings. However, the disclosure may be implemented in various different forms and therefore is not limited to the embodiments described herein, but should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the disclosure.

[0058] In addition, in order to clearly describe the disclosure in the drawings, parts that are not related to the description are omitted, and similar parts are given similar drawing reference numerals throughout the specification.

[0059] In the entire specification, when a part is said to be connected (linked, contacted, coupled) to another part, this includes not only the case where it is directly connected but also the case where it is indirectly connected with another member in between.

[0060] In addition, when a part such as a layer, film, region, or plate is said to be on another part, this includes not only the case where it is directly on another part, but also the case where there is another part in between. In addition, in this specification, when a part such as a layer, film, region, or plate is formed on another part, the direction in which it is formed is not limited to the upper direction, and includes being formed in the side or lower direction. On the other hand, when a part such as a layer, film, region, or plate is said to be under another part, this includes not only the case where it is directly under another part, but also the case where there is another part in between.

[0061] In this specification, the terms upper surface and lower surface are used as relative concepts in order to easily explain the technical idea of the disclosure. Therefore, the terms upper surface and lower surface do not refer to a specific direction, position, or component, and are interchangeable with each other.

[0062] For example, the upper surface may be interpreted as the lower surface, and the lower surface may be interpreted as the upper surface. Therefore, the upper surface may be expressed as first and the lower surface may be expressed as second, or the lower surface may be expressed as first and the upper surface may be expressed as second. However, within one embodiment, the terms upper surface and lower surface are not used interchangeably.

[0063] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the disclosure belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant technology, and shall not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0064] In addition, when a part is said to include a certain component, this does not exclude other components unless specifically stated to the contrary, but rather means that other components may be additionally provided.

[0065] The terms used in this specification are used only to describe specific embodiments and are not intended to limit the disclosure. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, the terms include or have are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood as not excluding in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0066] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0067] First, a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure will be described.

[0068] The electrical properties of a material generally depend on its unique crystal structure. For example, copper, which has an isotropic cubic structure, exhibits high electrical conductivity regardless of orientation, while graphene, which has a two-dimensional layered structure, exhibits significant differences in electrical conductivity in directions parallel and perpendicular to the layered structure. This difference in electrical conductivity along different directions is called electrical anisotropy, and is considered a unique characteristic of each material.

[0069] The disclosure provides a method for synthesizing metal nanosheets with in-plane electrical anisotropy through specific grain alignment.

[0070] In the disclosure, a template with a layered structure is used to grow a metal in a two-dimensional manner and metal nanosheets grown in the interlayer space of the layered template have grain boundaries uniformly aligned along the metal growth direction.

[0071] This enables the implementation of high (>103) electrical anisotropy even in metallic materials with a high-symmetry cubic crystal structure.

[0072] The disclosure may provide a metallic electrical switching device based on metal nanosheets that exhibit in-plane electrical anisotropy at a level not seen in conventional monoatomic metals.

[0073] As an example of the embodiment, there may be a method for manufacturing metal nanosheets with in-plane electrical anisotropy, including: providing a template having a two-dimensional layered structure with a limited interlayer height; and a step of electroplating metal in the interlayer space of the template, [0074] wherein nucleation occurs in the interlayer space of the template and the interlayer height is fixed.

[0075] Through the above embodiment, since high electrical anisotropy can be achieved even with metal materials having a high-symmetry cubic crystal structure, the two-dimensional metal nanosheets synthesized using this method exhibit high anisotropy and overcome the limitations of thickness-dependent two-dimensional materials.

[0076] At this time, despite their cubic crystal structure, the metal nanosheets exhibit high electrical anisotropy, expressed as G.sub.max/G.sub.min (=G.sub.yy/G.sub.xx), with a maximum electrical anisotropy of 3700 or higher.

[0077] As described above, the two-dimensional metal nanosheets synthesized using the nanosheet manufacturing method according to the embodiments of the disclosure can achieve high electrical anisotropy through microstructural control and grain orientation engineering.

[0078] This allows for high electrical anisotropy, exceeding the level of anisotropy limited by the intrinsic properties of existing materials, compared to low-symmetry crystal structures (Tetragonal, Monoclinic, Orthorhombic, Triclinic, Hexagonal, Trigonal) typically utilized to achieve electrical anisotropy, or ternary or higher compounds, where atomic structure anisotropy increases with increasing element count; [0079] furthermore, this structure offers the potential for expansion to other materials. In addition, these metal nanosheets not only exhibit high electrical anisotropy but also exhibit electrical anisotropy in the in-plane direction, offering the potential for application as orthogonal elements in switching devices.

[0080] This will be described in more detail below with reference to FIGS. 1 and 2.

[0081] FIG. 1 is a schematic view illustrating a manufacturing process of a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure, compared to a conventional method.

[0082] FIG. 2 is a schematic view illustrating the manufacturing principle of a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure, compared to a conventional method.

[0083] Referring to FIGS. 1 and 2, [0084] a comparison can be made between a metal structure fabricated on a conventional flat surface and a metal structure fabricated using a two-dimensional template used in the disclosure.

[0085] It can be confirmed that the metal nanosheets obtained by electroplating on a conventional flat surface exhibit an isotropic crystal structure with random nucleation of ions on the substrate and randomly oriented grain boundaries.

[0086] In contrast, [0087] as in the above embodiment, the metal nanosheets fabricated by electroplating within a two-dimensional template with a limited interlayer spacing (height) exhibit aligned grain boundaries.

[0088] Furthermore, in electroplating using a two-dimensional template, nucleation occurs only on the negative electrode surface at the template tip, causing nuclei to grow in one direction, and this difference may lead to the formation of an anisotropic microstructure with parallel, aligned grain boundaries within the sheet.

[0089] FIG. 3 is a schematic view illustrating the overall structure of a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure.

[0090] FIG. 4 is an actual photograph of a template applied in a method for manufacturing a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure.

[0091] Referring to FIGS. 3 and 4, as an example of the above embodiment, the providing of the template may include, to fix the interlayer height, [0092] forming a pair of glass layers on the upper and lower surfaces of the template; and sealing three of the side surfaces of the template with epoxy resin.

[0093] Here, the providing of the template may include: [0094] attaching a negative electrode to one end of the template; and connecting a wire to the negative electrode.

[0095] When the template is provided as shown in FIG. 4 and electroplating is performed as shown in FIG. 3, nucleation occurs on the surface of the negative electrode, and ion diffusion proceeds through the interlayer space of the template, allowing unidirectional crystal growth to occur.

[0096] Furthermore, referring to FIG. 2, it can be confirmed that the grain boundaries of the metal plated through the step of electroplating are aligned parallel to the upper and lower surfaces of the template.

[0097] Through this process, after complete growth, the grain boundaries within the sheet are uniformly aligned, forming an anisotropic microstructure.

[0098] As an example of the above embodiment, there may be a method for manufacturing a metal nanosheet having in-plane electrical anisotropy, wherein the interlayer height of the template is greater than the ion size of the metal to be plated, but less than the ion size of the metal in its hydrated state.

[0099] As in the above embodiment, when the channel size (layer height, interlayer spacing) is smaller than the critical nucleation size (the size of ions in the hydrated metal), local nucleation and limited particle growth are possible.

[0100] FIG. 5 is a graph illustrating the ion sizes of different metal types, the ion sizes of the metals in their hydrated state, and the interlayer spacing of graphene oxide (GO).

[0101] Referring to FIG. 5, the interlayer heights of the templates implementable depending on the type of metal can be confirmed.

[0102] Referring to FIG. 5, there may be a method for manufacturing metal nanosheets with in-plane electrical anisotropy, wherein the interlayer height of the template usable in the above embodiment is 2.5 to 7.5 .

[0103] More preferably, the interlayer height may be 4 to 7.5 .

[0104] Most preferably, the interlayer height may be 4 to 6 .

[0105] Referring to FIG. 5, it can be confirmed that the above-described effects can be achieved for the widest variety of metals when the layer height of the template is 4 to 6 .

[0106] As an example of the above embodiment, there may be a method for manufacturing metal nanosheets with in-plane electrical anisotropy, wherein the template includes an insulator having a two-dimensional van der Waals gap, and is composed of at least one insulator selected from the group consisting of two-dimensional atomic structures, such as graphene oxide (GO), vermiculite, and hBN.

[0107] At this time, only when an insulator is used as the template can ions be reduced only on the negative electrode surface.

[0108] If a conductor, rather than an insulator, is used as the template, the template surface may supply electrons to the ions, potentially leading to metal reduction at undesirable locations.

[0109] Furthermore, as described above, the template must be an insulator with a two-dimensional van der Waals gap and a two-dimensional atomic structure.

[0110] While three-dimensional insulators, such as silicon oxide, cannot have a uniform interlayer height that allows metal ion movement, [0111] an insulator with a two-dimensional atomic structure possesses a uniform interlayer height (van der Waals gap) that allows metal ion movement, making it an essential element for the growth of aligned metal nanosheets.

[0112] Furthermore, as an example of the above embodiment, a method for manufacturing a metal nanosheet with in-plane electrical anisotropy may be provided, characterized in that the metal includes at least one selected from the group consisting of Mg, Al, Cr, Mn, Fe, Co, Ni, Cu, Zn, Rb, Sr, Ag, Cd, Cs, Ba, La, and Pb, as shown in FIG. 5.

[0113] A metal nanosheet according to another embodiment of the disclosure will be described.

[0114] As an example of the above embodiment, there may be a metal nanosheet formed using the aforementioned method for manufacturing a metal nanosheet, and having in-plane electrical anisotropy.

[0115] Furthermore, the metal nanosheet may be characterized by being composed of one or more metals selected from the group consisting of Mg, Al, Cr, Mn, Fe, Co, Ni, Cu, Zn, Rb, Sr, Ag, Cd, Cs, Ba, La, and Pb.

[0116] Since the metal nanosheet is a different category of invention with substantially the same technical structure as the metal nanosheet manufacturing method, [0117] it is noted that the aforementioned descriptions of the metal nanosheet manufacturing method are applicable as is.

[0118] An all-metal three-terminal electrical switching device according to another embodiment of the disclosure will be described.

[0119] FIG. 9 shows an image and a schematic view of an all-metal three-terminal electrical switching device according to an embodiment of the disclosure.

[0120] Referring to FIG. 9, as an example of the embodiment, there may be an all-metal three-terminal electrical switching device, including: a metal nanosheet having in-plane electrical anisotropy; and a plurality of electrodes connected to the metal nanosheet, [0121] wherein the plurality of electrodes include: a source electrode; a first drain electrode (); and a second drain electrode ().

[0122] As an example of the embodiment, the first drain electrode () may be connected in a direction parallel to the grain alignment axis of the metal nanosheet, and the second drain electrode () may be connected in a direction perpendicular to the grain alignment axis of the metal nanosheet.

[0123] At this time, the source electrode may face the second drain electrode () and be connected in a direction perpendicular to the grain alignment axis of the metal nanosheet.

[0124] The all-metal switching device according to the above embodiment utilizes a metal nanosheet having in-plane electrical anisotropy, and [0125] the metal nanosheet may be characterized by a high electrical anisotropy (G.sub.max/G.sub.min) of up to 3700 or greater, despite having a cubic crystal structure.

[0126] That is, the metal nanosheet having in-plane electrical anisotropy may be characterized by high conductivity in a direction parallel to the grain alignment axis and low conductivity in a direction perpendicular to the grain alignment axis.

[0127] Regarding this, the on/off ratio of the switching device may be determined by formula 1.

[00002]$\begin{array}{cc}1+\frac{\mathrm{Rxx}Vd}{\mathrm{Ryy}V||d}& \left[\mathrm{Equation}1\right]\end{array}$

[0128] In the switching device described above, the on/off ratio is a key indicator of device performance, and it is defined as the ratio of the current flowing in the ON state (I.sub.on) to the current flowing in the OFF state (I.sub.off).

[0129] A higher ON/OFF ratio clearly differentiates the current between the ON and OFF states, enabling stable distinction between logic signals 1 and 0 in digital circuits and maintaining a high signal-to-noise ratio (SNR).

[0130] In addition, when the on/off ratio is large, the leakage current in the off state is reduced, which can reduce power consumption and heat generation, thereby improving the operating speed and integration level of the device.

[0131] The switching device according to the above embodiment may be characterized by an on/off ratio of 10.sup.7 or greater according to formula 1.

[0132] Therefore, when external power is applied in a direction parallel to the grain boundary alignment axis, current flow increases by 10.sup.7 times or more compared to when external power is applied, enabling the on/off state to be distinguished, similar to a semiconductor transistor.

[0133] In the switching device according to the above embodiment, the on/off ratio (change in current flow due to external power application) is affected by 1) the resistance difference (electrical conductivity difference) between the vertical and parallel directions, as well as 2) the applied voltage.

[0134] This can be explained using formula 1 and FIG. 11.

[0135] Formula 1 above is a formula indicating that the on/off ratio of the device is determined by the resistance difference (R.sub.xx/R.sub.yy) between the vertical and parallel directions and the applied voltage (V.sub.d.sup./V.sub.d.sup.).

[0136] FIG. 11 is a graph showing that the mathematical prediction of the device's on/off ratio according to the applied voltage matches experimental data, and that the on/off ratio can be increased by up to 10.sup.7 times or more depending on the driving voltage.

[0137] More specifically, for a device with a resistance difference of 200 times or more between directions parallel and perpendicular to the grain alignment axis, [0138] when the driving voltage was varied from 10.sup.7 V to 1 V for the first drain voltage (V.sub.d.sup.) and [0139] from 10.sup.5 V to 1 V for the second drain voltage (V.sub.d.sup.), [0140] the device's on/off ratio was mathematically calculated using formula 1, and it was confirmed that it increased by up to 10.sup.7 times under the conditions of V.sub.d.sup.=1 V, V.sub.d.sup.=10.sup.5 V.

[0141] Additionally, referring to FIG. 11, for the corresponding device, [0142] for the first drain voltage (V.sub.d.sup.), one of three driving voltages (10.sup.3 V, 10.sup.2 V, 10.sup.1 V) was selected, [0143] for the second drain voltage (V.sub.d.sup.), one of three driving voltages (10.sup.3 V, 10.sup.2 V, 10.sup.1 V) was selected, and [0144] the on/off ratio was experimentally measured for a total of nine driving voltage combinations corresponding to the rectangular areas in the graph, and compared with mathematical calculations.

[0145] As a result, the experimental measurements showed an on/off ratio of up to 10.sup.4 times greater under conditions of V.sub.d.sup.=10.sup.1 V, V.sub.d.sup.=10.sup.3 V, and as shown in the inset graph, the agreement between the experimental measurements and mathematical calculations confirms the validity of the theoretical calculations.

[0146] Furthermore, as an example of the above embodiment, the switching device may be characterized in that the magnitude of the current (I.sub.s) flowing through the device varies depending on the voltage applied to the first drain electrode () and the second drain electrode (), and that if the magnitude of the current (I.sub.s) is below a threshold current, the device is in an off state, and if it exceeds the threshold current, the device is in an on state.

[0147] At this time, the threshold current may be set within a range of 10.sup.9 A to 10.sup.6 A.

[0148] If the threshold is set too low, below 10.sup.9 A, external noise or leakage current can easily exceed the threshold, potentially resulting in false switching.

[0149] Conversely, if the threshold is set too high, exceeding 10.sup.6 A, excessive current is required to drive the device itself, increasing power consumption and degrading the stability of logic operations.

[0150] As described above, the switching device may be characterized by being capable of implementing any one of the logical operations, AND, OR, NAND, NOR, XOR, and XNOR, depending on the application conditions of the first drain voltage (V.sub.d.sup.) and the second drain voltage (V.sub.d.sup.).

[0151] That is, a device according to an example embodiment of the disclosure uses the first drain voltage (V.sub.d.sup.) and the second drain voltage (V.sub.d.sup.) as input signals (two-input), and compares the output current (I.sub.s) with a threshold current to determine whether it is 0 or 1, and this allows a single device to reliably implement six logic gates (AND, OR, NAND, NOR, XOR, XNOR).

[0152] At this time, depending on the input values of the first drain voltage (V.sub.d.sup.) and the second drain voltage (V.sub.d.sup.), the output current (I.sub.s) is classified as being above or below the threshold value, thereby consistently corresponding to the truth table of the logic operation, and thus it is sufficient to reliably implement logic operations such as AND, OR, NAND, NOR, XOR, and XNOR; however, this requirement is not limited to the specific voltage values exemplified in the embodiments.

[0153] Specific embodiments are described in detail in experimental example 3 below.

[0154] Furthermore, unlike conventional semiconductor transistors, which incorporate a dielectric layer and utilize the charge/discharge effect of an electric field to induce electrons in the channel and change the current flow, [0155] the all-metal three-terminal electrical switching device does not include a dielectric layer and therefore operates without charging/discharging, and utilizes an anisotropic conduction path as the channel, changing the current flow depending on channel activation.

[0156] This allows for low-voltage operation without a theoretical operating voltage, and furthermore, switching speeds can be increased by eliminating the RC delay caused by resistance and capacitance in the device operation mechanism.

[0157] By utilizing a metal nanosheet with aligned crystal grains, with an increased on/off ratio due to electrical anisotropy, electrical anisotropy can be maximized, and an on/off ratio of up to 10.sup.7 times or more can be achieved.

[0158] These switching characteristics offer the advantage of enabling logical operations in a single device.

[0159] Manufacturing example 1. Manufacturing of metal (Ni) nanosheets with in-plane electrical anisotropy. [0160] Manufacturing example 1 will be described with reference to FIGS. 3 and 4. [0161] Graphene oxide was prepared by dropping a highly concentrated graphene oxide solution (5 g/L; Graphene Supermarket) onto a glass slide until the film height reached 20 m. The solution was then dried at room temperature for 24 hours. [0162] Silver paste electrodes and copper wires were attached to the ends of the graphene oxide. [0163] The graphene oxide was placed between two glass slides, and the gap between the two slides, including the three corners, was covered with commercial epoxy (S-208, DEVCON). [0164] The epoxy was then dried at room temperature for 24 hours. [0165] A nickel plate was used as the negative electrode, and the prepared graphene oxide template served as the positive electrode. [0166] The electrolyte was prepared using deionized water (DI) containing 80 g/L of NiSO.sub.4.Math.6H.sub.2O, 40 g/L of NiCl.sub.2.Math.6H.sub.2O, and 30 g/L of H.sub.3BO.sub.3. [0167] A constant current of 0.01 A was supplied for 24 hours via a power supply device.

Experimental Example 1. Analysis of Electrical Conductivity Characteristics According to The Direction and Thickness of Metal Nanosheet According to an Embodiment of the Disclosure

[0168] FIG. 6 shows images of a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure and a typical metal nanosheet, each with electrodes attached in 12 directions.

[0169] FIG. 7 shows data obtained by measuring the electrical conductivity of a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure in FIG. 6 and a typical metal nanosheet in each direction.

[0170] In experimental example 1, the graphene oxide template filled with metal nanosheets was mechanically exfoliated from a silicon oxide substrate using Scotch tape, and the graphene oxide containing the metal nanosheets was heated to 350 C.

[0171] This process removed the graphene oxide, leaving only the anisotropic metal nanosheets on the silicon oxide substrate.

[0172] Thereafter, as shown in FIG. 6, 12-directional electrodes were fabricated on the metal nanosheets, conductivity was measured along these directions, and the anisotropic conductivity differences across the metal nanosheets were identified.

[0173] Additionally, the isotropic conductivity of metal nanosheets fabricated using a conventional deposition method (sputtering) was confirmed, allowing comparison with the anisotropy of the metal nanosheets of the disclosure.

[0174] At this time, the regions indicated in FIGS. 6 and 7 represent the directions of maximum nanosheet conductivity, respectively.

[0175] As shown in FIG. 6, 12 electrodes were fabricated around a Ni nanosheet at 30 intervals, and the electrical conductivity was measured.

[0176] As a result, as shown in FIG. 7, the electrical conductivity decreased to 1,265 S at =0, 968 S at /6, 955 S at /3, and 25 S at /2, before increasing again at =.

[0177] This demonstrates the varying conductivity of a single nanosheet depending on the grain boundary orientation, demonstrating a nearly 50-fold difference in electrical conductivity between conduction parallel to the grain boundary (=0) and conduction perpendicular to the grain boundary (=/2).

[0178] Furthermore, FIG. 7 demonstrates the thickness dependence of the angle-resolved conductivity of conventional sputter deposition and template-mediated nanosheets, and [0179] electrical anisotropy (G.sub.max/G.sub.min) and trends of sputtered (circular) and templated (square) nanosheets according to sample thickness can be observed.

[0180] At this time, while conventional techniques (sputtered Ni) maintain isotropy regardless of thickness, [0181] the template-grown metal (Ni) nanosheets according to the disclosure exhibit anisotropy from the outset, regardless of thickness, and the anisotropy gradually increases as the thickness decreases.

[0182] Thus, the metal (Ni) nanosheets according to the disclosure enables to confirm that the in-plane electrical anisotropy of the metal nanosheets can be controlled by adjusting the thickness.

[0183] More specifically, when the metal nanosheets have a thickness of 10 nm to 60 nm, the metal nanosheets are characterized by an anisotropy value of 10 or greater, as determined by formula 2.

[00003]$\begin{array}{cc}\mathrm{Anisotropy}\mathrm{value}=G_{\max }/G_{\min }\left(=G_{\mathrm{yy}}/G_{xx}\right)& \left[\mathrm{Formula}2\right]\end{array}$

[0184] In formula 2, G.sub.max represents the highest electrical conductivity measured on the corresponding surface, and G.sub.min represents the lowest electrical conductivity measured on the corresponding surface.

[0185] Furthermore, when the metal nanosheet has a thickness of 10 nm to 30 nm, the metal nanosheet may be characterized by an anisotropy value of 100 or greater according to formula 2.

[0186] When the metal nanosheet has a thickness of 10 nm to 20 nm, the metal nanosheet may be characterized by an anisotropy value of 1000 or greater according to formula 2.

[0187] Through experimental example 1, the electrical conductivity was measured along different directions, and cross-sections in directions with high electrical conductivity and those with low conductivity were examined, confirming that the cross-sections had grain boundary differences.

Experimental Example 2. Analysis of the Cross-Sectional Structure of a Metal Nanosheet According to an Embodiment of the Disclosure

[0188] FIG. 8 shows STEM images of the y-z plane (Zones 1 to 3) and x-z plane (Zones 4 to 6) at various magnifications of a cross-section of a metal nanosheet with in-plane electrical anisotropy according to an embodiment of the disclosure.

[0189] FIG. 8 shows the microstructural differences between the two samples through TEM analysis (BF-STEM and high-resolution TEM).

[0190] Referring to the STEM images in the y-z plane (Zones 1 to 3), the samples exhibit the geometry and symmetry of the [0 1 1] plane of FCC Ni, with a consistent periodic structure and fewer grain boundaries.

[0191] This indicates non-uniform nucleation and growth primarily along the y-direction at the positive electrode surface.

[0192] Conversely, the STEM images in the x-z plane (Zones 4 to 6) reveal a random grain distribution with diverse orientations.

[0193] This suggests a correlation between grain orientation and conductivity anisotropy.

Experimental Example 3. Analysis of Switch Characteristics of an all-Metal Three-Terminal Electrical Switching Device According to an Embodiment of the Disclosure

[0194] FIG. 9 shows an image and a schematic view of an all-metal three-terminal electrical switching device according to an embodiment of the disclosure.

[0195] Referring to FIG. 9, the structure of an all-metal three-terminal electrical switching device according to an embodiment of the disclosure can be confirmed, and [0196] the all-metal three-terminal electrical switching device is an all-metal device that uses an external voltage to adjust the current.

[0197] At this time, the on-off ratio of the all-metal three-terminal electrical switching device is as shown in formula 1.

[00004]$\begin{array}{cc}1+\frac{\mathrm{Rxx}Vd}{\mathrm{Ryy}V||d}& \left[\mathrm{Equation}1\right]\end{array}$

[0198] In formula 1, R.sub.xx is the electrical resistance in the direction perpendicular to the grain boundary alignment direction (high resistance), and

[0199] R.sub.yy is the electrical resistance in the direction parallel to the grain boundary alignment direction (low resistance).

[0200] FIG. 10 shows experimental data analyzing the characteristics of an all-metal three-terminal electrical switching device according to an embodiment of the disclosure.

[0201] Referring to FIG. 10, the on/off state and subthreshold swing characteristics of the all-metal three-terminal electrical switching device can be confirmed.

[0202] FIG. 11 is a graph showing that the mathematical prediction of the device's on/off ratio according to the applied voltage matches experimental data, and that the on/off ratio can be increased by up to 10.sup.7 times or more depending on the driving voltage.

[0203] Referring to FIG. 11, it can be confirmed that the on-off ratio can be increased by up to 10.sup.7 times or more depending on the voltages (V.sub.d.sup., V.sub.d.sup.) applied to the two terminals of an all-metal three-terminal electrical switching device.

[0204] FIG. 12 is a graph showing the current (I.sub.s) values as a function of the first drain voltage (V.sub.d.sup.) and second drain voltage (V.sub.d.sup.).

[0205] Referring to FIG. 12, the areas marked by white rectangles in the graph indicate that controlling the two input voltages within those areas enables the implementation of the logical operations indicated by the rectangles.

[0206] FIG. 13 illustrates the relationship between the input voltages (V.sub.d.sup., V.sub.d.sup.) and the output current (I.sub.s) for each of the six rectangular areas shown in FIG. 12, as well as examples of implementing each logical operation based on these relationships.

[0207] More specifically, referring to FIG. 13, [0208] when for the first drain voltage (V.sub.d.sup.), two voltages are selected at 5 mV intervals within 5 mV, 0 mV, and 5 mV and defined as IN1=0 and IN1=1, respectively, for the second drain voltage (V.sub.d.sup.), two voltages are selected at 0.24 V intervals within 0.48 V, 0.36 V, 0.24 V, 0.12 V, 0 V, 0.12 V, and 0.24 V and defined as IN2=0 and N2=1, respectively, [0209] for the current (I.sub.s) flowing within the device, the case of |I.sub.s|<410.sup.8 A is defined as the off-current level (OUT=0, 0), and the case of |I.sub.s|>410.sup.8 A is defined as the on-current level (OUT=1, 1), [0210] a logical operation can be implemented through the relationship between the two input voltages and the output current.

1. AND Logic Gate Implementation (FIGS. 13a and b)

[0211] When V.sub.d.sup.=0 mV is defined as IN1=0, V.sub.d.sup.=5 mV as IN1=1, [0212] V.sub.d.sup.=0.12 V as IN2=0, and V.sub.d.sup.=0.12 V as IN2=1, [0213] it is possible to implement AND logic in which OUT=0 is output when [(IN1, IN2)=(0, 0), (0, 1), (1, 0)], and [0214] OUT=1 is output when [(IN1, IN2)=(1, 1)].

2. OR Logic Gate Implementation (FIGS. 13c and d)

[0215] When V.sub.d.sup.=0 mV is defined as IN1=0, V.sub.d.sup.=5 mV as IN1=1, [0216] V.sub.d.sup.=0 V as IN2=0, and V.sub.d.sup.=0.24 V as IN2=1, [0217] it is possible to implement OR logic in which OUT=0 is output when [(IN1, IN2)=(0, 0)], and [0218] OUT=1 is output when [(IN1, IN2)=(0, 1), (1, 0), (1, 1)].

3. NAND Logic Gate Implementation (FIGS. 13e and f)

[0219] When V.sub.d.sup.=0 m V is defined as IN1=0, V.sub.d.sup.=5 mV as IN1=1, [0220] V.sub.d.sup.=0.48 V as IN2=0, and V.sub.d.sup.=0.24 V as IN2=1, [0221] it is possible to implement NAND logic in which OUT=0 is output when [(IN1, IN2)=(1, 1)], and [0222] OUT=1 is output when [(IN1, IN2)=(0, 0), (0, 1), (1, 0)].

4. NOR Logic Gate Implementation (FIGS. 13g and h)

[0223] When V.sub.d.sup.=0 mV is defined as IN1=0, V.sub.d.sup.+=5 mV as IN1=1, [0224] V.sub.d.sup.=0.36 V as IN2=0, and V.sub.d.sup.=0.12 V as IN2=1, [0225] It is possible to implement NOR logic in which OUT=0 is output when [(IN1, IN2)=(0, 1), (1, 0), (1, 1)], and [0226] OUT=1 is output when [(IN1, IN2)=(0, 0)].

5. XNOR Logic Gate Implementation (FIGS. 13i and j)

[0227] When V.sub.d.sup.=0 mV is defined as IN1=0, V.sub.d.sup.=5 mV as IN1=1, [0228] V.sub.d.sup.=0.24 V as IN2=0, and V.sub.d.sup.=0 V as IN2=1, [0229] it is possible to implement XNOR logic in which OUT=0 is output when [(IN1, IN2)=(0, 1), (1, 0)], and [0230] OUT=1 is output when [(IN1, IN2)=(0, 0), (1, 1)].

6. XOR Logic Gate Implementation (FIGS. 13k and l)

[0231] When V.sub.d.sup.=0 mV is defined as IN1=0, V.sub.d.sup.=5 mV as IN1=1, [0232] V.sub.d.sup.=0 V as IN2=0, and V.sub.d.sup.=0.24 V as IN2=1, [0233] it is possible to implement XOR logic in which OUT=0 is output when [(IN1, IN2)=(0, 1), (1, 0)], and [0234] OUT=1 is output when [(IN1, IN2)=(0, 0), (1, 1)].

[0235] Likewise, it can be confirmed that an all-metal three-terminal electrical switching device that does not include a dielectric layer according to an embodiment of the disclosure can operate without using charging and discharging of a capacitor, and can operate as a low-voltage, high-speed device while achieving a high on-off ratio and implementing logical operations.

[0236] The description of the disclosure is for illustrative purposes, and those skilled in the art will understand that it can be easily modified into other specific forms without changing the technical idea or essential features of the disclosure. Therefore, the embodiments described above should be understood as being exemplary in all respects and not limiting. For example, each component described as a single type may be implemented in a distributed manner, and likewise, components described as distributed may be implemented in a combined form.

[0237] The scope of the disclosure is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the disclosure.