WIDE-RANGE SWITCHED-MODE POWER AMPLIFIER ARCHITECTURE

Abstract

According to one embodiment, a power amplifier includes a plurality of switches and an output tank network. One or more of the switches are configured to generate one or more first intermediate waveforms having one or more first fundamental frequency components, and one or more of the switches are configured to generate one or more second intermediate waveforms by chopping the one or more first intermediate waveforms with controllable timing. The second intermediate waveforms have one or more second fundamental frequency components that are controllably reduced from those of the one or more first intermediate waveforms. The output tank network is configured to filter the one or more second intermediate waveforms to provide an output waveform to a load, the output waveform having one or more third fundamental frequency components. In some cases, all switches achieve zero voltage switching under different power and load conditions with resistive and reactive loads.

Claims

1. A power amplifier comprising: a plurality of switches, wherein: one or more of the switches are configured to generate one or more first intermediate waveforms having one or more first fundamental frequency components, and one or more of the switches are configured to generate one or more second intermediate waveforms by chopping the one or more first intermediate waveforms with controllable timing, the second intermediate waveforms having one or more second fundamental frequency components that are controllably reduced from those of the one or more first intermediate waveforms; and an output tank network configured to filter the one or more second intermediate waveforms to provide an output waveform to a load, the output waveform having one or more third fundamental frequency components.

2. The power amplifier of claim 1 wherein the one or more switches are configured to chop the one or more first intermediate waveforms with controllable timing determined by an electrical angle.

3. The power amplifier of claim 1 wherein the one or more of the switches configured to generate the first intermediate waveforms are different from the one or more of the switches configured to generate one or more second intermediate waveforms.

4. The power amplifier of claim 1 wherein the one or more of the switches configured to generate the one or more first intermediate waveforms and the one or more of the switches configured to generate one or more second intermediate waveforms include one or more switches in common.

5. The power amplifier of claim 1 wherein the output tank network comprises a capacitor and inductor connected in series with the load.

6. The power amplifier of claim 1 wherein the plurality of switches comprises at least two switches.

7. The power amplifier of claim 6 wherein the at least two switches are connected in series between a voltage source and ground.

8. The power amplifier of claim 1 wherein the plurality of switches comprises at least six switches.

9. The power amplifier of claim 8 wherein a first three of the at least six switches are connected series between a voltage and ground and wherein at least a second three of the at least six switches are also connected series between a voltage and ground.

10. The power amplifier of claim 1 wherein the one or more first intermediate waveforms comprise one or more square waves.

11. The power amplifier of claim 1 wherein the one or more second intermediate waveforms comprise one or more square waves.

12. The power amplifier of claim 1 wherein the output waveform is a sinusoidal waveform.

13. The power amplifier of claim 1 comprising one or more inductive networks configured to provide zero-voltage switching (ZVS) for the plurality of switches.

14. The power amplifier of claim 13 wherein the one or more inductive networks include the output tank network.

15. The power amplifier of claim 13 wherein the one or more inductive networks include an inductor connected in parallel with the output tank network.

16. The power amplifier of claim 13 wherein the one or more inductive networks include at least two inductive networks.

17. The power amplifier of claim 1 wherein the one or more switches comprise at least four switches arranged as two inverter halves configured to be operated out of phase to provide a second intermediate waveforms taken differentially between the two inverter halves.

18. The power amplifier of claim 1 wherein the one or more second intermediate waveforms comprise at least two second intermediate waveforms combined such that a direct current (DC) component and even harmonics of the at least two second intermediate waveforms cancel and the fundamental components of the at least two second intermediate waveforms reinforce to drive the load.

19. A system comprising: a power amplifier having: a plurality of switches, wherein: one or more of the switches are configured to generate one or more first intermediate waveforms having one or more first fundamental frequency components, and one or more of the switches are configured to generate one or more second intermediate waveforms by chopping the one or more first intermediate waveforms with controllable timing, the second intermediate waveforms having one or more second fundamental frequency components that are controllably reduced from those of the one or more first intermediate waveforms; and an output tank network configured to filter one or more second intermediate waveforms to provide an output waveform to a load, the output waveform having one or more third fundamental frequency components; and a controller configured to control the plurality of switches.

20. The system of claim 19 wherein the controller is configured to use at least one of: frequency modulation is to adjust for variations in reactance of the load; frequency modulation to control power, voltage or current delivered to the load; or beta modulation to control power, voltage or current delivered to the load.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The manner of making and using the disclosed subject matter may be appreciated by reference to the detailed description in connection with the drawings, in which like reference numerals identify like elements.

[0020] FIG. 1 is a block diagram showing a wide-range switched-mode power amplifier system, according to some embodiments.

[0021] FIGS. 2A and 2B are schematic diagrams showing examples of a six-switch wide-range voltage-mode class-D power amplifier, according to some embodiments.

[0022] FIGS. 3A-C are graphs showing modulated dual polarity square-wave waveforms that can be generated within a six-switch wide-range voltage-mode class-D power amplifier, according to some embodiments.

[0023] FIG. 4 is a series of graphs showing control sequences that may be used with a wide-range voltage-mode class-D power amplifier, according to some embodiments.

[0024] FIGS. 5A-D are schematic diagrams showing circuit operation of a six-switch wide-range voltage-mode class-D power amplifier, according to some embodiments.

[0025] FIGS. 6A and 6B are schematic diagrams showing examples of a three-switch wide-range voltage-mode class-D power amplifier, according to some embodiments.

[0026] FIGS. 7A-C are graphs showing modulated single polarity square-wave waveforms that can be generated within a three-switch wide-range voltage-mode class-D power amplifier.

[0027] FIG. 8 is a schematic diagram showing a six-switch wide-range voltage-mode class-D power amplifier with switch capacitances, according to some embodiments.

[0028] FIGS. 9A-C are graphs showing modulated dual polarity square-wave waveforms that can be generated within a six-switch wide-range voltage-mode class-D power amplifier with switch capacitances, according to some embodiments.

[0029] FIG. 10 is a series of graphs showing control sequences that may be used with a wide-range voltage-mode class-D power amplifier with switch capacitances, according to some embodiments.

[0030] FIG. 10A is a series of graphs showing additional control sequences that may be used with a wide-range voltage-mode class-D power amplifier with switch capacitances, according to some embodiments.

[0031] FIGS. 11A-H are schematic diagrams showing circuit operation of a six-switch wide-range voltage-mode class-D power amplifier with switch capacitances, according to some embodiments.

[0032] FIGS. 12A and 12B are graphs showing dynamic frequency modulation that may be used with a wide-range switched-mode power amplifier, according to some embodiments.

[0033] FIG. 13 is a graph showing a relationship between power, , and resistive load.

[0034] FIGS. 14A and 14B are graphs showing further relationships between power, B. and resistive load and reactive load.

[0035] FIGS. 15A-C are graphs showing modulated sinusoidal waveforms that may be used with a wide-range switched-mode power amplifier, according to some embodiments.

[0036] FIGS. 16A-D are graphs showing modulated half-sine waveforms that may be used with a wide-range switched-mode power amplifier, according to some embodiments.

[0037] FIGS. 17A and 17B are schematic diagrams showing examples of a wide-range class-E power amplifier without and with switch capacitances, respectively, according to some embodiments.

[0038] FIGS. 18A and 18B are control sequences and modulated half-sine waveforms that may be used in conjunction with a wide-range class-E power amplifier without and with switch capacitances, respectively, according to some embodiments.

[0039] FIGS. 19A and 19B are schematic diagrams showing examples of a wide-range current-mode class-D power amplifier with and without switch capacitances, respectively, according to some embodiments.

[0040] FIG. 20 is a series of graphs showing control sequences and modulated sinusoidal waveforms that may be used with a wide-range current-mode class D power amplifier, according to some embodiments.

[0041] FIG. 21A is a schematic diagram showing how dynamic frequency tuning can be used to manage the effect of varying load reactance by changing the operating frequency, according to some embodiments.

[0042] FIG. 21B is a schematic diagram showing how phase-switched impedance modulation can be used to manage the effect of varying load reactance by controlling the switch S.sub.1, according to some embodiments.

[0043] FIG. 21C is a schematic diagram showing how structural modulation can be used to manage the effect of varying load reactance by controlling the switches, according to some embodiments.

[0044] FIG. 21D is a schematic diagram showing how a combination of dynamic frequency tuning, phase-switched impedance modulation, and structural modulation can be used to manage the effect of varying load reactance by changing the operating frequency and controlling the switches, according to some embodiments.

[0045] FIG. 22 is a schematic diagram showing an example of a wide-range voltage-mode class-D power amplifier with multiple output, according to some embodiments.

[0046] FIGS. 23A-E are graphs showing examples of modulated square-wave waveforms in modulation with some control strategies.

[0047] The drawings are not necessarily to scale, or inclusive of all elements of a system, emphasis instead generally being placed upon illustrating the concepts, structures, and techniques sought to be protected herein.

DETAILED DESCRIPTION

[0048] Referring to FIG. 1, an illustrative power amplifier system 100 can include a DC voltage source 102 (V.sub.dc), a load 104, a switched-mode power amplifier 106 coupled between the voltage source 102 and the load 104, and a controller 108 coupled to the amplifier 106. Power amplifier 106 can include one or more switches and other electronic devices (e.g., capacitors and inductors) arranged in a particular circuit topology, detailed examples of which are described below in conjunction with several other figures.

[0049] Controller 108 may operate the switches of power amplifier 106 according to one or more control sequences and using modulation as discussed in detail below. In some cases, controller 108 may also implement a secondary control scheme such as dynamic frequency modulation (i.e., changing the operating frequency of the power amplifier). More generally, the power, voltage, and/or current delivered to load 104 can be controlled using modulation, frequency modulation, or both. Controller 108 can include hardware and/or software configured implement disclosed control schemes and, in some embodiments, can be provided as an application specific integrated circuit (ASIC). Disclosed power amplifier topologies and control schemes allow for wide operating ranges, including resistive load range and reactive load range and/or a wide range of power levels.

[0050] In some embodiments, and as shown in FIG. 1, controller 108 may be configured to adapt and/or frequency modulation of amplifier 106 based on one or more inputs. For examples, controller 108 may be configured to receive commands via signal path 110 for setting and/or switching frequency to desired values. As another example, controller 108 may be configured to receive feedback from load via signal path 112 and to adapt and/or switching frequency based on said feedback. In some cases, systems 100 may include a VI probe or other type of sensor for measuring power, impedance, reactance, and/or another electrical characteristic of load 104, and the output of such a sensor may be used to provide feedback to controller 108. As yet another example, an adaptive feedforward technique may be used to adjust and/or switching frequency.

[0051] In some embodiments, controller 108 may be configured to perform phase-switched impedance modulation, structural modulation, or both using structures and techniques described below.

[0052] Turning to FIGS. 2A and 2B, according to some embodiments, a wide-range voltage-mode class-D power amplifier architecture can have six switches for a double-ended (or differential) version, or three switches for a single-ended version. The double-ended variant provides improved harmonic content in the output and higher power capability than the single-ended variant at the expense of a higher component count.

[0053] FIG. 2A shows an example of an inverter 200 according to a six-switch voltage-mode class-D power amplifier architecture. A load 202 is modeled as a series combination of a resistor R.sub.load and an inductor L.sub.load, which is in series with a first inductor 204 (L.sub.s) and a capacitor 206 (C.sub.s). A second inductor 208 (L.sub.ZVS) is used to achieve the zero-voltage switching of switches, which will be illustrated later. The inverter 200 further includes a set of six total switches 210a-f (S.sub.1-6) with a first set of three switches 210a, 210c, 210e (S.sub.1, S.sub.3, S.sub.5) arranged in series and a second set of three switches 210b, 210d, 210f (S.sub.2, S.sub.4, S.sub.6) also be arranged in series, as shown. A voltage source 220 (V.sub.dc) may be connected as shown.

[0054] The six switches 210a-f may be configured to generate one or more first intermediate waveforms having one or more fundamental frequency components. A subset of the switches 210a-f can be configured to chop the one or more first intermediate waveforms with controllable timing to generate one or more second intermediate waveforms having fundamental frequency components that are controllably reduced from those of the first intermediate waveforms.

[0055] As shown in the figure, a first voltage v.sub.a1 can be defined across a node connecting switches 210a. 210c (S.sub.1, S.sub.3) and ground; a second voltage v.sub.b1 can be defined across a node connecting switches 210b, 210d (S.sub.2, S.sub.4) and ground; a third voltage v.sub.a2 can be defined across a node connecting switches 210c, 210e (S.sub.3, S.sub.5) and ground; and a fourth voltage v.sub.b2 can be defined across a node connecting switches 210d, 210f (S.sub.4, S.sub.6) and ground. With this arrangement, a first intermediate waveform can be taken as v.sub.ab1(v.sub.a1-b1)=v.sub.a1v.sub.b1 and a second intermediate waveform can be taken as v.sub.ab2(v.sub.a2-b2)=v.sub.a2v.sub.b2. Equivalently, v.sub.a1, v.sub.b1, and v.sub.ab1 may both be referred to as a first intermediate waveform and v.sub.a2, v.sub.b2, and v.sub.ab2 may both be referred to as a second intermediate waveform.

[0056] The load 202, first inductor 204 (L.sub.s), and capacitor 206 (C.sub.s) may collectively be referred to as the load branch. In the architecture of FIG. 2A, the load branch is close to ground (i.e., can be connected to ground by a single switch 210e or 210f). In contrast. FIG. 2B shows a version of a six-switch inverter 240 wherein the load branch is close to voltage source 220 (V.sub.dc) (i.e., can be connected to V.sub.dc by a single switch 210e or 210f). Like elements of FIGS. 2A and 2B are indicated using like reference numerals.

[0057] Inverter 200 of FIG. 2A and inverter 240 of FIG. 2B can be controlled such that voltage v.sub.ab1(v.sub.a1-b1)=v.sub.a1v.sub.b1 is ideally a square wave, as shown in FIGS. 3A-C and approximately trapezoidal in practice, as shown in 9A-C. In the figures, v.sub.ab1=v.sub.a1v.sub.b1 and v.sub.ab2=v.sub.a2v.sub.b2. As shown, phase control angle is used to create a phase-controlled (or chopped) waveform v.sub.ab2(v.sub.a2-b2)=v.sub.a2v.sub.b2, based on voltage v.sub.a1-b1; whose nonzero duration or duty ratio depends on . In other words, controls chopping from a first intermediate waveform 302 to a second intermediate waveform 304. The fundamental component v.sub.a2-b2_1st of v.sub.a2-b2, is controlled by , which provides a means to control RF output power. In the case of an ideal square wave, where the rise and fall times of v.sub.a1-b1 and v.sub.a2-b2 are instantaneous, has a usable range of 0180. Fundamentals of the second intermediate waveform 304 are filtered by the load branch (or output tank network) to produce sinusoidal output 306. In this and other examples disclosed herein, the output tank is comprised of L.sub.s and C.sub.s. Graphs 300, 320, and 340 show examples for three different control angles .

[0058] The six-switch wide-range voltage-mode class-D power amplifier is related to the full-bridge voltage-mode class-D power amplifier but utilizes additional switches to achieve a wide output control range while preserving efficient operation.

[0059] FIG. 4 shows control sequences (switch functions) of the six switches, where a switching function state of one (1) indicates a switch is on and state of zero (0) indicates a switch is off. Graphs 400a-f illustrate respective control sequences 402a-f for respective switches 210a-f (S.sub.1-6) of FIGS. 2A and 2B.

[0060] As shown, S.sub.1 and S.sub.2 may operate (e.g., ideally operate) in a complementary fashion (i.e., neglecting dead time). In the first half cycle. S.sub.1, S.sub.4, and S.sub.6 are on. S.sub.3 also conducts during the first portion of the first half cycle but turns off at control angle at which point S.sub.5 turns on (neglecting dead time) and conducts while S.sub.3 is off. In the second half cycle. S.sub.2, S.sub.3 and S.sub.5 are held on. S.sub.4 conducts for the first portion of the second half of the cycle, turning off at +180, at which point S.sub.6 turns on (again, neglecting deadtime between S.sub.4 and S.sub.6).

[0061] The circuit operation over these intervals is shown in FIGS. 5A-5D. As shown in FIG. 5A, between 0, v.sub.a1=v.sub.a2=V.sub.dc, v.sub.b1=v.sub.b2=0 with switches S.sub.1, S.sub.3, S.sub.4, and S.sub.6 turned on. As shown in FIG. 5B, between 180, v.sub.a1=V.sub.dc, v.sub.a2=0, v.sub.b1=v.sub.b2=0 with switches S.sub.1, S.sub.4, S.sub.5, and S.sub.6 turned on. As shown in FIG. 5C, between 180+180, v.sub.a1=v.sub.a2=0, v.sub.b1=v.sub.b2=V.sub.dc with switches S.sub.2, S.sub.3, S.sub.4, and S.sub.5 turned on. As shown in FIG. 5D, between +180360, v.sub.a1=v.sub.a2=0, v.sub.b1=V.sub.dc, v.sub.b2=0 with switches S.sub.2, S.sub.3, S.sub.5, and S.sub.6 turned on.

[0062] Other related six-switch variants providing similar control capabilities can likewise be realized. For example, consider the inverter 240 of FIG. 2B where the load branch is connected between the top four switches. The top two switches are S.sub.5 and S.sub.6 (210e and 210f) while the bottom four switches are S.sub.3, S.sub.4, S.sub.1, S.sub.2 (210c. 210d. 210a. 210b), v.sub.a2-b2 is the modulated waveform of v.sub.a1-b1(v.sub.ab1)=v.sub.a1v.sub.b1, Where v.sub.a2-b2(v.sub.ab2)=v.sub.a2v.sub.b2 is still the voltage across the load branch of C.sub.s, L.sub.s, L.sub.load, and R.sub.load, and v.sub.a1-b1 is the voltage across the inductor L.sub.ZVS. With the control sequences in FIG. 4, the circuit in FIG. 2B can also modulate v.sub.a1-b1 as v.sub.a2-b2, shown in FIG. 3.

[0063] Three-switch single-ended versions of the wide-range voltage-mode class-D power amplifier can also be formulated, as illustrated in FIGS. 6A and 6B. This implementation creates a single polarity square wave in voltage v.sub.1, and a modulated rectangular waveform of a different duty ratio in voltage v.sub.2.

[0064] FIG. 6A shows an example of an inverter 600 according to a three-switch voltage-mode class-D power amplifier architecture. A load 602 is connected in series with a first inductor 604 (L.sub.s) and a first capacitor 606 (C.sub.s). A second inductor 608 (L.sub.ZVS) is used to achieve the zero-voltage switching of switches. Inverter 600 further includes three switches 610a, 610c, 610e (S.sub.1, S.sub.3, S.sub.5) arranged in series, as shown. A voltage source 620 (V.sub.dc) may be connected as shown. Inverter 600 can also include second and third capacitors 612a, 612b (C.sub.big) for voltage-second balance of L.sub.ZVS.

[0065] As shown in the figure, a first voltage v.sub.1 can be defined across a node connecting switches 610a, 610c (S.sub.1, S.sub.3) and ground and a second voltage 12 can be defined across a node connecting switches 610c, 610e (S.sub.3, S.sub.5) and ground. With this arrangement, v.sub.1 may correspond to a first intermediate waveform and v.sub.2 may correspond to a second intermediate waveform.

[0066] In the architecture of FIG. 6A, the load branch is close to ground. In contrast. FIG. 6B shows a version of a three-switch inverter 640 wherein the load branch is close to voltage source 620 (V.sub.dc). Like elements of FIGS. 6A and 6B are indicated using like reference numerals.

[0067] As illustrated in FIGS. 7A-C, inverter 600 of FIG. 6A and inverter 640 of FIG. 6B can be controlled such that voltage v.sub.1 is (ideally) a square wave. As shown, phase control angle is used to create a phase-controlled (or chopped) waveform v.sub.2 whose nonzero duration or duty ratio depends on . In other words, controls chopping from a first intermediate waveform 702 to a second intermediate waveform 704. Fundamentals of the second intermediate waveform 704 are filtered by the output tank to produce sinusoidal output 706. Graphs 700, 720, and 740 show examples for three different control angles .

[0068] The three-switch single-ended version of the circuit can provide power control using fewer switches but may result in even harmonics in the output voltage waveforms and less load power.

[0069] Control sequences 400, 420, and 440 of FIG. 4 can be used to control a three-switch inverter such as inverter 600 of FIG. 6A or inverter 640 6B. That is, whereas the six-switch version uses all the six control sequences, the three-switch version may use only those sequences corresponding to S.sub.1, S.sub.3, and S.sub.5 for example.

[0070] What follows is an analysis of wide-range switched-mode power amplifiers according to the present disclosure. While the analysis is presented herein in terms of six-switch topologies, the subject matter sought to be protected herein extends to topologies with other numbers of switches, including but not limited to three-switch topologies.

[0071] For the waveforms in FIGS. 3A-3C, the peak amplitude and phase of the k.sup.th harmonic of v.sub.a2-b2 can be calculated as

[00001]$\begin{array}{cc}.Math.V_k.Math.=\frac{2\sqrt{2}}{k}{V}_{\mathrm{dc}}\sqrt{1-\cos \left(k\right)}& \left(1\right)\end{array}$$\mathrm{and}$$\begin{array}{cc}{}_k=-\arctan \frac{1-\cos k}{\sin k}& \left(2\right)\end{array}$ [0072] where harmonic order k equals 1 for v.sub.a2-b2_1st, k is odd. The corresponding fundamental time-domain expression of v.sub.a2-b2 is v.sub.a2-b2_1st=|V.sub.1|cos(t+.sub.1).

[00002]$\mathrm{If}=,.Math.V_k.Math.=\frac{4}{k}{V}_{\mathrm{dc}}\mathrm{and}{}_k=-\frac{}{2},$

which are the amplitudes and phases of the square-wave Fourier series.

[0073] The average load power owing to the k.sup.th harmonic component may be calculated as

[00003]$\begin{array}{cc}{P}_k=\frac{1}{2}{.Math.I_k.Math.}^2{R}_{\mathrm{load}}=\frac{1}{2}\frac{{.Math.V_k.Math.}^2{R}_{\mathrm{load}}}{{\left[\left(L_S+L_{\mathrm{load}}\right)-\frac{1}{C_S}\right]}^2+R_{\mathrm{load}}^2}& \left(3\right)\end{array}$ [0074] where is the operating frequency and |V.sub.k| can be calculated from equation (1). For a high-quality output filter tank, the average load power P can be approximated as being fundamental power P.sub.1.

[0075] For a given resistive load R.sub.load, different values of will result in different voltages applied to the load and hence different load power. To maintain the power range P.sub.minP.sub.max for a given R.sub.load, there is a range .sub.min.sub.max. There are minimum and maximum load resistance values R.sub.min and R.sub.max that are the boundaries to achieve a minimum to maximum power range P.sub.minP.sub.max for .sub.min.sub.max with a specified DC voltage V.sub.dc.

[0076] Given a high quality-factor output tank L.sub.s, C.sub.s, a switching frequency can be selected that makes the net series reactance posed by the output tank L.sub.s, C.sub.s, and load inductance L.sub.load provide a desired value, such that and power range only depend on the resistive load (in the range R.sub.minR.sub.max). In this way, for a given resistive component of the load impedance, similar circuit operation and waveforms can be maintained irrespective of the load reactance. That is, frequency modulation can be used to make the net reactance posed by the tank and the load be some desired values. Techniques for frequency selection/modulation are described in detail below. Additional techniques for achieving a wide operating range are also described in detail below.

[0077] Turning to FIG. 8, in some practical applications, switches may be nonideal such that the voltages v.sub.a1-b1 and v.sub.a2-b2 may not rise and fall instantaneously. For example, switches have an output capacitance which may be modeled as a capacitance C.sub.sw in parallel with the switch.

[0078] Illustrative inverter 800 includes a first inductor 804 (L.sub.s) and a first capacitor 806 (C.sub.s) connected in series with a load 802, along with a second inductor 808 (L.sub.ZVS) for achieving the zero-voltage switching of switches. The inverter 800 further includes six switches 810a-f (S.sub.1-6) each in parallel with a respective capacitor 810a-f (C.sub.sw1-6). A voltage source 820 (V.sub.dc) may be connected as shown. The switches may be operated, for example, using the control sequences of FIG. 10.

[0079] As a consequence of switch capacitances C.sub.sw1-6, the circuit voltage waveforms have finite rise and fall times. To avoid switching loss at high frequency, zero-voltage switching (ZVS) may be implemented in a manner such that the switch voltage remains small at device turn-off, and devices are turned on only when they have small voltage across them. Thus, in some cases, despite providing modulated output waveforms, each switch can be turned on and off with zero voltage switching. Some transitions for ZVS switching in the circuits of FIG. 8 depend on the second inductor 808 (i.e., LVS inductor L.sub.ZVS). Others depend upon the net inductance in the load series branch (L.sub.s, C.sub.s, L.sub.load, and R.sub.load). ZVS for this second group of transitions can also be implemented with an additional inductive reactance branch (not shown) placed in parallel with the load series branch.

[0080] FIGS. 9A-C show waveforms that may be generated within the inverter 800 of FIG. 8. Graphs 900, 920, and 940 show examples for three different control angles , with first intermediate waveform 902, second intermediate waveform 904, and sinusoidal output 906 being plotted in each graph. The modulation variable is in the range of .sub.1180.sub.2, v.sub.ab1=v.sub.a1v.sub.b1 and v.sub.ab2=v.sub.a2v.sub.b2. In FIG. 8. L.sub.zvs relates to the ZVS switch voltage transition times .sub.1 and .sub.1 in FIGS. 9A-C and the net inductance from the load series branch relates to the ZVS switch voltage transition time .sub.1 and .sub.2 in FIGS. 9A-C.

[0081] Because of switch capacitances (C.sub.sw1-6), as shown in FIG. 8 and finite rise and fall times of voltages v.sub.a1-b1 and v.sub.a2-b2, as shown in FIG. 9, a voltage rise time .sub.1 and fall time .sub.1 in v.sub.a1-b1 (expressed in electrical angle) can be defined. .sub.1 and .sub.1 of can be the same or different and do not need to depend heavily on loading conditions. The rise time of v.sub.a2-b2 follows v.sub.a1-b1 as .sub.1 and its fall time .sub.2 depends on the loading conditions.

[0082] The practical waveforms of v.sub.a1-b1, v.sub.a2-b2, and v.sub.a2-b2_1st are shown in FIGS. 9A-C. Because of the existence of nonzero rise/fall times .sub.1 and .sub.2, |V.sub.k| and .sub.k become

[00004]$\begin{array}{cc}.Math.V_k.Math.=\frac{2\sqrt{2}}{k^2}{V}_{\mathrm{dc}}\sqrt{\frac{1-\cos \left(k{}_1\right)}{{}_1^2}+\frac{1-\cos \left(k{}_2\right)}{{}_2^2}+\frac{\cos \left[k\left(+{}_2\right)\right]+\cos \left[k\left(-{}_1\right)\right]-\cos \left(k\right)-\cos \left[k\left(+{}_2-{}_1\right)\right]}{{}_1{}_2}}& \left(4\right)\end{array}$$\mathrm{and}$$\begin{array}{cc}{}_k=-\arctan \frac{{}_1\sin k+{}_2\sin \left(k{}_1\right)-{}_1\sin \left[k\left(+{}_2\right)\right]}{{}_1\cos k+{}_2\cos \left(k{}_1\right)-{}_2-{}_1\cos \left[k\left(+{}_2\right)\right]}& \left(5\right)\end{array}$

respectively, where |V.sub.k| and .sub.k are the peak amplitude and phase of the k.sup.th harmonic of v.sub.a2-b2, respectively, k is odd.

[0083] The corresponding fundamental time-domain expression of v.sub.a2-b2 is

[00005]$\begin{array}{cc}{v}_{a2-b2\_1\mathrm{st}}=.Math.V_1.Math.\cos \left(t+{}_1\right)& \left(6\right)\end{array}$

where |V.sub.1| and .sub.1 are the amplitude and phase from equations (4) and (5), respectively.

[0084] The average load power owing to the k.sup.th harmonic component may be calculated as

[00006]$\begin{array}{cc}{P}_k=\frac{1}{2}{.Math.I_k.Math.}^2{R}_{\mathrm{load}}=\frac{1}{2}\frac{{.Math.V_k.Math.}^2{R}_{\mathrm{load}}}{{\left[\left(L_S+L_{\mathrm{load}}\right)-\frac{1}{C_S}\right]}^2+R_{\mathrm{load}}^2}& \left(7\right)\end{array}$

where is the operating frequency and |V.sub.k| is from equation (4).

[0085] FIG. 10 shows control sequences that may be used for the wide-range voltage-mode class-D power amplifier with switched capacitances, such as inverter 800 of FIG. 8. FIGS. 11A-H illustrate circuit operation of such an amplifier. In FIG. 10, graphs 1000a-f illustrate control sequences 1002a-f for six switches S.sub.1 6 having capacitances.

[0086] As shown in FIG. 11A, between 0.sub.1, v.sub.a1=v.sub.a2, v.sub.b2=0 with switches S.sub.3 and S.sub.6 turned on. As shown in FIG. 11B, between .sub.1, v.sub.a1=v.sub.a2=V.sub.dc, v.sub.b1=v.sub.b2=0 with switches S.sub.1, S.sub.3, S.sub.4 and S.sub.6 turned on. As shown in FIG. 11C, between +.sub.2, v.sub.a1=V.sub.dc, v.sub.b1=v.sub.b2=0 with switches S.sub.1, S.sub.4 and S.sub.6 turned on. As shown in FIG. 11D, between +.sub.2180, v.sub.a1=V.sub.dc, v.sub.a2=0, v.sub.b1=v.sub.b2=0 with switches S.sub.1, S.sub.4, S.sub.5 and S.sub.6 turned on. As shown in FIG. 11E, between 180180+.sub.1, v.sub.a2=0, v.sub.b1=v.sub.b2 with switches S.sub.4 and S.sub.5 turned on. As shown in FIG. 11F, between .sub.1+180+180, v.sub.a1=v.sub.a2=0, v.sub.b1=v.sub.b2=V.sub.dc with switches S.sub.2, S.sub.3, S.sub.4 and S.sub.5 turned on. As shown in FIG. 11G, between +180+.sub.2+180 v.sub.a1=v.sub.a2=0, v.sub.b1=V.sub.dc with switches S.sub.2, S.sub.3 and S.sub.5 turned on. As shown in FIG. 11H, between +.sub.2+180360, v.sub.a1=v.sub.a2=0, v.sub.b1=V.sub.dc, v.sub.b2=0 with switches S.sub.2, S.sub.3, S.sub.5 and S.sub.6 turned on.

[0087] Compared to FIG. 4, the control sequences 1002a-f of FIG. 10 include dead time between switches to permit zero-voltage switching: S.sub.1 turns on with a delay angle .sub.1 after S.sub.5 turns off under ZVS. During the dead-time interval 0<t<.sub.1, v.sub.a1=v.sub.a2 increases to V.sub.dc by i.sub.zvs charging C.sub.5 so that S.sub.1 can have ZVS turn-on, which can be observed in FIG. 11A. Also, during this interval, i.sub.zvs discharges C.sub.4 so that S.sub.4 can have ZVS turn-on. S.sub.3 still turns off at but S.sub.5 turns on with a dead-time delay .sub.2. During this dead-time delay, C.sub.5 gets discharged by i.sub.load, so that S.sub.5 can have ZVS turn-on, as shown in FIG. 11C. (As previously mentioned, an additional inductive branch in parallel with the output network branchnot shown in FIG. 8can also provide current for ZVS switching.) The turn off of S.sub.1 and S.sub.5 maintain unchanged without any delay as compared to the idealized case. The other three switches S.sub.2, S.sub.4, and S.sub.6 operate 180 out of phase with the switches S.sub.1, S.sub.3, and S.sub.5, respectively. As in the control sequence in FIG. 4, the AND of S.sub.3 and S.sub.5 is S.sub.2 while AND of S.sub.4 and S.sub.6 is S.sub.1 in FIG. 10, which is similar to that with ZVS class-D full-bridge operation.

[0088] Given the input DC voltage V.sub.dc, it is desired to realize an output power range P.sub.minP.sub.max for a load range R.sub.minR.sub.max with an example reactive component of 0L.sub.load,max. (A capacitive component to the load represented with an equivalent capacitance up to C.sub.load,max could likewise be considered.) For example, consider an example with V.sub.dc=300 V, P.sub.min=300 W, P.sub.max=3000 W, a 4 resistive load range. i.e., R.sub.max/R.sub.min=4, a reactive load component from j 0 to +j 15, and the quality factor Q of the load branch (C.sub.s, L.sub.s, R.sub.load, and L.sub.load) is 520, e.g., as determined by waveform purity and/or frequency range considerations. With given V.sub.dc=300 V and power range P.sub.min=300 WP.sub.max=3000 W, Q.sub.min=5 for the series branch (L.sub.s, C.sub.s, L.sub.load, and R.sub.load), and center frequency f.sub.c=13.56 MHz, parameters can be determined as follows.

[0089] FIG. 10A shows additional control sequences that may be used for the wide-range voltage-mode class-D power amplifier with switch capacitances, such as inverter 800 of FIG. 8. In FIG. 10A, graphs 1020a-f illustrate control sequences 1022a-f for six switches S.sub.1-6 having capacitances. In contrast to the control sequences of FIG. 10, the control sequences 1022a-f of FIG. 10A include an additional dead time between switches, namely delay angle 83. This results in ten (10) different operating regions labeled (a)-(j) in FIG. 10A.

[0090] The disclosed wide-range power amplifier architecture is able to maintain ZVS for all inverter devices across load and power conditions; this is achieved by charging and discharging switch capacitances C.sub.sw by i.sub.zvs and i.sub.load during dead times .sub.1, .sub.2, and .sub.3.

[0091] Modeling i.sub.zvs and i.sub.load can be important for predicting ZVS conditions. Because the voltage across L.sub.zvs is approximately a square wave (albeit with nonzero rise and fall times, as seen in FIG. 5, the current flow through L.sub.zvs is an approximately symmetric triangle waveform that can be expressed as:

[00007]$\begin{array}{cc}{i}_{\mathrm{ZVS}}=\{\begin{array}{c}\frac{2I_{\mathrm{ZVS},\mathrm{pk}}}{}t-I_{\mathrm{ZVS},\mathrm{pk}},0+k.Math.2t<+k.Math.2\\ -\frac{2I_{\mathrm{ZVS},\mathrm{pk}}}{}t+3I_{\mathrm{ZVS},\mathrm{pk}},+k.Math.2t<2+k.Math.2\end{array}& \left(8\right)\end{array}$$\mathrm{with}{I}_{\mathrm{ZVS},\mathrm{rms}}=\frac{1}{\sqrt{3}}{I}_{\mathrm{ZVS},\mathrm{pk}}\mathrm{and}{I}_{\mathrm{ZVS},\mathrm{pk}}=\frac{V_{\mathrm{dc}}{T}_s}{4L_{\mathrm{ZVS}}}.$

[0092] As long as the quality factor Q of the load branch is high enough, for example, Q=5, the load current i.sub.load can be represented as

[00008]$\begin{array}{cc}{i}_{\mathrm{load}}=I_{\mathrm{load},\mathrm{pk}}\cos \left(t+{}_1-{}_{\mathrm{load}}\right)& \left(9\right)\end{array}$$\mathrm{where}{I}_{\mathrm{load},\mathrm{pk}}=\frac{.Math.V_1.Math.}{\sqrt{R_{\mathrm{load}}^2+X_{\mathrm{net}}^2}}\mathrm{and}\tan {}_{\mathrm{load}}=\frac{X_{\mathrm{net}}}{R_{\mathrm{load}}}$

|V.sub.1| is the fundamental component. e.g., from equation (1).

[0093] ZVS can be important for high-frequency and very-high-frequency power conversion. For practical voltage-mode class D power amplifiers, there are dead times in control sequences as seen in FIG. 10 and FIG. 10A to enable switch capacitances to losslessly charge and discharge, so that the switches can have zero-voltage turn-on. In some cases, three dead-times: .sub.1, .sub.2, and .sub.3 may be considered in the wide-range voltage-mode class D power amplifier.

[0094] Regarding .sub.1, consider the commutation of current from S.sub.5 to S.sub.1 with S.sub.3 held on. During .sub.1, v.sub.a1=v.sub.a2. The combination of i.sub.zvs and i.sub.load charge C.sub.sw5 and discharge C.sub.sw1. S.sub.1 turns on at zero voltage when v.sub.a1=v.sub.a2=V.sub.dc. Assume v.sub.a1=v.sub.a2=v.sub.1(t),

[00009]$\begin{array}{cc}{i}_{\mathrm{Csw}1}+i_{\mathrm{Csw}5}=-i_{\mathrm{ZVS}}-i_{\mathrm{load}}& \left(10\right)\end{array}$$\mathrm{where}$$i_{\mathrm{Csw}1}=C_{\mathrm{sw}1}\frac{d\left(v_1-v_{\mathrm{dc}}\right)}{\mathrm{dt}}=C_{\mathrm{sw}1}\frac{{dv}_1}{\mathrm{dt}}$$\mathrm{and}$$i_{\mathrm{Csw}5}=C_{\mathrm{sw}5}\frac{d\left(v_1-0\right)}{\mathrm{dt}}=C_{\mathrm{sw}5}\frac{{dv}_1}{\mathrm{dt}}.$

[0095] With the integration during .sub.1,

[00010]$\begin{array}{cc}{}_0^{V_{\mathrm{dc}}}\left(C_{\mathrm{sw}1}+C_{\mathrm{sw}5}\right){dv}_1=-{}_0^{{}_1/}\left(i_{\mathrm{ZVS}}+i_{\mathrm{load}}\right)\mathrm{dt}.& \left(11\right)\end{array}$

[0096] The precise solution can be derived from

[00011]$\begin{array}{cc}\left(C_{\mathrm{sw}1}+C_{\mathrm{sw}5}\right)V_{\mathrm{dc}}=-{}_0^{{}_1}\left[i_{\mathrm{ZVS}}\left(t\right)+i_{\mathrm{load}}\left(t\right)\right]d\left(t\right).& \left(12\right)\end{array}$

[0097] Regarding i.sub.zvs(t)i.sub.zvs(0)=I.sub.zvs,pk and i.sub.load(t)i.sub.load(0)=I.sub.load,pk cos(.sub.1.sub.load) from equations (8) and (9) during .sub.1, a linear approximation can be

[00012]$\begin{array}{cc}\left(C_{\mathrm{sw}1}+C_{\mathrm{sw}5}\right)\frac{V_{\mathrm{dc}}}{{}_1}=I_{\mathrm{ZCS},\mathrm{pk}}-I_{\mathrm{load},\mathrm{pk}}\cos \left({}_1-{}_{\mathrm{load}}\right).& \left(13\right)\end{array}$

[0098] Assuming C.sub.sw1=C.sub.sw5=C.sub.sw (i.e., equal effective switch capacitances),

[00013]$\begin{array}{cc}{}_1=\frac{2C_{\mathrm{sw}}{V}_{\mathrm{dc}}}{\frac{V_{\mathrm{dc}}{T}_S}{4L_{\mathrm{ZVS}}}-\frac{.Math.V_1.Math.}{\sqrt{R_{\mathrm{load}}^2+X_{\mathrm{net}}^2}}\cos \left({}_1-\arctan \frac{X_{\mathrm{net}}}{R_{\mathrm{load}}}\right)}& \left(14\right)\end{array}$

where |V.sub.1| can be calculated from equation (1) without considering the dead times for simplicity.

[0099] Then

[00014]$\begin{array}{cc}{}_1=\frac{2C_{\mathrm{SW}}}{\frac{T_S}{4L_{\mathrm{ZVS}}}-\frac{\frac{2\sqrt{2}}{}\sqrt{1-\cos }}{\sqrt{R_{\mathrm{load}}^2+X_{\mathrm{net}}^2}}\cos \left({}_1-\arctan \frac{X_{\mathrm{net}}}{R_{\mathrm{load}}}\right)}& \left(15\right)\end{array}$

[0100] For ZVS turn-on of S.sub.1, there is no requirement on the current direction of i.sub.load as long as I.sub.zvs,pk>I.sub.load,pk cos(.sub.1.sub.load). .sub.1 is almost load independent.

[0101] Regarding .sub.2, consider commutation of current from S.sub.3 to S.sub.5 with S.sub.1 held on, i.sub.load charges C.sub.sw3 and discharges C.sub.sw5. S.sub.5 turns on at zero voltage when v.sub.a2=0. Assuming v.sub.a2=v.sub.2(t),

[00015]$\begin{array}{cc}{i}_{Csw3}+i_{Csw5}=i_{load}& \left(16\right)\end{array}$$\mathrm{where}$$i_{Csw3}=C_{sw3}\frac{d\left(V_{dc}-v_2\right)}{dt}=-C_{sw3}\frac{{\mathrm{dv}}_2}{\mathrm{dt}}$$\mathrm{and}$$i_{Csw5}=C_{sw5}\frac{d\left(0-v_2\right)}{dt}=-C_{sw5}\frac{{\mathrm{dv}}_2}{dt}$

[0102] With the integration during 82,

[00016]$\begin{array}{cc}{}_{V_{dc}}^0-\left(C_{sw3}+C_{sw5}\right)d{v}_2={}_{/}^{\left(+{}_z\right)/}{i}_{\mathrm{load}}\left(t\right)\mathrm{dt}.& \left(17\right)\end{array}$

[0103] The precise solution can be derived from

[00017]$\begin{array}{cc}\left(C_{sw3}+C_{sw5}\right)V_{dc}={}_{}^{\left(+{}_2\right)}{i}_{\mathrm{load}}\left(t\right)d\left(t\right)& \left(18\right)\end{array}$

[0104] Regarding i.sub.load(t)I.sub.load()=I.sub.load,pk cos(+.sub.1.sub.load) from equations (8) and (9) during .sub.2, a linear approximation can be made

[00018]$\begin{array}{cc}\left(C_{sw3}+C_{\mathrm{sw}5}\right)\frac{V_{dc}}{{}_2}=I_{\mathrm{load},\mathrm{pk}}\cos \left(+{}_1-{}_{\mathrm{load}}\right)& \left(19\right)\end{array}$$\mathrm{Similarly},$$\begin{array}{cc}{}_2=\frac{2C_{sw}}{\frac{\frac{2\sqrt{2}}{}\sqrt{1-\cos }}{\sqrt{R_{\mathrm{load}}^2+x_{net}^2}}\cos \left(+{}_1-\arctan \frac{x_{\mathrm{net}}}{R_{\mathrm{load}}}\right)}& \left(20\right)\end{array}$

where it is again assumed all switch capacitances are equal.

[0105] For ZVS turn-on of S.sub.5, i.sub.load() has to be positive. .sub.2 is load dependent.

[0106] Regarding .sub.3, consider commutation of current from S.sub.1 to S.sub.3 with S.sub.5 held on, i.sub.zvs charges C.sub.sw1 and discharges C.sub.sw3. S.sub.3 turns on at zero voltage when v.sub.a1=0. Assuming v.sub.a1=v.sub.3(t),

[00019]$\begin{array}{cc}{i}_{\mathrm{Csw}1}+i_{\mathrm{Csw}3}=i_{\mathrm{zvs}}& \left(21\right)\end{array}$$\mathrm{where}$$i_{\mathrm{Csw}1}=C_{\mathrm{sw}1}\frac{d\left(V_{dc}-v_3\right)}{dt}=-C_{\mathrm{sw}1}\frac{{\mathrm{dv}}_3}{\mathrm{dt}}$$\mathrm{and}$$i_{\mathrm{Csw}3}=C_{\mathrm{sw}3}\frac{d\left(0-v_3\right)}{dt}=-C_{\mathrm{sw}3}\frac{{\mathrm{dv}}_3}{dt}.$

[0107] With the integration during 83,

[00020]$\begin{array}{cc}{}_{V_{dc}}^0-\left(C_{sw1}+C_{sw3}\right)d{v}_3={}_{/-{}_3/}^{/}{i}_{zvs}\left(t\right)dt.& \left(22\right)\end{array}$

[0108] The precise solution can be derived from

[00021]$\begin{array}{cc}\left(C_{sw1}+C_{sw3}\right)V_{dc}={}_{-{}_3}^{}{i}_{zvs}\left(t\right)d\left(t\right).& \left(23\right)\end{array}$

[0109] Regarding i.sub.zvs(t)i.sub.zvs()=I.sub.zvs,pk from equations (8) and (9) during .sub.3, a linear approximation can be

[00022]$\begin{array}{cc}\left(C_{sw1}+C_{sw3}\right)\frac{V_{dc}}{{}_3}=I_{\mathrm{zvs},\mathrm{pk}}& \left(24\right)\end{array}$$\mathrm{Similarly},$$\begin{array}{cc}{}_3=\frac{8L_{\mathrm{ZVS}}{C}_{sw}}{T_s}& \left(25\right)\end{array}$

[0110] For ZVS turn-on of S.sub.3, there is no requirement of i.sub.load(t) during .sub.3 at all. .sub.3 is fully load-independent.

[0111] In practice, .sub.1 and .sub.3 can overlap with each other or contain each other. The rise of v.sub.a1 and the fall of v.sub.b1 can happen at the same time. The fall of v.sub.a1 and the rise of v.sub.b1 can happen at the same time as well.

[0112] Next describes are techniques for frequency selection/modulation. Because of variable reactive loads, which can be inductive L.sub.load as shown in FIG. 8 or capacitive C.sub.load, the operating frequency may be selected to keep net reactance X.sub.net formed by the output tank and load reactance constant.

[00023]$\begin{array}{cc}{X}_{\mathrm{net}}={}_c\left(L_s-\frac{1}{{}_c^2{C}_S}\right)=\left(L_s-\frac{1}{{}^2{C}_s}\right)+X_{\mathrm{load}}& \left(26\right)\end{array}$

where X.sub.load=L.sub.load for an inductive load or X.sub.load=1/C.sub.load for a capacitive load. .sub.c is the angular center frequency, e.g., 213.56 MHz. The operating frequency

[00024]$\begin{array}{cc}\begin{array}{c}=\frac{{}_c{L}_{net}+\sqrt{{\left({}_c{L}_{net}\right)}^2+4\left(L_s+L_{load}\right)/C_s}}{2\left(L_s+L_{\mathrm{load}}\right)}\\ =\frac{{}_c{L}_{net}+\sqrt{{\left({}_c{L}_{net}\right)}^2+4L_s/\left(C_s+C_{\mathrm{load}}\right)}}{2L_s}\end{array}& \left(27\right)\end{array}$

where .sub.cL.sub.net=.sub.cL.sub.s1/.sub.cC.sub.5=X.sub.net, which is used to achieve ZVS of the switches. The frequency selection under L.sub.load and C.sub.load is shown in FIGS. 12A and 12B, respectively.

[0113] FIGS. 12 and 12A illustrate dynamic frequency modulation under different L.sub.load and C.sub.load for constant X.sub.net. In FIG. 12A, a graph 1200 plots operating frequency 1202 and impedance X.sub.net 1204 as a function of L.sub.load. In FIG. 12B, a graph 1220 plots frequency 1222 and impedance X.sub.net 1224 as a function of C.sub.load.

[0114] The average power owing to the k.sup.th harmonic component becomes

[00025]$\begin{array}{cc}{P}_k=\frac{1}{2}{.Math.I_k.Math.}^2{R}_{\mathrm{load}}=\frac{1}{2}\frac{{.Math.V_k.Math.}^2{R}_{\mathrm{load}}}{X_{net}^2+R_{\mathrm{load}}^2}& \left(28\right)\end{array}$

from equation (7), where we are interested in the dominant component of average power P.sub.1. By selecting operating frequency as equation (27), P.sub.1 in equation (28) is invariant to L.sub.load or C.sub.load but depends on R.sub.load. Also, with high-Q filtering from the output tank, the shape of the relevant operating waveforms remain the same for a given R.sub.load.

[0115] Other modulation methods can be used as well for the series load branch, shown in FIGS. 21A-D, or other frequency selection criteria can be used.

[0116] Turning to FIG. 13, initially, one can regard X.sub.net=0, which would be the case if ZVS of the switches were realized with an additional ZVS inductive branch placed in parallel with the output network branch instead of using i.sub.load with an inductive X.sub.net. The average power owing to the k.sup.th harmonic component becomes

[00026]$\begin{array}{cc}{P}_k=\frac{1}{2}{.Math.I_k.Math.}^2=\frac{1}{2}\frac{{.Math.V_k.Math.}^2}{R_{\mathrm{load}}}& \left(29\right)\end{array}$

[0117] Assuming .sub.1=0 and .sub.2=0, |V.sub.k| in equation (4) becomes equation (1), the average power owing to the k.sup.th harmonic component becomes

[00027]$\begin{array}{cc}{P}_k=\frac{1}{2}{.Math.I_k.Math.}^2=\frac{4}{k^2{}^2}\frac{V_{dc}^2\left[1-\cos \left(k\right)\right]}{R_{\mathrm{load}}}& \left(30\right)\end{array}$

[0118] Only fundamental power is considered because of high enough quality factor

[00028]$\begin{array}{cc}{P}_1=\frac{4}{{}^2}\frac{V_{dc}^2\left(1-\cos \right)}{R_{\mathrm{load}}}.& \left(31\right)\end{array}$

[0119] The relationship among P.sub.1, , and R.sub.load is shown in FIG. 13 from (31). FIG. 13 illustrates power P.sub.1, , resistive load R.sub.load relationship for X.sub.net=0, .sub.1=0, and .sub.2=0. In FIG. 13. R.sub.max=24 to have the full power range. In a graph 1300, is plotted by lines 1302 and 1306, whereas power is plotted by lines 1304 and 1308.

[0120] With

[00029]$\begin{array}{cc}\begin{array}{c}{L}_s^{}/C_s=Q_{\min }^2{R}_{\max }^2\\ L_s^{}{C}_s=1/{}_c^2\end{array}& \left(32\right)\end{array}$

and Q.sub.min=5, R.sub.max=24, .sub.c=213.56 Mrad/s, the result is L.sub.s=1.41 H and C.sub.s=97.8 pF. L.sub.s=L.sub.s+L.sub.remain where L.sub.net=X.sub.net/.sub.c can be determined to achieve ZVS with C.sub.sw=80 pF during .sub.2. In some cases, one can select L.sub.net=90 nH.

[0121] The resulting quality factor of the output load branch (L.sub.s, C.sub.s, L.sub.load, R.sub.load) will be higher than Q.sub.min=5 in equation (32), satisfying the requirement. In some cases, L.sub.s and C.sub.s may be selected according to a conservative design with respect to the quality factor.

[0122] Turning to FIGS. 14A and 14B, given the known variables and requirements, one can plot the relationship among power P.sub.1, , and R.sub.load from equation (7), as shown, considering X.sub.net. FIGS. 14A and 14B illustrate the relationship between power, , and R.sub.load considering X.sub.net, .sub.1, and .sub.2. Graph 1400 of FIG. 14A shows power range for different and R.sub.load from equation (7). It can be seen that some R.sub.load can not achieve the full power range. e.g. R.sub.load=1 and R.sub.load=25. R.sub.min=3 and R.sub.max=20. Graph 1420 of FIG. 14B shows achievable power range for within the limits under different R.sub.load. The single points may come, for example, from simulation with consideration of different L.sub.load with dynamic frequency modulation.

[0123] Turning to FIGS. 15A-C, similar to an ideal square-wave or a quasi square-wave, and single polarity square-wave that can be modulated or switched as shown in FIGS. 3, 9, and 7, the sine wave or half-sine wave can also be modulated, which can be shown in FIGS. 15A-C for modulated sine-wave and FIGS. 16A-D for modulated half-sine wave in ideal cases where the fall time at is instantaneous. Modulated half-sine wave has one more degree of freedom where the half resonant period can be smaller than or larger than 180 while modulated sine wave has to have the half resonant period less than 180. This is also true for square-wave and single polarity square-wave in six-switch wide-range voltage-mode class-D power amplifier and the three-switch wide-range voltage-mode class-D power amplifier, respectively.

[0124] FIGS. 15A-C show modulated sinusoidal waveforms that may be used with a wide-range switched-mode power amplifier, according to some embodiments. Graphs 1500, 1520, and 1540 show examples for three different control angles , with first intermediate waveform 1502, second intermediate waveform 1504, and sinusoidal output 1506 plotted in each graph. In FIGS. 15A-C, D180=1802, 0<D180; v.sub.ab1=v.sub.a1v.sub.b1 and v.sub.ab2=v.sub.a2v.sub.b2.

[0125] FIGS. 16A-D show modulated half-sine waveforms that may be used with a wide-range switched-mode power amplifier, according to some embodiments. Graphs 1600, 1620, 1640, and 1660 show examples for three different control angles , with first intermediate waveform 1602, second intermediate waveform 1604, and sinusoidal output 1606 plotted in each graph. In these figures, 0<D<1 and 0<(1D)360; v.sub.ab1=v.sub.a1v.sub.b1 and v.sub.ab2=v.sub.a2v.sub.b2. In FIG. 16A, (1D)360>180. In FIG. 16B, (1D)360>180. In FIG. 16C, (1D)360<180. In FIG. 16D, (1D)360<180.

[0126] The circuit to achieve the waveform modulation in FIGS. 16A-D can be a wide-range class-E power amplifier, such amplifier 1700 of FIG. 17A and/or amplifier 1720 of FIG. 17B. The circuit to achieve modulation in FIGS. 15A-C can be a wide-range current-mode class-D power amplifier, as amplifier 1900 of FIG. 19A and/or amplifier 1920 of FIG. 19B. These represent related single-ended and double-ended converter concepts, respectively, just as the single- and double-ended concepts described for the wide-range voltage-mode class-D inverter.

[0127] Practically, v.sub.2 cannot goes to zero instantaneously and the switches have switch capacitance C.sub.sw. ZVS turn off of v.sub.a2-b2 and v.sub.2 corresponding switches can be achieved, similar to FIGS. 9 and 11.

[0128] FIGS. 18A and 18B show control sequences and modulated half-sine waveforms, with graph 1800 of FIG. 18A corresponding to an ideal case of the circuit in FIG. 17A with 0<D<1 and 0<(1D)360, and graph 1820 of FIG. 18B corresponding to a practical case of the circuit in FIG. 17B with 0<D<1 and 0<(1D)360.

[0129] An example of circuit operation of wide-range class-E power amplifiers is that C.sub.1 and L.sub.1 with AND of S.sub.1 and S.sub.2 form a load-independent half-sine wave v.sub.1 first and then S.sub.1 and S.sub.2 modulate v.sub.1 as v.sub.2. Through the series load branch L.sub.s, C.sub.s, L.sub.load, and R.sub.load, the load can obtain different power levels based on different duty ratio D, , and (dead time related). FIGS. 18A and 18B shows the control sequences and modulated half-sine waveforms with ideal and practical wide-range class-E power amplifiers shown in FIGS. 17A and 17B with L.sub.1=109.55 nF, C.sub.1=740 pF, C.sub.sw=20 pF, L.sub.s=1.17 F, C.sub.s=117 pF in simulation.

[0130] As part of the operational capability of this approach, variable power can be achieved for a given resistive load or constant power can be achieved for a variable resistive load. Dynamic frequency modulation can be used to deal with reactive loads.

[0131] An example of circuit operation of wide-range current-mode class-D power amplifiers is that C.sub.p and L.sub.p with AND of S.sub.1 and S.sub.3 and AND of S.sub.2 and S.sub.4 form a load-independent sine wave v.sub.a1_b1 first and then the four switches modulate v.sub.ab1(v.sub.a1-b1)=v.sub.a1v.sub.b1 as v.sub.ab2(v.sub.a2-b2)=v.sub.a2v.sub.b2. Through the series load branch L.sub.s, C.sub.s, L.sub.load, and R.sub.load, the load can obtain different power levels based on different duty ratio D and (neglecting dead time). In FIG. 20, a graph 2000 shows the control sequences and modulated sinusoidal waveforms with ideal wide-range current-mode class-D power amplifiers shown in FIGS. 19A and 19B with L.sub.p=97.8 nF, C.sub.p=978 pF, C.sub.sw=0.1 pF, L.sub.s=3.35 F, C.sub.s=46.94 pF in simulation.

[0132] As part of the operational capability of this approach, variable power can be achieved for a given resistive load or constant power can be achieved for a variable resistive load. Dynamic frequency modulation can be used to deal with reactive loads.

[0133] FIGS. 21A-D illustrate additional or alternative structures and techniques to handle/manage varying load reactance, according to embodiments of the present disclosure. Managing variations in the reactive component of the load impedance can allow for fixed-frequency operation in the face of variable load reactance. As previously discussed, dynamic frequency tuning can be used to manage the effect of varying load reactance, as one example. This is shown by circuit 2100 of FIG. 21A for the series load branch C.sub.s, L.sub.s, L.sub.load, and R.sub.load. A switching frequency can be selected that makes the net series reactance posed by the output tank L.sub.s, C.sub.s, and load inductance Load provide a desired value X.sub.net. As another example, as illustrated by circuit 2120 of FIG. 21B, phase-switched modulation may be used. As another example, as illustrated by circuit 2140 of FIG. 21C, structural modulation may be used (e.g., in the form of a switching network). As another example, as illustrated by circuit 2160 of FIG. 21D, a combination of these techniques may be used (e.g., phase-switch modulation in combination with structural modulation). In some cases, the load branch can also be a parallel branch or a combination of series and parallel branch.

[0134] Turning to FIG. 22, the general concepts, structures, and techniques sought to be protected herein can provide for wide-range power amplifiers having multiple output. An illustrative wide-range voltage-mode class-D power amplifier 2200 includes N sets 2202a-n of four switches, with load branches 2204-n arranged in parallel connected to v.sub.a1 and v.sub.b1. Each set 2202a-n can generate a modulated waveform v.sub.a2-b2_n of v.sub.a1-b1, as shown in FIGS. 3A-C. Each v.sub.a2-b2_n and its fundamental component v.sub.a2-b2_n_1st can be the same or different for the same or different series load branch with the same or different C.sub.s_n, L.sub.s_n, L.sub.load_n, and R.sub.load_n.

[0135] Similarly, other wide-range circuits including six-switch voltage-mode class-D power amplifier (FIGS. 2A, 2B and FIG. 8), three-switch voltage-mode class-D power amplifier (FIGS. 6A, 6B), current-mode class-D power amplifier (FIGS. 19A, 19B), and class-E power amplifier (FIGS. 17A, 17B) can also have multiple output.

[0136] In general, as the modulation suggests, different zero-state portions or more zero-state portions can be applied to v.sub.a1-b1 as v.sub.a2-b2, as shown in FIGS. 23A-E. Graphs 2300, 2320, 2340, 2360, and 2380 show five different examples of modulation, with first intermediate 2302 and second intermediate waveform 2304 plotted in each graph. It is still achievable to calculate fundamental component v.sub.a2-b2_1st and corresponding load power from different modulated or chopped v.sub.a2-b2 and corresponding allocation.

[0137] The publication Wide-range switched-mode power amplifier architecture. 2023 IEEE 24th Workshop on Control and Modeling for Power Electronics (COMPEL). Ann Arbor, MI. USA. 2023. pp. 1-9, by Xin Zan. Khandoker Nuzhat Rafa Islam, and David Perreault is hereby incorporated by reference in its entirety.

[0138] As used herein, the terms processor and controller are used to describe electronic circuitry that performs a function, an operation, or a sequence of operations. The function, operation, or sequence of operations can be hard coded into the electronic circuit or soft coded by way of instructions held in a memory device. The function, operation, or sequence of operations can be performed using digital values or using analog signals. In some embodiments, the processor or controller can be embodied in an application specific integrated circuit (ASIC), which can be an analog ASIC or a digital ASIC, in a microprocessor with associated program memory, in a digital signal processor (DSP), and/or in a discrete electronic circuit, which can be analog or digital. A processor or controller can include internal processors or modules that perform portions of the function, operation, or sequence of operations. Similarly, a module can include internal processors or internal modules that perform portions of the function, operation, or sequence of operations of the module.

[0139] As used herein, the term predetermined. when referring to a value or signal, is used to refer to a value or signal that is set, or fixed, in the factory at the time of manufacture, or by external means, e.g., programming, thereafter. As used herein, the term determined, when referring to a value or signal, is used to refer to a value or signal that is identified by a circuit during operation, after manufacture.

[0140] While electronic circuits shown in figures herein may be shown in the form of analog blocks or digital blocks, it will be understood that the analog blocks can be replaced by digital blocks that perform the same or similar functions and the digital blocks can be replaced by analog blocks that perform the same or similar functions. Analog-to-digital or digital-to-analog conversions may not be explicitly shown in the figures but should be understood.

[0141] In the foregoing detailed description, various features are grouped together in one or more individual embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that each claim requires more features than are expressly recited therein. Rather, inventive aspects may lie in less than all features of each disclosed embodiment.

[0142] References in the disclosure to one embodiment. an embodiment, some embodiments, or variants of such phrases indicate that the embodiment(s) described can include a particular feature, structure, or characteristic, but every embodiment can include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment(s). Further, when a particular feature, structure, or characteristic is described in connection knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0143] The disclosed subject matter is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways. As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out the several purposes of the disclosed subject matter. Therefore, the claims should be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.

[0144] Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the disclosed subject matter may be made without departing from the spirit and scope of the disclosed subject matter.

[0145] All publications and references cited herein are expressly incorporated herein by reference in their entirety.