Abstract
A circuit for a smart semiconductor switch includes an electronic switch electrically coupled between an output node and a supply node. An overcurrent protective circuit is configured to generate an overcurrent signal in response to a load current flowing through the electronic switch exceeding a first overcurrent threshold, and to cause the electronic switch to be tripped. A control circuit is configured to switch the electronic switch on and off based on an input signal in a first mode, and to drive a load connected to the output node by repeatedly switching the electronic switch on and off in a second mode, and to prevent the electronic switch from being permanently tripped by the overcurrent protective circuit.
Claims
1. A circuit, comprising: an electronic switch electrically coupled between an output node and a supply node; a current measurement circuit configured to measure a load current flowing through the electronic switch to produce a current measurement signal based on the load current; an overcurrent protective circuit configured to generate an overcurrent signal in response to the load current flowing through the electronic switch exceeding a first overcurrent threshold based on the current measurement signal, the overcurrent signal configured to cause the electronic switch to be tripped; and a control circuit configured to: in a first mode, switch the electronic switch on and off based on an input signal, and in a second mode, drive a load connected to the output node by repeatedly switching the electronic switch on and off based on a temperature of the electronic switch, and prevent the electronic switch from being permanently tripped by the overcurrent protective circuit.
2. The circuit of claim 1, wherein the load is a capacitive load, and wherein the control circuit is configured to gradually drive the capacitive load in the second mode by repeatedly switching the electronic switch on and off.
3. The circuit of claim 1, wherein the control circuit is configured to prevent the electronic switch from being permanently tripped by the overcurrent protective circuit in the second mode by replacing the first overcurrent threshold with a second overcurrent threshold that is higher than the first overcurrent threshold.
4. The circuit of claim 1, wherein the control circuit is configured to prevent the electronic switch from being permanently tripped by the overcurrent protective circuit in the second mode by temporarily deactivating the overcurrent protective circuit.
5. The circuit of claim 1, wherein the control circuit is configured to prevent the electronic switch from being permanently tripped by the overcurrent protective circuit in the second mode by causing a filtering of transient overcurrent states that are shorter than a selected delay time.
6. The circuit of claim 1, further comprising: a configuration circuit configured to be electrically coupled to a resistor, wherein the configuration circuit is configured to set the first overcurrent threshold based on a resistance value of the resistor.
7. The circuit of claim 1, further comprising: a detection circuit configured to activate the second mode based on at least one of the input signal or a command signal received by the detection circuit.
8. The circuit of claim 7, wherein activating the second mode comprises increasing the first overcurrent threshold.
9. The circuit of claim 7, wherein the detection circuit is configured to activate the second mode in response to the input signal being modulated.
10. The circuit of claim 1, wherein the control circuit comprises a driver circuit configured to drive the electronic switch, the driver circuit being configured to drive the electronic switch at a lower slew rate in the second mode than in the first mode.
11. The circuit of claim 1, wherein the control circuit is configured to trip the electronic switch in response to the temperature of the electronic switch exceeding a temperature threshold.
12. The circuit of claim 1, wherein the control circuit is configured to trip the electronic switch in response to a temperature difference between the temperature of the electronic switch and a temperature of a chip located at a distance from the electronic switch exceeding a temperature difference threshold.
13. The circuit of claim 1, further comprising: an overtemperature protective circuit configured to trigger an overtemperature tripping of the electronic switch in response to at least one of the temperature of the electronic switch or a temperature difference between the temperature of the electronic switch and a temperature of a chip located at a distance from the electronic switch reaching a permissible maximum value, the permissible maximum value being higher in the second mode than in the first mode.
14. The circuit of claim 1, wherein the current measurement circuit comprises a shunt resistor coupled in series with the electronic switch.
15. The circuit of claim 1, wherein the current measurement circuit comprises a sense transistor arrangement.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Exemplary embodiments are explained in greater detail below with reference to figures. The illustrations are not necessarily to scale and the exemplary embodiments are not restricted only to the aspects illustrated. Rather, importance is attached to presenting the principles underlying the exemplary embodiments. In the figures:
(2) FIG. 1 illustrates an example of a circuit that can be used as a smart semiconductor switch.
(3) FIG. 2 uses exemplary timing charts to illustrate the operation of the circuit from FIG. 1 on a capacitive load.
(4) FIG. 3 illustrates a modification of the circuit from FIG. 1, in which the threshold for an overcurrent tripping for a capacitive load is set to a maximum.
(5) FIG. 4 uses exemplary timing charts to illustrate the functioning of the circuit from FIG. 3 when the capacitive load is connected.
(6) FIG. 5 illustrates a further example of a circuit that can be used as a smart semiconductor switch.
(7) FIG. 6 shows a modification of the example from FIG. 3.
(8) FIG. 7 uses a timing chart to illustrate the filtering of very short, transient overcurrent events.
(9) FIG. 8 shows a further modification of the example from FIG. 3.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
(10) Before various exemplary embodiments are discussed in more detail, an example of a smart semiconductor switch will first be explained. The example depicted in FIG. 1 shows a smart semiconductor switch having one channel, i.e. one power transistor T.sub.S for driving a load. It goes without saying that the concepts described here can also be applied to multichannel systems. The switching element in the example shown is a MOS transistor, in particular a MOSFET (metal-oxide semiconductor field effect transistor) in the form of a DMOS field effect transistor (double-diffused metal-oxide semiconductor field effect transistor). It goes without saying that other types of electronic switches may also be used, such as e.g. bipolar transistors, IGBTs (insulated gate bipolar transistors) or the like.
(11) In the example depicted in FIG. 1, the switching element (power transistor T.sub.S) is connected between an output node OUT and a supply node VS. Both the output node OUT and the supply node VS can be connected directly (e.g. by way of bonding wires or the like) to appropriate chip contacts (e.g. pins). That is to say that when the power transistor T.sub.S is activated (on) the load current flows from the supply node VS (which is connected to a power supply) via the load current path of the power transistor T.sub.S to the output node OUT, which, during operation, is connected to a load that is symbolized by the resistor R.sub.L in FIG. 1. In the present case, the power transistor T.sub.S operates as a high-side switch. It goes without saying that the concepts described here can also be applied to systems containing low-side switches.
(12) The fact that the power transistor T.sub.S is connected between the nodes VS and OUT does not preclude a further element such as e.g. the current measuring resistor R.sub.S from being able to be arranged between the power transistor T.sub.S and one of the nodes VS or OUT. In the example shown, the measuring resistor R.sub.S (sense resistor) is connected between the source electrode of the (n-channel) power transistor T.sub.S and the nodes OUT. The voltage drop i.sub.L.Math.R.sub.S across the measuring resistor R.sub.S represents the load current i.sub.L flowing through the load current path (in the case of a MOS transistor the drain-source current path) of the transistor.
(13) The control electrode of the power transistor T.sub.S (in the case of a MOS transistor the gate electrode) is driven by a gate driver circuit ii. Said circuit is designed to take a logic signal ON (input signal of the gate driver) as a basis for switching the power transistor T.sub.S on and off. The gate driver 11 may also be designed to control the gradient of the switching edges (i.e. the slew rate). In the example shown, the slew rate is dependent on the signal SR supplied to the gate driver 11. Suitable gate driver circuits are known per se and are therefore not discussed in more detail here.
(14) The logic signal ON is the result of a logic function relating to multiple other logic signals. In the example shown, the logic signal ON is output by the AND gate 13, which performs the function ON=OT.Math.IN.Math.OC. The dot (.Math.) denotes a logic AND function and the overline above OT and OC denotes a negation. OT is a logic signal that indicates an overtemperature state, and OC is a logic signal that indicates an overcurrent state. In the example shown, both an overtemperature state (OT=1, OT=0) and an overcurrent state (OC=1, OC=0) result in the power transistor T.sub.S being tripped. The logic signal IN can be regarded as a switching command for switching the transistor T.sub.S on and off. It is dependent on the input signal received at the input node IN. The logic signal IN signals that the transistor T.sub.S is switched on if either the input signal received at the input node IN indicates a logic 1 or the signal CLS indicates a logic 1. CLS can also be understood as the abbreviation for capacitive load switching (switching a capacitive load). In the example shown, this OR function is performed by the OR gate 14, the output signal from which is the logic signal IN. The CLS mode will be explained in more detail later on, but overcurrent and overtemperature protection are discussed first.
(15) The overcurrent protective circuit 31 depicted in FIG. 1 is designed to compare the current measurement signal with an associated threshold. In the present example, the overcurrent protective circuit 31 signals an overcurrent state (OC=1) if the load current i.sub.L exceeds the associated threshold i.sub.OCT (e.g. i.sub.L.Math.R.sub.S>i.sub.OCT.Math.R.sub.S). Essentially, the overcurrent protective circuit 31 contains a comparator circuit. Suitable comparator circuits are known per se and are therefore not discussed further here. The specific implementation of the overcurrent protective circuit 31 is also dependent, inter alia, on the current measuring circuit used. Instead of the current measuring resistor R.sub.S shown, a so-called sense FET arrangement can also be used, in which some transistor cells of the power transistor are used for current measurement.
(16) The threshold i.sub.OCT is configurable and, in the example shown, is generated by the circuit 32 (denoted by overcurrent threshold generation in FIG. 1) on the basis of the input from an external circuit. The overcurrent protective circuit 31 receives the present threshold i.sub.OCT from the circuit 32. The latter can receive a signal containing information about the desired threshold i.sub.OCT from an external circuit, e.g. an external controller. In one example, the circuit 32 can communicate with an external controller by way of a digital communication interface, for example by means of an SPI (Serial Peripheral Interface). Alternatively, configuration of the threshold by means of a component (e.g. resistor) connected to a configuration pin is also possible (cf. FIG. 5).
(17) In the example shown, two temperature values are measured. A first temperature value T.sub.J represents the temperature of the transistor cell array of the power transistor T.sub.S, ideally the junction temperature of the power transistor. Alternatively, a temperature measurement in the hot area close to the transistor is also possible. A second temperature value T.sub.A represents the chip temperature away from the power transistor, i.e. at a comparatively cool place on the semiconductor chip as far away as possible from the Hot-Spot in the transistor cell array. Suitable temperature sensors integrated in the chip are known per se and are therefore not described further here. The overtemperature protective circuit 23 is designed to take the two temperature measured values T.sub.J and T.sub.A as a basis for indicating an overtemperature state (OT=1).
(18) An overtemperature state can be triggered by various circumstances. By way of example, the overtemperature protective circuit 23 may signal an overtemperature state if the junction temperature T.sub.J of the transistor T.sub.S exceeds a temperature threshold, which in some embodiments may represent a permissible maximum value T.sub.J,max(T.sub.J>T.sub.J,max). Furthermore, the overtemperature protective circuit 23 may signal an overtemperature state if the temperature difference T.sub.J-T.sub.A exceeds a temperature difference threshold, which in some embodiments may represent a permissible maximum value T.sub.max (T.sub.JT.sub.A>T.sub.max). The overtemperature protective circuit 23 (i.e. the comparator contained therein) can exhibit a hysteresis. As such, for example an overtemperature state may be signalled if the condition T.sub.JT.sub.A>T.sub.max is satisfied, but the overtemperature state can be cancelled again only if the condition T.sub.JT.sub.A<T.sub.maxT.sub.H is satisfied. The value T.sub.H here represents the hysteresis. In particular, the values T.sub.max and T.sub.H are configurable. The value T.sub.J,max may also be configurable (for example by means of a digital communication interface). The thresholds T.sub.max and T.sub.maxT.sub.H may also be dependent on whether the smart semiconductor switch operates in a CLS mode, which is described below.
(19) As mentioned, CLS denotes switching on a capacitive load (capacitive load switching). Depending on the implementation, the CLS mode can be activated in different ways. By way of example, there may be provision for a specific chip pin, and the CLS mode can be activated if e.g. a high level is applied to this chip pin. In the example shown, the circuit 21 (denoted by CLS mode detection in FIG. 1) detects and activates the CLS mode if a pulse-width-modulated (PWM) signal having e.g. a duty cycle of 50 percent and a defined frequency is applied to the input node IN. This frequency can be e.g. in the kilohertz range (e.g. 30 kHz). The circuit 21 can detect this frequency in the input signal and use a high level of the logic signal CLS to indicate the CLS mode (CLS=1). A low level of the logic signal CLS signals a normal mode, in which the transistor T.sub.S is switched on if the signal applied to the input node has a high level.
(20) The transistor T.sub.S is also activated/switched on in the CLS mode, but the transition to the CLS mode results in some operating parameters of the smart semiconductor switch being altered. In the example shown in FIG. 1, the circuit 22 (denoted by CLS settings in FIG. 1) is designed to reconfigure the gate driver 11 in such a way that the slew rate (SR) of the switching edges is lowered (compared to the normal mode). In addition, the circuit 22 may be designed to reconfigure the parameters (temperature thresholds and hysteresis) of the overtemperature protective circuit 23 and to reset them to the previous (standard) values again on leaving the CLS mode.
(21) When overcurrent protection is active, a problem can arise in the CLS mode that is explained below on the basis of the timing charts shown in FIG. 2. The top chart in FIG. 2 shows one possibility for activating the CLS mode, namely modulating the input signal supplied to the input node IN, said signal likewise being denoted by IN in FIG. 2. The modulation of the input signal is detected by the circuit 21, and the signal CLS is then set to high (CLS=1). Consequently, the logic signal IN changes to high (IN=1) and so does the logic signal ON (ON=1), therefore, which results in the transistor T.sub.S being switched on. FIG. 2 relates to the case of a capacitive load, resulting in a very high inrush current.
(22) The high inrush current can result in very rapid heating of the transistor T.sub.S and in an overcurrent tripping due to the condition T.sub.J-T.sub.A>T.sub.max (OT=0), the value T.sub.J,max being able to be lower in the CLS mode than in the normal mode. As a consequence of the overcurrent tripping, the transistor T.sub.S cools slightly (T.sub.J-T.sub.A<T.sub.maxT.sub.H), resulting in the transistor T.sub.S being switched on again. The hysteresis of the overtemperature protective circuit 23 results in toggling, i.e. regular switching of the transistor T.sub.S off and on again, with the inrush current i.sub.L charging the capacitance of the load further in each cycle and the output voltage V.sub.OUT (i.e. the voltage V.sub.OUT) rising somewhat in each cycle. This process is depicted in the middle chart in FIG. 2. The regular switching of the load current on and off (toggling) is depicted in the third chart in FIG. 2.
(23) In one exemplary embodiment, the permissible maximum value T.sub.J,max or the permissible maximum value T.sub.max (or both) is set to higher values in the CLS mode than in the normal mode. The permissible maximum values can be configured on the basis of the level of the logic signal CLS.
(24) Regardless of whether different (higher) permissible maximum values are possibly used in the overtemperature protective circuit 23 in the CLS mode than in the normal mode, in practice it may be that during the toggling depicted in FIG. 2 a current peak triggers an undesirable overcurrent tripping in the CLS mode because the load current i.sub.L exceeds the threshold i.sub.OCT set for the respective application at least for a short time. In the example depicted in FIG. 2, the overcurrent tripping is triggered at the time t.sub.A. Switching on again after an overcurrent event generally requires the smart semiconductor switch to be reset.
(25) FIG. 3 shows a modification of the example from FIG. 1 that facilitates a solution to the problem explained on the basis of FIG. 2. The example depicted in FIG. 3 is broadly identical to the example from FIG. 1, and additional reference is made to the explanations above. The text below primarily discusses the differences between the examples from FIG. 3 and FIG. 1.
(26) Specifically, unlike in the example from FIG. 1, the circuit 32 for generating the overcurrent threshold i.sub.OCT in FIG. 3 is designed to generate a different overcurrent threshold for the overcurrent protective circuit 31 in the CLS mode than in the normal mode. While the smart semiconductor switch is not being operated in the CLS mode, the overcurrent threshold I.sub.OCT corresponds to the configured value i.sub.OCT,set. As already mentioned, the circuit 32 is designed to receive information relating to the desired threshold and to set the overcurrent threshold i.sub.OCT accordingly. This information can be received via a digital communication interface, for example, or can also be ascertained on the basis of a device parameter of an external component connected to a chip pin (e.g. on the basis of the resistance value of a connected resistor, see FIG. 5). When the CLS mode is active, this configuration is overwritten (override) and the circuit 32 sets the overcurrent threshold i.sub.OCT to a predefined or selected standard value i.sub.OCT,max, which may correspond to a permissible maximum overcurrent threshold, for example. When the CLS mode is left, the overcurrent threshold i.sub.OCT is reset from the predefined or selected standard value i.sub.OCT,max to the previously configured i.sub.OCT,set again.
(27) The (undesirable) permanent overcurrent tripping, depicted in FIG. 2, when a capacitive load is switched on is prevented by temporarily raising the threshold i.sub.OCT from i.sub.OCT,set to i.sub.OCT,max. In this context, permanent means until a reset command is received, since the detection of an overcurrent condition i.sub.L>i.sub.OCT is stored in a latch (flipflop). That is to say that, after an overcurrent state has been detected, the logic signal OT remains at a high level (OT=1) until the latch is reset. It is therefore not possible for the smart semiconductor switch to automatically switch on again. The reset command generally needs to be produced by an external controller. The control electronics of the smart semiconductor switch (in particular the circuit 21 for detecting the CLS mode and the circuit 32 for overcurrent threshold generation) are thus designed to prevent the electronic switch from being permanently tripped by the overcurrent protective circuit 31 (using the AND gate 13) in the CLS mode.
(28) The way in which the circuit from FIG. 3 functions is explained in more detail below on the basis of the timing charts in FIG. 4. The top timing chart in FIG. 4 is the same as in FIG. 2, and in this example too the control command for activating the smart semiconductor switch in the CLS mode consists in a PWM signal with a e.g. 50 percent duty cycle and a defined frequency of e.g. 30 kHz being supplied to the input node IN. This input signal can be generated and supplied to the input node IN e.g. by an external controller (for example a microcontroller).
(29) The bottom timing chart in FIG. 4 shows the characteristic of the load current i.sub.L as the result of the regular switching of the power transistor T.sub.S on and off (toggling), which, as explained above, is dependent on the temperature T.sub.J of the power transistor T.sub.S, in particular on the difference temperature T.sub.JT.sub.A. The middle timing chart shows the resultant gradual rise in the output voltage V.sub.OUT until (approximately) the level of the supply voltage V.sub.S is reached (V.sub.OUTV.sub.S).
(30) The bottom timing chart likewise depicts the overcurrent threshold i.sub.OCT and also the changeover of the threshold i.sub.OCT from the threshold i.sub.OCT,set configured for the respective application to the standard (maximum) value i.sub.OCT,max and back to the value i.sub.OCT,set again. It can be seen that the temporary increase of the overcurrent threshold i.sub.OCT prevents detection of an overcurrent state and the associated permanent tripping of the power transistor (i.e. until a reset command is received).
(31) The circuit in FIG. 5 is a modification of the circuit from FIG. 3. In particular, FIG. 5 shows a possible implementation of the circuit 32 that generates the overcurrent threshold i.sub.OCT for the overcurrent protective circuit 31. As shown in FIG. 5, the circuit 32 is connected to a configuration pin OC, to which an external resistor, denoted by R.sub.OC in FIG. 5, can be connected during operation. The circuit 32 is designed to set the overcurrent threshold i.sub.OCT on the basis of the resistance value of the external resistor R.sub.OC. By way of example, the circuit 32 can apply a defined (e.g. constant) voltage U.sub.ROC to the configuration pin OC and set the overcurrent threshold i.sub.OCT on the basis of the resultant current U.sub.ROC/R.sub.OC. As in the previous examples already, the overcurrent threshold i.sub.OCT is set to a standard value/maximum value if the signal CLS indicates the activation of the CLS mode. When the CLS mode ends, the overcurrent threshold i.sub.OCT is reset to the value predefined by the external resistor R.sub.OC again. Otherwise, the circuit from FIG. 5 is the same as that in FIG. 3, and reference is made to the above description in relation to FIG. 3.
(32) As mentioned, the circuit 32 (optionally in combination with further circuit components) in the exemplary embodiments described here is designed to prevent the power transistor T.sub.S from being permanently tripped (i.e. up to a reset) by the overcurrent protective circuit 31. According to the examples shown in FIGS. 3 and 5, this permanent tripping is prevented by temporarilywhile the CLS mode is activeincreasing the overcurrent threshold i.sub.OCT. In the example from FIG. 6, this permanent tripping is prevented by temporarily, in particular while the CLS mode is active, deactivating the overcurrent circuit 31.
(33) FIG. 6 shows a modification of the circuit from FIG. 3. As shown in FIG. 6, the logic signal CLS, which indicates an active CLS mode, is used as a disable signal DIS for the circuit 31. That is to say that the overcurrent protective circuit 31 is inactive while the CLS mode is active. The circuit 32 generates the desired/configured threshold i.sub.OCT for example on the basis of the value of an external resistor. The components in FIG. 6 that are not explained at this juncture are the same as in FIG. 3, and reference is made to the description above.
(34) According to a further exemplary embodiment, the aforementioned permanent tripping is prevented by virtue of the overcurrent protective circuit 31 being designed to signal an overcurrent state (OC=1) at least in the CLS mode only when the overcurrent condition i.sub.L>i.sub.OCT is satisfied for a determined, defined delay time. That is to say that an overcurrent state (OC=1) is signaled only after the delay time, and very short, transient incursions above the overcurrent threshold i.sub.OCT are filtered/ignored. Suitable circuits that omit/suppress short, transient pulses shorter than the delay time in the logic signal OC are known per se and are therefore not discussed further here. The functioning of such a circuit, which may be contained in the overcurrent protective circuit 31, is shown in FIG. 7. Short, transient overcurrent states i.sub.L>i.sub.OCT such as for example at the time t.sub.1 (see FIG. 7, overcurrent state from t.sub.1 to t.sub.1+T.sub.P) do not result in tripping. As soon as the state i.sub.L>i.sub.OCT lasts for a defined delay time T.sub.F, an overcurrent state is signalled by the logic signal OC=1 and tripping is triggered (see FIG. 7, overcurrent state from time t.sub.2 results in tripping at the time t.sub.2+T.sub.F).
(35) The example from FIG. 8 is a modification of the example from FIG. 3, in which a switch-on command for activating the power transistor in the normal mode, a command for activating (and optionally deactivating) the CLS mode and the overcurrent threshold to be set are received via a digital communication interface 35. In this example, the switch-on signal IN, which results in the power transistor T.sub.S being switched on, is generated by the logic circuit 34 on the basis of the data received via the interface 35. The circuit 21 generates the logic signal CLS on the basis of the received data. As in the previous examples, a high level of the signal CLS indicates the CLS mode. FIG. 8 likewise shows an explicit reset for the overcurrent protective circuit 31 by way of a command received via the communication interface. In the example shown, the communication interface generates a reset signal RES for the overcurrent protective circuit 31, resulting in a signaled overcurrent state being cancelled and it being possible for the power transistor T.sub.S to be switched on again. It goes without saying that in other exemplary embodiments the reset signal RES can also be generated in another way and does not necessarily have to be generated on the basis of data that are received via a digital interface.
(36) It goes without saying that the circuits depicted in the figures are merely examples. A person skilled in the art is capable of also implementing the same or an equivalent function using (in part) other components. It goes without saying that logic levels at one or more nodes of the circuits can be inverted, which does not result in the functioning of the circuit being changed if the logic components are adapted as appropriate. All of the logic functions can therefore be implemented e.g. using NAND or NOR gates without significantly changing the functioning of the circuit by and large.
