Method for controlling fault using switching technique of three phase four wire interlinking converter

Abstract

A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.

Claims

1. A process-implemented method for controlling fault of a three phase four wire interlinking converter comprising a processor, the method comprising: obtaining, by the processor, a first d-q-o coordinate plane based on an internal phase angle of an output voltage produced from each phase of an inverter; converting, by the processor, the first d-q-o coordinate plane to a second d-q-o coordinate plane based on an o-axis configured differently from the first d-q-o coordinate plane; obtaining, by the processor, an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining, by the processor, occurrence of a fault and an area related to the fault based on the output voltage vector; and allocating, by the processor in the occurrence of the fault, a zero voltage vector to the area related to the fault.

2. The method of claim 1, wherein the determining of the area related to the fault comprises determining the area based on switching states of the output voltage vector, and wherein the switching states mean an on/off combination of switching components controlled separately by respective output phases of a three phase AC power source.

3. The method of claim 1, wherein the allocating of the zero voltage vector to the area related to the fault comprises applying a symmetric space vector voltage modulation method to determine an order of providing the zero voltage vector.

4. A non-transitory computer-readable medium storing a program for executing the method of claim 1 in a computer system.

5. A three phase four wire interlinking converter system, the system comprising: an inverter configured to convert a DC power to a three phase AC power and output the three phase AC power; and a processor configured to control switching components included in the inverter to control the three phase AC power output separately for each phase, wherein the processor is further configured to: obtain a first d-q-o coordinate plane based on an internal phase angle of an output voltage produced from each phase of the inverter; convert the first d-q-o coordinate plane to a second d-q-o coordinate plane based on an o-axis configured differently from the first d-q-o coordinate plane; obtain an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determine occurrence of a fault and an area related to the fault based on the output voltage vector; and allocate a zero voltage vector to the area related to the fault.

6. The system of claim 5, wherein, when determining the area related to the fault, the processor is configured to determine the area related to the fault based on switching states of the output voltage vector, and wherein the switching states mean an on/off combination of switching components controlled separately by respective output phases of a three phase AC power source.

7. The system of claim 5, wherein, when allocating the zero voltage vector to the area related to the fault, the processor is configured to allocate the zero voltage vector to the area related to the fault by applying a symmetric space vector voltage modulation method to determine an order of providing the zero voltage vector.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included herein as a part of detailed descriptions to help understanding the present disclosure, provide embodiments of the present disclosure and describe technical features of the present disclosure with detailed descriptions below.

(2) FIG. 1 is a circuit diagram illustrating a situation in which a short circuit occurs between lines of a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(3) FIG. 2 is a block diagram of a three-phase four-wire interlinking converter according to one embodiment of the present disclosure.

(4) FIG. 3 is a flow diagram illustrating a method for controlling a fault of a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(5) FIGS. 4A to 4C show results of performing o-axis transform to a voltage vector on a distorted voltage vector plane when a short circuit occurs in a three-phase four wire interlinking converter system according to one embodiment of the present disclosure.

(6) FIGS. 5A to 5C illustrate space vectors in the occurrence of a line-to-line short circuit of a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(7) FIGS. 6A to 6C show combination results using a symmetric space vector voltage modulation method when a short circuit occurs in a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(8) FIGS. 7A to 7D illustrate d-q-o transform of unbalanced voltage in the occurrence of a U-V line-to-line short circuit of a three-phase four wire interlinking converter system according to one embodiment of the present disclosure.

(9) FIGS. 8A to 10D illustrate fault control of an interlinking converter in the occurrence of a line-to-line short circuit of an interlinking converter system according to one embodiment of the present disclosure.

(10) FIG. 11 illustrates d-, q-axis voltage vectors for controlling a fault in the occurrence of a U-V line-to-line short circuit of an interlinking converter according to one embodiment of the present disclosure.

(11) FIG. 12 illustrates switching duty on the U, V, W, N phase in the occurrence of a U-V line-to-line short circuit of an interlinking converter according to one embodiment of the present disclosure.

(12) FIGS. 13A and 13B illustrates output phase voltages and line-to-line voltage waveforms of an interlinking converter when SVPWM is performed using switching duty in the occurrence of a U-V line-to-line short circuit of an interlinking converter according to one embodiment of the present disclosure.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

(13) In what follows, embodiments disclosed in this document will be described in detail with reference to appended drawings, where the same or similar constituting elements are given the same reference number irrespective of their drawing symbols, and repeated descriptions thereof will be omitted. The suffixes, “module” and “unit”, for the constituting elements used in the following descriptions are assigned or used interchangeably only for the convenience of writing the present document and do not have separate meanings or roles distinguished from each other. Also, in describing an embodiment disclosed in the present document, if it is determined that a detailed description of a related art incorporated herein unnecessarily obscure the gist of the embodiment, the detailed description thereof will be omitted. Also, it should be understood that the appended drawings are intended only to help understand embodiments disclosed in the present document and do not limit the technical principles and scope of the present disclosure; rather, it should be understood that the appended drawings include all of the modifications, equivalents or substitutes described by the technical principles and belonging to the technical scope of the present disclosure.

(14) Terms including an ordinal number such as first or second may be used to describe various constituting elements, but the constituting elements should not be limited by the terms. Those terms are used only for the purpose of distinguishing one constituting element from the others.

(15) If a constituting element is said to be “connected” or “attached” to other constituting element, the former may be connected or attached directly to the other constituting element, but there may be a case in which another constituting element is present between the two constituting elements. On the other hand, if a constituting element is said to be “directly connected” or “directly attached” to other constituting element, it should be understood that there is no other constituting element between the two constituting elements.

(16) A singular expression should be understood to indicate a plural expression unless otherwise explicitly stated.

(17) In the present disclosure, the term “include” or “have” is used to indicate existence of an embodied feature, number, step, operation, element, component, or a combination thereof; and should not be understood to preclude the existence or possibility of addition of one or more other features, numbers, steps, operations, elements, components, or a combination thereof.

(18) FIG. 1 is a circuit diagram illustrating a situation in which a short circuit occurs between lines of a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(19) Referring to FIG. 1, a short circuit may occur between the V line and the W line in the load phase of an AC system in a standalone DC-AC microgrid.

(20) FIG. 2 is a block diagram of a three-phase four-wire interlinking converter according to one embodiment of the present disclosure.

(21) Referring to FIG. 2, a three-phase four-wire interlinking converter system may include an inverter 100 and at least one processor 110.

(22) The inverter 100 may convert DC power to three-phase AC power and output the three-phase AC power.

(23) The processor 110 may be connected to the inverter converting DC power to three-phase AC power and outputting the three-phase AC power, control switching components included in the inverter to control the three-phase output AC power separately for each phase, obtain a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of the inverter, convert the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane, obtain an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane, determine occurrence of a fault and an area related to the fault based on the output voltage vector, and allocate a zero voltage vector to the area related to the fault.

(24) Since the constituting elements of the three-phase four-wire interlinking converter described in FIG. 2 are an example generally included in an electronic device, the structure of the interlinking converter according to an embodiment of the present disclosure is not limited to the constituting elements described above; part of the constituting elements may be omitted and/or a new constituting element may be added depending on the needs.

(25) The operations of the three-phase four-wire interlinking converter system applied to various embodiments of the present disclosure are not limited to the example described above, and a method for controlling a fault illustrated in FIG. 3 below may be performed by one or more processors included in the three-phase four-wire interlinking converter system. A detailed description will be given later with reference to FIG. 3.

(26) FIG. 3 is a flow diagram illustrating a method for controlling a fault of a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(27) Referring to FIG. 3, the processor 110 of the three-phase four-wire interlinking converter system may obtain a first d-q-o coordinate plane based on an internal phase angle of each output voltage produced from each phase of the inverter S110.

(28) By performing d-q-o transform through synchronized coordinate rotations on each phase, the processor 110 may obtain the first d-q-o coordinates by computing the d-, q-, and o-axis components for each phase.

(29) The processor 110 may transform the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane S120.

(30) By performing o.sub.n-axis coordinate transform of d- and q-axis through o-axis transform, the processor 110 may transform the first d-q-o coordinate plane to the second d-q-o coordinate plane.

(31) In the first d-q-o coordinate transform, an o-axis waveform appears, but the o.sub.n-axis value of the second d-q-o coordinate plane, which performs coordinate transform for a new o.sub.n-axis plane, becomes 0, and only the waveforms of d.sub.n and q.sub.n remain. In other words, unbalanced voltage occurring in the existing o-axis may be removed through new coordinate transform of the d.sub.n-q.sub.n-o.sub.n axis.

(32) By performing d-q transform with respect to the second d-q-o coordinate plane, the processor 110 may obtain an output voltage vector to determine a fault location S130.

(33) A distorted voltage occurring along the existing o-axis is transformed to the second d-q-o coordinate plane and has a phase difference of 120 degrees with respect to the n plane through new coordinate transform of the d.sub.n-q.sub.n-o.sub.n axis.

(34) To compensate for the phase difference, the processor 110 may perform d-q transform with respect to the second d-q-o coordinate plane and convert a signal having a phase difference of 120 degrees into a signal having a phase difference of 90 degrees.

(35) The processor 110 may determine occurrence of a fault and an area related to the fault based on the output voltage vector S140.

(36) The processor 110 may determine the occurrence of a fault and an area related to the fault and generate a space vector through an effective vector and a zero vector selected based on an output voltage vector and a switching state. The generated space vectors may be divided into the respective sector areas. The processor 110 may calculate a reference voltage V.sub.ref for each sector area based on the division.

(37) When the fault occurs, the processor 110 may allocate a zero voltage vector to the area related to the fault S150.

(38) The processor 110 may apply a symmetric space vector voltage modulation method advantageous for harmonic characteristics to determine the time to apply a vector after obtaining the synthesized reference voltage V.sub.ref based on each sector area.

(39) The symmetric space vector voltage modulation method refers to a method in which the effective voltage vector exists in the center of one period after modulation and a zero voltage vector is applied before and after the effective voltage vector for d.sub.0/2 hours. Using the method, the processor 110 may determine the application times of the voltage vectors and allocate the voltage vectors based on a combination of six effective voltage vectors and two zero voltage vectors selected in the occurrence of a line-to-line short circuit.

(40) FIGS. 4A to 4C show results of performing o-axis transform to a voltage vector on a distorted voltage vector plane when a short circuit occurs in a three-phase four wire interlinking converter system according to one embodiment of the present disclosure.

(41) The three-phase four-wire interlinking converter system is controlled by one or more processors 110 constituting the system or connected to the system, and one or more operations described in the following are stored as instructions in one or more memories constituting the system. The one or more processors 110 performs a method for controlling a fault according to various embodiments of the present disclosure using the instructions stored in the one or more memories.

(42) Referring to FIG. 4, the processor 110 analyzes a switching plane in which a zero voltage vector is applied to the fault location of a short circuit of a power distribution network based on switching vector analysis using a switching technique of an interlinking converter. In other words, the processor 110 configures a new o-axis existing on a distorted voltage vector plane and performs coordinate transformation based on the configured o-axis. This coordinate transformation may be referred to as o-axis transform.

(43) The interlinking converter system applied to various embodiments detects a fault of the three-phase four-wire interlinking converter system or performs compensation for the fault using the o-axis transform and the space vector voltage modulation technique (space vector PWM) in the occurrence of a line-to-line short circuit.

(44) Space Vector Modulation Technique (Space Vector PWM, SVPWM)

(45) The triangle wave PWM modulates each of the three-phase reference voltages while space vector PWM modulates the three-phase reference voltage into a space vector of the complex space. Here, a phase voltage may be expressed by a switching state function as shown in Eq. 1.

(46) $\begin{array}{cc}{V}_{\mathrm{an}}=\frac{V_{\mathrm{DC}}}{3}\left(2S_1-S_2-S_3\right)V_{\mathrm{bn}}=\frac{V_{\mathrm{DC}}}{3}\left(-S_1+2S_2-S_3\right)V_{\mathrm{cn}}=\frac{V_{\mathrm{DC}}}{3}\left(-S_1-S_2+2S_3\right)& \left[\mathrm{Eq}.1\right]\end{array}$

(47) The output voltage vectors and switching states when SVPWM is applied to the existing three-phase four-wire interlinking converter are shown in Table 1.

(48) TABLE-US-00001 TABLE 1 S.sub.1S.sub.2S.sub.3S.sub.4 V.sub.UN V.sub.VN V.sub.WN .sub.vα .sub.vβ .sub.vo m {right arrow over (V.sub.1)} 0000 0 0 0 0 0 0 0 {right arrow over (V.sub.2)} 0010 0 0 1 $-\frac{1}{\sqrt{6}}$ $-\frac{1}{\sqrt{2}}$ $\frac{1}{\sqrt{3}}$ 1 {right arrow over (V.sub.3)} 0100 0 1 0 $-\frac{1}{\sqrt{6}}$ $\frac{1}{\sqrt{2}}$ $\frac{1}{\sqrt{3}}$ 1 {right arrow over (V.sub.4)} 0110 0 1 1 $-\frac{2}{\sqrt{3}}$ 0 $\frac{2}{\sqrt{3}}$ 0$\sqrt{2}$ {right arrow over (V.sub.5)} 1000 1 0 0 $\frac{2}{\sqrt{3}}$ 0 $\frac{1}{\sqrt{3}}$ 1 {right arrow over (V.sub.6)} 1010 1 0 1 $\frac{1}{\sqrt{6}}$ $-\frac{1}{\sqrt{2}}$ $\frac{2}{\sqrt{3}}$ $\sqrt{2}$ {right arrow over (V.sub.7)} 1100 1 1 0 $\frac{1}{\sqrt{6}}$ $\frac{1}{\sqrt{2}}$ $\frac{2}{\sqrt{3}}$ 0$\sqrt{2}$ {right arrow over (V.sub.8)} 1110 1 1 1 0 0 $\sqrt{3}$ $\sqrt{3}$ {right arrow over (V.sub.9)} 0001 0 0 0 0 0 $-\sqrt{3}$ $\sqrt{3}$ {right arrow over (V.sub.10)} 0011 0 0 0 $-\frac{1}{\sqrt{6}}$ $-\frac{1}{\sqrt{2}}$ $-\frac{2}{\sqrt{3}}$ $\sqrt{2}$ {right arrow over (V.sub.11)} 0101 0 1 0 $-\frac{1}{\sqrt{6}}$ 0$\frac{1}{\sqrt{2}}$ $\frac{2}{\sqrt{3}}$ $\sqrt{2}$ {right arrow over (V.sub.12)} 0111 0 1 1 $-\frac{2}{\sqrt{3}}$ 0 $-\frac{1}{\sqrt{3}}$ 1 {right arrow over (V.sub.13)} 1001 1 0 0 $\frac{2}{\sqrt{3}}$ 0 $-\frac{2}{\sqrt{3}}$ $\sqrt{2}$ {right arrow over (V.sub.14)} 1011 1 0 1 $\frac{1}{\sqrt{6}}$ $-\frac{1}{\sqrt{2}}$ 0$-\frac{1}{\sqrt{3}}$ 1 {right arrow over (V.sub.15)} 1101 1 1 0 $\frac{1}{\sqrt{6}}$ $\frac{1}{\sqrt{2}}$ $-\frac{1}{\sqrt{3}}$ 1 {right arrow over (V.sub.16)} 1111 1 1 1 0 0 0 0

(49) At this time, V.sub.2 to V.sub.7 and V.sub.10 to V.sub.15 states are called an active voltage vector and have magnitude of two-thirds of DC voltage; V.sub.1, V.sub.8, V.sub.9, and V.sub.16 are zero voltage vectors, indicating a state in which no load is applied.

(50) When the one-line earth fault occurs, to apply a zero voltage to the faulty phase and a normal voltage vector to the remaining phases, the processor 110 selects only the case where the state of the faulty phase is the same as that of N phase. By using a vector selected from the operation above, a three-phase reference voltage may be expressed as one space vector in the complex space.

(51) FIGS. 5A to 5C illustrate space vectors in the occurrence of a line-to-line short circuit of a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(52) The processor 110 may generate a space vector through an effective vector and a zero vector selected based on an output voltage vector and a switching state of the switching component 111.

(53) Referring to FIG. 5A, a vector selected in the occurrence of a U-V line-to-line short circuit is {right arrow over (V.sub.1)}, {right arrow over (V.sub.2)}, {right arrow over (V.sub.7)}, {right arrow over (V.sub.8)}, {right arrow over (V.sub.9)}, {right arrow over (V.sub.10)}, {right arrow over (V.sub.15)}, {right arrow over (V.sub.16)}, and a voltage plane depicted through the selected voltage vectors may be checked. The voltage vector plane is composed of six areas and may be depicted by two sections having different sizes. Also, by using selected vectors, a three-phase reference voltage V.sub.ref may be expressed by one space vector in the complex space, and the reference voltage V.sub.ref may be calculated for each sector area.

(54) Referring to FIG. 5B, a vector selected in the occurrence of a U-W line-to-line short circuit is {right arrow over (V.sub.1)}, {right arrow over (V.sub.3)}, {right arrow over (V.sub.6)}, {right arrow over (V.sub.8)}, {right arrow over (V.sub.9)}, {right arrow over (V.sub.11)}, {right arrow over (V.sub.14)}, {right arrow over (V.sub.16)}, and a voltage plane depicted through the selected voltage vectors may be checked. The voltage vector plane is composed of six areas and may be depicted by two sections having different sizes. Also, by using selected vectors, a three-phase reference voltage V.sub.ref may be expressed by one space vector in the complex space, and the reference voltage V.sub.ref may be calculated for each sector area.

(55) Referring to FIG. 5C, a vector selected in the occurrence of a V-W line-to-line short circuit is {right arrow over (V.sub.1)}, {right arrow over (V.sub.4)}, {right arrow over (V.sub.5)}, {right arrow over (V.sub.8)}, {right arrow over (V.sub.9)}, {right arrow over (V.sub.12)}, {right arrow over (V.sub.13)}, {right arrow over (V.sub.16)}, and a voltage plane depicted through the selected voltage vectors may be checked. The voltage vector plane is composed of six areas and may be depicted by two sections having different sizes. Also, by using selected vectors, a three-phase reference voltage V.sub.ref may be expressed by one space vector in the complex space, and the reference voltage V.sub.ref may be calculated for each sector area.

(56) FIGS. 6A to 6C illustrate switch operations using a symmetric space vector voltage modulation method for each sector when a short circuit occurs in a three-phase four-wire interlinking converter system according to one embodiment of the present disclosure.

(57) The processor 110 may apply a symmetric space vector voltage modulation method advantageous for harmonic characteristics to determine the time to apply a vector after obtaining the synthesized reference voltage V.sub.ref based on each sector area.

(58) The symmetric space vector voltage modulation method refers to a method in which the effective voltage vector exists in the center of one period after modulation and a zero voltage vector is applied before and after the effective voltage vector for d.sub.0/2 hours. Using the method, the processor 110 may determine the application times of the voltage vectors based on a combination of six effective voltage vectors and two zero voltage vectors selected in the occurrence of a line-to-line short circuit.

(59) Symmetric space vector voltage modulation method (Symmetric SVPWM) is called so because an effective voltage vector is located in the center of a switching period, which is advantageous for harmonic characteristics, and an on-sequence and an off-sequence are symmetric to each other.

(60) In other words, the symmetric space vector voltage modulation method, to place the effective vector in the center of the switching period, divides a zero vector by ½ over the sampling period and puts the divided zero vector on both sides of the switching period. For a zero vector located in the middle of the switching period, the method places V.sub.16 that turns on all switches. As a result, the processor 110 turns on the switches by applying vectors in the order of V.sub.1, V.sub.9, V.sub.13, and V.sub.16 for the first sampling period using a minimum number of switches. The processor 110 turns off the switches by applying the vectors V.sub.16, V.sub.13, V.sub.9, and V.sub.1 in the reverse order for the second sampling period.

(61) Referring to FIG. 6A, the figure shows a switch operation using the symmetric SVPWM for each sector in the case of a U-V line-to-line short circuit. Referring to FIG. 6B, the figure shows a switch operation using the symmetric SVPWM for each sector in the case of a U-W line-to-line short circuit. Referring to FIG. 6C, the figure shows a switch operation using the symmetric SVPWM for each sector in the case of a V-W line-to-line short circuit.

(62) FIGS. 7A to 7D illustrate d-q-o transform of unbalanced voltage in the occurrence of a U-V line-to-line short circuit of a three-phase four wire interlinking converter system according to one embodiment of the present disclosure.

(63) Referring to FIGS. 7A to 7D, the figures show that unbalanced voltages on the U, V, and W phases controlled during fault control for applying a voltage vector between U-V lines as a zero voltage vector in the case of a U-V line-to-line short circuit and simulated waveforms during the proposed d-q-o transform.

(64) Referring to FIG. 7A, voltage waveforms on the respective U, V, and W phases may be checked in the case of a short circuit between the U-V phases.

(65) Referring to FIG. 7B, the figure shows the d-, q-, and o-axis waveforms of three phases converted through the conventional d-q-o transform in the case of a short circuit between U-V phases. The processor 110 calculates the d-, q-, and o-axis components for each phase by performing the d-q-o transform through rotational synchronization coordinate transformation of each phase. As a result, since voltage distortion exists along the q-axis and o-axis due to a short circuit between the U-V phases, it is not possible to accurately detect and track the magnitude and phase.

(66) Referring to FIG. 7C, the figure shows new d.sub.n, q.sub.n, and o.sub.n-axis waveforms obtained by performing o.sub.n-axis transform on the d-axis and q-axis in the occurrence of a short circuit between U-V phases. In other words, while the o-axis waveform persists against the application of the conventional d-q-o coordinate transformation, the o.sub.n-axis value becomes zero, and only the d.sub.n and q.sub.n waveforms remain when coordinate transformation is applied with respect to a new o.sub.n-axis plane.

(67) Equation 2 below shows that accurate detection of phase and magnitude is possible through a new o-axis transform PLL technique that may be applied when a short-circuit occurs on the load phase of the three-phase four-wire interlinking converter.

(68) $\begin{array}{cc}\left[\begin{array}{c}d\\ q\\ o\end{array}\right]=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}1& -\frac{1}{2}& -\frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& \frac{\sqrt{3}}{2}\\ \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}\end{array}\right]\left[\begin{array}{c}{V}_m\sin \omega t\\ V_m\sin \left(\omega t-\frac{2}{3}\pi \right)\\ 0\end{array}\right]& \left[\mathrm{Eq}.2\right]\end{array}$

(69) Equation 2 shows the conventional d-q-o axis transform when an unbalanced three-phase voltage is applied.

(70) $\begin{array}{cc}R=\left[\begin{array}{c}\stackrel{.fwdarw.}{V_5}\\ \stackrel{.fwdarw.}{V_5}\times \stackrel{.fwdarw.}{V_7\times }\stackrel{.fwdarw.}{V_5}\\ \stackrel{.fwdarw.}{V_5\times }\stackrel{.fwdarw.}{V_7}\end{array}\right]=\left[\begin{array}{ccc}\sqrt{\frac{2}{3}}& 0& \frac{1}{\sqrt{3}}\\ -\sqrt{\frac{1}{6}}& \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{3}}\\ -\sqrt{\frac{1}{6}}& -\frac{1}{\sqrt{2}}& \frac{1}{\sqrt{3}}\end{array}\right]& \left[\mathrm{Eq}.3\right]\end{array}$

(71) Equation 3 rotates a switching vector distorted elliptically onto a new o-axis using a rotation matrix R.

(72) $\begin{array}{cc}\left[\begin{array}{c}{d}_n\\ q_n\\ o_n\end{array}\right]=\sqrt{\frac{2}{3}}R\left[\begin{array}{c}{V}_m\sin \omega t-\frac{1}{2}{V}_m\sin \left(\omega t-\frac{2}{3}\pi \right)\\ \frac{\sqrt{3}}{2}{V}_m\sin \left(\omega t-\frac{2}{3}\pi \right)\\ \frac{1}{\sqrt{2}}{V}_m\sin \omega t+\frac{1}{\sqrt{2}}{V}_m\sin \left(\omega t-\frac{2}{3}\pi \right)\end{array}\right]& \left[\mathrm{Eq}.4\right]\end{array}$

(73) Through Eq. 4, an unbalanced voltage occurring along the existing o-axis may be removed through a new coordinate transformation on the d.sub.n-q.sub.n-o.sub.n axis, but the component on the n plane has a phase difference of 120 degrees.

(74) $\begin{array}{cc}\left[\begin{array}{c}{d}_r\\ q_r\\ o_r\end{array}\right]=\frac{2}{\sqrt{3}}\left[\begin{array}{ccc}\frac{\sqrt{3}}{2}& 0& 0\\ -\frac{1}{2}& -1& 0\\ 0& 0& \frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}{D}_N\\ Q_N\\ O_N\end{array}\right]=\left[\begin{array}{c}{V}_m\sin \omega t\\ V_m\cos \omega t\\ 0\end{array}\right]& \left[\mathrm{Eq}.5\right]\end{array}$

(75) Equation 5 may perform d.sub.r-q.sub.r-o.sub.r compensation to convert a signal having a phase difference of 120 degrees on the n plane to a signal having a phase difference of 90 degrees.

(76) Referring to FIG. 7D, the figure shows d.sub.e and q.sub.e waveforms obtained from transformation of a synchronized coordinate system. The figure shows that the d.sub.e and q.sub.e values are kept to be constant during the synchronized coordinate transformation and when the voltage on the d.sub.e-axis is controlled to be zero, the q.sub.e value becomes the magnitude of a voltage on the V and W phases not exhibiting an earth fault.

(77) FIGS. 8A to 10D illustrate fault control of an interlinking converter in the occurrence of a line-to-line short circuit of an interlinking converter system according to one embodiment of the present disclosure.

(78) FIGS. 8A to 10D show SVPWM waveforms during fault control, where FIGS. 8A to 8D assumes a case of a U-W line-to-line short circuit; FIGS. 9A to 9D, a V-W line-to-line short circuit; and FIGS. 10A to 10D, a W-U line-to-line short circuit. At this time, FIGS. 8A to 10D illustrate voltage control waveforms of an interlinking converter generated in the occurrence of a line-to-line short circuit.

(79) Referring to FIGS. 8A to 8D, in the occurrence of a U-V line-to-line short circuit, FIG. 8A shows the respective three-phase voltages, FIG. 8B three-phase output currents, FIG. 8C d-axis and q-axis voltage vectors for performing SVPWM, and FIG. 8D an SVPWM sector according to a position of the voltage vector.

(80) Referring to FIGS. 9A to 9D, in the occurrence of a V-W line-to-line short circuit, FIG. 9A shows the respective three-phase voltages, FIG. 9B three-phase output currents, FIG. 9C d-axis and q-axis voltage vectors for performing SVPWM, and FIG. 9D an SVPWM sector according to a position of the voltage vector.

(81) Referring to FIGS. 10A to 10D, in the occurrence of a W-U line-to-line short circuit, FIG. 10A shows the respective three-phase voltages, FIG. 10B three-phase output currents, FIG. 10C d-axis and q-axis voltage vectors for performing SVPWM, and FIG. 10D an SVPWM sector according to a position of the voltage vector.

(82) As a result of performing the method for controlling a fault of an interlinking converter according to some embodiments of the present specification, it may be confirmed that a zero voltage vector is applied to the lines between which a short circuit occurs, and a phase voltage of 220 V.sub.rms is normally controlled for each phase voltage. Therefore, the method may electrically isolate only the point where the short circuit has occurred and at the same time, supply each phase voltage normally.

(83) FIG. 11 illustrates d-, q-axis voltage vectors for controlling a fault in the occurrence of a U-V line-to-line short circuit of an interlinking converter according to one embodiment of the present disclosure.

(84) Referring to FIG. 11, as described with reference to the equations above, it may be confirmed that as a result of transforming an unbalanced voltage vector onto the n plane comprising d- and q-axis, a reference voltage vector waveform having a phase difference of 120 degrees is generated.

(85) FIG. 12 illustrates switching duty on the U, V, W, N phase in the occurrence of a U-V line-to-line short circuit of an interlinking converter according to one embodiment of the present disclosure.

(86) Referring to FIG. 12, it may be confirmed that through fault control, an interlinking converter applies a zero voltage vector to the lines between which a short circuit occurs, applies a normal voltage to the respective phases to which a load is connected, and checks the switching duty of each phase after performing SVPWM on the voltage vectors.

(87) FIGS. 13A and 13B illustrate output phase voltages and line-to-line voltage waveforms of an interlinking converter when SVPWM is performed using the switching duty of FIG. 12.

(88) Referring to FIG. 13A, the U and V phase output in-phase 128 V rated voltage while W phase outputs 128V voltage having a phase difference of 240 degrees.

(89) Referring to FIG. 13B, since the U-V line-to-line voltage is short-circuited, a zero voltage is produced by application of a zero voltage vector.

(90) Therefore, the short-circuit section may be electrically cut off with a zero voltage, normal AC voltage is supplied to all of the U, V, and W phases for household power using the respective phase loads, and thereby, only the fault sector may be separated. In particular, the proposed method for controlling a fault may supply power to all phases in the case of a line-to-line short circuit, and at the same time, may separate the fault sector. Compared to a secure cooperation method using the existing circuit breaker, the fault sector may be quickly separated by changing the switching method. In the case of a small microgrid using phase loads, power may be supplied smoothly.

(91) The present disclosure may be implemented in the form of computer-readable code in a recording medium storing programs. The computer-readable recording medium includes all kinds of recording devices storing data that may be read by a computer system. Examples of a computer-readable recording medium include a Hard Disk Drive (HDD), a Solid State Disk (SSD), a Silicon Disk Drive (SDD), a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and implementation in the form of carrier waves (for example, transmission through the Internet). Therefore, the detailed descriptions above should be regarded as being illustrative rather than restrictive in every aspect. The technical scope of the present disclosure should be determined by a reasonable interpretation of the appended claims, and all of the modifications that fall within an equivalent scope of the present disclosure belong to the technical scope of the present disclosure.