CUSTOM CAPACITIVE DAC WITH ON CHIP AUTOCALIBRATION FOR HIGH RESOLUTION SUCCESSIVE APPROXIMATION REGISTER ADC

Abstract

Disclosed herein is a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a capacitive digital-to-analog converter (DAC) including a binary-weighted capacitor array, and a bridge capacitor separating the binary-weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node, with a first terminal of the bridge capacitor being connected to the first node and a second terminal of the bridge capacitor being connected to the second node. A multipurpose capacitor is connected to the first node, with the multipurpose capacitor serving as both a termination capacitor for the first switched capacitor array and a shield between the first node and the bridge capacitor. A dummy is capacitor connected to the second node and serving as a shield between the second node and the bridge capacitor.

Claims

1. A successive approximation register (SAR) analog-to-digital converter (ADC) comprising: a capacitive digital-to-analog converter (DAC) including a binary-weighted capacitor array; a bridge capacitor separating the binary-weighted capacitor array into a first switched capacitor array connected to a first nodeand a second switched capacitor array connected to a second node, with a first terminal of the bridge capacitor being connected to the first node and a second terminal of the bridge capacitor being connected to the second node; and a multipurpose capacitor connected to the first node, wherein the multipurpose capacitor serves as both a termination capacitor for the first switched capacitor array and a shield between the first node and the bridge capacitor; and a dummy capacitor connected to the second node and serving as a shield between the second node and the bridge capacitor.

2. The SAR ADC of claim 1, wherein the capacitive DAC comprises metal layers, and wherein: the multipurpose capacitor is formed by plates in second, third, fourth, fifth, and sixth ones of the metal layers; the bridge capacitor is formed by plates in the second, third, fourth, fifth, and sixth ones of the metal layers; and the plates of the multipurpose capacitor and the bridge capacitor in the fifth and third metal layers are connected to one another.

3. The SAR ADC of claim 2, wherein: upper plates of the bridge capacitor and the dummy capacitor are connected by a horizontal plate in the sixth metal layer; and the dummy capacitor includes a horizontal plate in the fifth metal layer connected to the horizontal plate thereof in the sixth metal layer through a vertical line.

4. The SAR ADC of claim 3, wherein: the dummy capacitor is connected to a first capacitor of the second switched capacitor array; and a horizontal plate in the fifth metal layer of the dummy capacitor is connected to a corresponding horizontal plate in the fifth metal layer of the first capacitor.

5. The SAR ADC of claim 1, wherein the capacitive DAC comprises a layout in which the bridge capacitor is centrally located, the multipurpose capacitor is positioned adjacent to a first side of the bridge capacitor, the dummy capacitor is positioned adjacent to a second side of the bridge capacitor, and the first and second switched capacitor arrays are positioned on either side of the centrally located bridge capacitor.

6. The SAR ADC of claim 5, wherein the layout further comprises: a tunnel created within a column containing the dummy capacitor; and a vertical metal line running through the tunnel to connect upper plates of capacitors across different columns of the binary-weighted capacitor array.

7. The SAR ADC of claim 6, wherein: the vertical metal line is formed in the fifth metal layer; and the tunnel provides isolation between the vertical metal line and plates of capacitors.

8. The SAR ADC of claim 5, wherein: each of the first and second switched capacitor arrays comprises multiple columns of capacitor elements; each column of capacitor elements is formed of a plurality of unit capacitors; and columns representing more significant bits comprise a larger number of unit capacitors compared to columns representing less significant bits.

9. The SAR ADC of claim 1, wherein the capacitive DAC comprises multiple metal layers, and wherein: the multipurpose capacitor is formed by conductive structures in at least three of the metal layers; the bridge capacitor is formed by conductive structures in at least three of the metal layers; and at least two of the conductive structures of the multipurpose capacitor and the bridge capacitor in non-adjacent metal layers are electrically connected to one another.

10. The SAR ADC of claim 9, wherein: upper conductive structures of the bridge capacitor and the dummy capacitor are electrically connected in an uppermost metal layer of the multiple metal layers; and the dummy capacitor includes a conductive structure in a metal layer below the uppermost metal layer, the conductive structure being electrically connected to the upper conductive structure through a vertical conductive element.

11. The SAR ADC of claim 10, wherein: the dummy capacitor is electrically connected to a first capacitor of the second switched capacitor array; and a conductive structure of the dummy capacitor in a metal layer below the uppermost metal layer is electrically connected to a corresponding conductive structure of the first capacitor in the same metal layer.

12. The SAR ADC of claim 1, further comprising: a first calibration DAC connected to the first node; a second calibration DAC connected to the second node; and auto-calibration logic configured to control the first and second calibration DACs to inject error correction signals during analog-to-digital conversion.

13. The SAR ADC of claim 12, wherein the auto-calibration logic is configured to: evaluate capacitance errors for a plurality of most significant capacitors in the binary-weighted capacitor array; and generate calibration coefficients based on the evaluated capacitance errors.

14. The SAR ADC of claim 13, wherein evaluating the capacitance errors comprises: sequentially testing each of the plurality of most significant capacitors; taking N readings for each tested capacitor, where N is a positive integer; and calculating an error value for each tested capacitor based on the N readings.

15. The SAR ADC of claim 14, further comprising: registers configured to store the generated calibration coefficients; and wherein the auto-calibration logic is further configured to apply the stored calibration coefficients as static corrections during subsequent analog-to-digital conversions.

16. The SAR ADC of claim 12, further comprising an ADC phase control circuit configured to: enable the auto-calibration logic to perform calibration when the SAR ADC switches from an idle state to an operative state; and manage a sequence of calibration phases for evaluating errors in the most significant capacitors of the binary-weighted capacitor array.

17. The SAR ADC of claim 13, wherein the plurality of most significant capacitors comprises the nine most significant capacitors in the binary-weighted capacitor array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG. 1 illustrates a prior art SAR ADC design, showing the basic structure with separate dummy capacitor columns for shielding.

[0040] FIG. 2 provides a top-down schematic view of the capacitor array layout in the prior art capacitive DAC of FIG. 1, demonstrating the arrangement of active and dummy capacitors.

[0041] FIG. 3 depicts a cross-sectional view of the prior art capacitor layout of FIG. 1, highlighting the metal layer arrangement and parasitic capacitances.

[0042] FIG. 4 presents the improved SAR ADC design disclosed herein, using a capacitor as both a termination capacitor and a shield, eliminating the need for separate dummy columns.

[0043] FIG. 5 shows the metal layer arrangement of the improved design of FIG. 4, illustrating how the interconnection scheme reduces parasitic capacitances.

[0044] FIG. 6 offers a top view of the capacitor layout in the design of FIG. 4, showing the modified dummy column that creates a tunnel for the M5 vertical line, improving linearity.

[0045] FIG. 7 illustrates a block diagram of a complete ADC system, including the ADC disclosed herein and the digital blocks necessary for implementing a self-calibration technique disclosed herein.

[0046] FIG. 8 is a schematic diagram of the ADC including calibration functionality, showing the main DACs and the calibration DACs.

[0047] FIG. 9 is a timing diagram illustrating the calibration workflow managed by the ADC phase control block, showing the sequence of calibration phases.

[0048] FIG. 10 shows the drive signals for both the positive and negative arrays during the calibration phase for evaluating the C16 capacitance error.

[0049] FIG. 11 illustrates the drive signals for the positive and negative arrays during the calibration phase for evaluating the C15 capacitance error.

[0050] FIG. 12 depicts the drive signals for the positive and negative arrays during the calibration phase for evaluating the C14 capacitance error.

[0051] FIG. 13 shows the drive signals for the positive and negative arrays during the calibration phase for evaluating the C9 capacitance error.

[0052] FIG. 14 illustrates the drive signals for the positive and negative arrays during the calibration phase for evaluating the C8 capacitance error.

DETAILED DESCRIPTION

[0053] The following disclosure enables a person skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. It is not intended to limit this disclosure to the embodiments shown, but to accord it the widest scope consistent with the principles and features disclosed or suggested herein.

[0054] Note that in the following description, any resistor or resistance mentioned is a discrete device, unless stated otherwise, and is not simply an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than a lead between those two points, and such resistor or resistance cannot be interpreted as a lead. Similarly, any capacitor or capacitance mentioned is a discrete device, unless stated otherwise, and is not a parasitic element, unless stated otherwise. Additionally, any inductor or inductance mentioned is a discrete device, unless stated otherwise, and is not a parasitic element, unless stated otherwise.

[0055] Now described with reference to FIG. 4 is a SAR ADC 10 that addresses the previously mentioned drawbacks of the design of FIGS. 2-3. The SAR ADC 10 comprises a fully differential architecture with two identical capacitive DACs, each connected to one input of a differential comparator 11. The SAR ADC 10 also includes SAR logic 16, similar to the described prior art designs. However, the capacitive DACs 13 and 33 in the SAR ADC 10 incorporates modifications to enhance performance and reduce area consumption.

[0056] Each capacitive DAC (13 and 33) includes a left-half node (Nl+ and Nl respectively) and a right-half node (Nr+ and Nr respectively), separated from each other and electrically coupled by a bridge capacitor Cub. The right-half nodes Nr+ and Nr are connected to the non-inverting and inverting inputs of the comparator 11, respectively.

[0057] The DAC 13 comprises two sets of switched capacitor circuits: 15(1) to 15(m) connected to Nr+, and 14(1) to 14(k) connected to node Nl+. Likewise, the capacitive DAC 33 comprises two sets of switched capacitor circuit: 35(1) to 35(m) connected to Nr, and 34(1) to 34(k) connected to Nl.

[0058] Each of these circuits contains either a unit capacitor Cu or multiples thereof (kCu or mCu), which can be switched between a reference voltage Vref and ground based on the control signals from the SAR logic 16. In greater detail, the multiples may be in multiples of two; for example, if k=5, then the capacitor for 14(1) or 34(1) would have a capacitance of Cu, the capacitor for 14(2) or 34(2) would have a capacitance of 2Cu, the capacitor for 14(3) or 34(3) would have a capacitance of 4Cu, the capacitor for 14(4) or 34(4) would have a capacitance of 8Cu, and the capacitor for 14(k=5) or 34(k=5) would have a capacitance of 16Cu. Likewise, for m=5, then the capacitor for 15(1) or 35(1) would have a capacitance of Cu, the capacitor for 15(2) or 35(2) would have a capacitance of 2Cu, the capacitor for 15(3) or 35(3) would have a capacitance of 4Cu, the capacitor for 15(4) or 35(4) would have a capacitance of 8Cu, and the capacitor for 15(m=5) or 35(m=5) would have a capacitance of 16Cu.

[0059] Notable in this design is the use of capacitor Cu2 at the left-half node Nl+ of the capacitive DAC 13 and the use of capacitor Cu2 at the left-half node Nl of the capacitive DAC 33. Unlike in FIG. 1, where no such capacitor is present, these capacitors Cu2 in FIG. 4 serve multiple important functionsit can be considered a multipurpose capacitor. First, the form part of the binary-weighted capacitor arrays 14(1), . . . , 14(k) and 34(1), . . . , 34(k). In addition, these capacitors Cu2 act as ground-connected termination capacitors, they function as shields between the nodes Nl+, Nl and the bridge capacitor Cub.

[0060] This multi-functional approach of capacitors Cu2 allows for the elimination of the separate dummy capacitor column (Cdl in FIG. 1) while still maintaining the necessary shielding effect. In the prior art design of FIG. 1, dummy capacitor column Cdl served solely as a shielding element, occupying valuable chip area. By repurposing capacitor Cu2, an existing and necessary component of the binary-weighted DAC structure, to also serve as a shield, the new design achieves improved area efficiency without compromising functionality.

[0061] At the right-side nodes Nr+, Nr single dummy capacitors Cdum are retained in each DAC, similar to the prior art design showing capacitor Cdr. These dummy capacitors ensure proper shielding for the right side of the bridge capacitors Cub and maintain symmetry in the overall DAC structures.

[0062] This configuration effectively addresses the parasitic coupling issues while significantly reducing the overall area of the DACs compared to the prior art design in FIG. 1. By eliminating the need for separate dummy columns on both sides of the bridge capacitor (as seen with dummy capacitor columns Cdl and Cdr in FIGS. 1-3), this design achieves considerable area savings, particularly in this fully differential ADC with separate DACs for inverting and non-inverting signal paths.

[0063] FIG. 5 illustrates the metal layer arrangement of the improved design. Cu2 is repurposed from the binary-weighted capacitor array to also function as a shield. The most significant bit capacitor 14(k) is not explicitly shown in this figure. The interconnection scheme has been optimized to reduce parasitic capacitances. The lower plates of the capacitors are connected primarily by vertical metal lines in the sixth metal layer M6, while the upper plates are connected by horizontal lines in metal layer M3 and M5. This arrangement minimizes the overlap between different metal layers, thereby reducing unwanted parasitic capacitances.

[0064] This approach achieves the same shielding effect as the previous design, with the parasitic capacitances Cp4 and Cp5 still referred to a fixed potential. Consequently, the switching of capacitances to the right and left of the bridge capacitor does not induce undesired voltage fluctuations on the floating electrodes. The result is a more area-efficient design that maintains the linearity and performance benefits of the previous approach.

[0065] By eliminating the need for multiple dummy columns (four in the case of a fully differential ADC with separate DACs for the main conversion and mismatch calibration), this design achieves considerable area savings. The dual use of capacitor Cu2 as a shield reduces the capacitor count without compromising functionality or the binary-weighted structure of the DACs 13 and 33. The retention of capacitor Cdum on the right side provides for balanced operation while minimizing additional area requirements.

[0066] This reduction in area not only improves the overall efficiency of the ADC 10 but also potentially reduces manufacturing costs and power consumption, making it particularly suitable for high-resolution applications where space and power are at a premium.

[0067] FIG. 6 provides a top-down view of the 3D structure that FIG. 5 shows in cross section top view of the capacitor layout of the DACs 13 and 33, showcasing the compact arrangement of the capacitor elements of the DAC 13 and 33; stated another way, FIG. 5 shows a cross sectional view of FIG. 6 taken along line A-A. The bridge capacitor Cub is shown in the center, flanked by the termination capacitor Cu2 on the left and the dummy capacitor Cdum on the right. The active switched capacitor arrays are positioned on either side of this central structure.

[0068] This design addresses the problem of parasitic paths as follows. The horizontal lines of M5 and M3, which form the upper plates of the capacitors and are shorted to each other, connect the upper part of each unitary element. These do not pair with the vertical lines of M6 and M4, which form the lower plates of the capacitors (also shorted) and connect the lower parts of the elements in the same column. By eliminating vertical M5/M3 lines running alongside M6, this arrangement significantly reduces parasitic couplings compared to the prior art design described in the background.

[0069] The reduction in parasitic couplings offers several advantages. It allows for lower power consumption in the drivers and reduces mismatches between various parasitic elements. By decreasing the absolute value of these parasitic elements, their contribution to mismatch due to technology variations is proportionally reduced, even with the same level of process mismatch.

[0070] A single vertical line of M5 is used to connect the top of elements across different columns.

[0071] As shown in FIG. 6, a tunnel is created within the dummy column for the M5 vertical line to run through. This helps ensure that the M5 line no longer runs adjacent to the bottom of the capacitance column tied to capacitor mCu.

[0072] In the DACs 13 and 33, a column tied to capacitor mCu is formed of 8 elements of, for example, 40 fF each, for a total expected capacitance of for example 320 fF. As a result, the capacitance values of all MSB columns are consistent, improving the linearity of the DAC.

[0073] FIG. 7 illustrates a block diagram of the ADC system designed for use in medical applications desiring low-power, high-resolution analog-to-digital conversion. The ADC system is divided into two main blocks: the ADC 10 and the digital block 20.

[0074] The ADC 10 represents the analog-to-digital converter described above. It contains the SAR logic 16, which implements the successive approximation register algorithm used the operation of the ADC 10. The SAR logic 16 controls the conversion process and interacts with other parts of the system. The ADC 10 outputs two signals: ADC_D<16:1>, which is the 16-bit digital output representing the converted analog input, and ADC_EOC, indicating the end of conversion when the ADC 10 completes a conversion cycle.

[0075] The digital block 20 includes the digital control and processing elements used for the ADC operation and calibration. Within this digital block 20, the ADC Phase Control 21 manages the overall operation of the ADC. It generates several control signals: ADC_EN to enable or disable the ADC 10, ADC_START to initiate a conversion cycle, and ADC_TEST_CAPS used for testing the capacitors in the ADC 10 as part of the calibration process. The ADC Phase Control 21 also generates ADC_CAL_On to enable the auto-cal logic 18. The digital block 20 also includes registers 22 that store calibration coefficients and other data for the operation of the ADC. These registers 22 are updated during a self-calibration process described hereinbelow to correct for non-linearity errors in the ADC 10.

[0076] The digital block 20 receives the ADC_D<16:1> and ADC_EOC signals from the ADC 10, using them for processing and coordinating the operation of the ADC 10. The digital block 20 outputs the DAC_ERR_Cx signal, which represents the calibration coefficients sent to the ADC 10 to correct for nonlinearity errors in the capacitive DACs 13 and 33. To achieve the high level of linearity required for a high Effective Number of Bits (ENOB), such as 14-bits, an Auto-Calibration technique described hereinbelow has been implemented. This technique compensates for both DAC and comparator non-linearity, enabling the ADC to achieve an ENOB of up to 14 bits.

[0077] The Auto-Calibration process evaluates the calibration coefficients, which are then stored in the registers 22. This calibration is performed automatically each time the device switches from the idle state to the operative state. By doing so, the system corrects for aging effects and slow temperature variations without the need for manual intervention or increased testing time. This approach not only maintains the ADC's high performance over time but also keeps operational costs low by eliminating the need for frequent manual calibrations.

[0078] By incorporating this self-calibration mechanism, the ADC 10 can achieve the desired Signal-to-Noise and Distortion Ratio (SNDR) for high-resolution performance, overcoming the limitations of relying solely on accurate capacitive DAC layout. This design approach is particularly suitable for medical applications that demand both low power consumption and high resolution in analog-to-digital conversion. The ability to automatically compensate for various factors that could degrade performance over time makes this ADC system especially valuable in medical devices where consistent, high-accuracy measurements are desired.

[0079] An example implementation of the ADC 10 including calibration functionality is now described with reference to FIG. 8. The ADC 10 comprises a fully differential architecture with four capacitive DACs: main DACs 13, 33 and two calibration DACs 43 and 53.

[0080] The first main DAC 13 includes a left-half node Nl+ and a right-half node Nr+, separated from each other and electrically coupled by a bridge capacitor Cu. The right-half node Nr+ is connected to the non-inverting input of the comparator. A first set of switched capacitor circuits 14(1) to 14(7) is connected to Nl+ and a second set of switched capacitor circuits 15(8) to 15(16) is connected to Nr+. Each of these circuits contains a binary-weighted capacitor array, with capacitances in 14(1) to 14(7) ranging from Cu to 64Cu, and with capacitances in 15(8) to 15(16) ranging from Cu to 128Cu. Each capacitor in switched capacitor circuits 14(1) to 14(7) can be switched between being connected to a common mode voltage Vcm, a reference voltage Vref, and ground. Each capacitor in switched capacitor circuits 15(1) to 15(7) can be switched between being connected to a common mode voltage Vcm, a reference voltage Vref, ground, and the input voltage Vin.

[0081] The second main DAC 33 includes a left-half node Nl- and a right-half node Nr, separated from each other and electrically coupled by a bridge capacitor Cu. The right-half node Nr is connected to the inverting input of the comparator. A first set of switched capacitor circuits 34(1) to 34(7) is connected to Nl and a second set of switched capacitor circuits 35(8) to 35(16) is connected to Nr. Each of these circuits contains a binary-weighted capacitor array, with capacitances in 34(1) to 34(7) ranging from Cu to 64Cu, and with capacitances in 35(8) to 35(16) ranging from Cu to 128Cu. Each capacitor in switched capacitor circuits 34(1) to 34(7) can be switched between being connected to a common mode voltage Vcm, a reference voltage Vref, and ground. Each capacitor in switched capacitor circuits 35(1) to 35(7) can be switched between being connected to a common mode voltage Vcm, a reference voltage Vref, ground, and the input voltage Vin.

[0082] The first calibration DAC 43 is connected to node Nc+, and includes a series of switched capacitor circuits 16(1) to 16(7), with capacitances ranging from Cu/2 to 16Cu. A termination capacitor having a capacitance of 32Cu is connected between node Nc+ and ground. An additional capacitor Cu/4 is connected between node Nc+ and node Nr+. Each capacitor in the capacitor circuits 16(1) to 16(7) can be switched between a reference voltage Vref and ground.

[0083] The second calibration DAC 53 is connected to node Nc, and includes a series of switched capacitor circuits 36(1) to 36(7), with capacitances ranging from Cu/2 to 16Cu. A termination capacitor having a capacitance of 32Cu is connected between node Nc and ground. An additional capacitor Cu/4 is connected between node Nc and node Nr. Each capacitor in the capacitor circuits 36(1) to 36(7) can be switched between a reference voltage Vref and ground.

[0084] The ADC 10 also includes a comparator 11 that receives inputs from the right-half nodes Nr+ and Nr of the main DACs 13 and 33. The output of the comparator 11 feeds into the SAR logic 17, which generates control signals for the switched capacitor circuits in the main DACs 13 and 33. An Auto-Cal Logic block 18 also receives the output of the comparator 11 and generated control signals for the switched capacitor circuits in the calibration DACs 43 and 53.

[0085] The calibration workflow will now be described, but first note that the following notations will be used.

[0086] In the main DAC 13, the capacitor in 14(1) will be referred to as capacitor C1p (having a capacitance of Cu), the capacitor in 14(2) will be referred to as capacitor C2p (having a capacitance of 2Cu), the capacitor in 14(3) will be referred to as capacitor C3p (having a capacitance of 4Cu), the capacitor in 14(4) will be referred to as capacitor C4p (having a capacitance of 8Cu), the capacitor in 14(5) will be referred to as capacitor C5p (having a capacitance of 16Cu), the capacitor in 14(6) will be referred to as capacitor C6p (having a capacitance of 32Cu), the capacitor in 14(7) will be referred to as capacitor C7p (having a capacitance of 64Cu), the capacitor in 15(8) will be referred to as capacitor C8p (having a capacitance of Cu), the capacitor in 15(9) will be referred to as capacitor C9p (having a capacitance of Cu), the capacitor in 15(10) will be referred to as capacitor C10p (having a capacitance of 2Cu), the capacitor in 15(11) will be referred to as capacitor Clip (having a capacitance of 4Cu), the capacitor in 15(12) will be referred to as capacitor C12p (having a capacitance of 8Cu), the capacitor in 15(13) will be referred to as capacitor C13p (having a capacitance of 16Cu), the capacitor in 15(14) will be referred to as capacitor C14p (having a capacitance of 32Cu), the capacitor in 15(15) will be referred to as capacitor C15p (having a capacitance of 64Cu), and the capacitor in 15(16) will be referred to as capacitor C16p (having a capacitance of 128Cu).

[0087] In the main DAC 33, the capacitor in 34(1) will be referred to as capacitor C1n (having a capacitance of Cu), the capacitor in 34(2) will be referred to as capacitor C2n (having a capacitance of 2Cu), the capacitor in 34(3) will be referred to as capacitor C3n (having a capacitance of 4Cu), the capacitor in 34(4) will be referred to as capacitor C4n (having a capacitance of 8Cu), the capacitor in 34(5) will be referred to as capacitor C5n (having a capacitance of 16Cu), the capacitor in 34(6) will be referred to as capacitor C6n (having a capacitance of 32Cu), the capacitor in 34(7) will be referred to as capacitor C7n (having a capacitance of 64Cu), the capacitor in 35(8) will be referred to as capacitor C8n (having a capacitance of Cu), the capacitor in 35(9) will be referred to as capacitor C9n (having a capacitance of Cu), the capacitor in 35(10) will be referred to as capacitor C10n (having a capacitance of 2Cu), the capacitor in 35(11) will be referred to as capacitor C11n (having a capacitance of 4Cu), the capacitor in 35(12) will be referred to as capacitor C12n (having a capacitance of 8Cu), the capacitor in 35(13) will be referred to as capacitor C13n (having a capacitance of 16Cu), the capacitor in 35(14) will be referred to as capacitor C14n (having a capacitance of 32Cu), the capacitor in 35(15) will be referred to as capacitor C15n (having a capacitance of 64Cu), and the capacitor in 35(16) will be referred to as capacitor C16n (having a capacitance of 128Cu).

[0088] The calibration workflow is managed by the ADC phase control block 21 (see FIG. 7), which enables the SAR logic 17 and auto-cal logic 18 in specific phases, as illustrated in the timing diagram of FIG. 9. The calibration process focuses on evaluating and correcting errors in the most significant capacitances, namely C16p to C8p in the positive array (DAC 13) and C16n to C8n in the negative array (DAC 33), as these have the greatest impact on nonlinearity errors.

[0089] After calibration is enabled, the error evaluation proceeds through a series of phases: ADC_TEST_CAP<16>, ADC_TEST_CAP<15>, ADC_TEST_CAP<14>, ADC_TEST_CAP<13>, ADC_TEST_CAP<12>, ADC_TEST_CAP<11>, ADC_TEST_CAP<10>, ADC_TEST_CAP<9>, and ADC_TEST_CAP<8>. During each of these phases, N readings (for example, N=8) are taken for the respective capacitance being evaluated.

[0090] The behavior of voltages across the capacitors in both the positive and negative arrays during these calibration phases is illustrated in FIGS. 10 through 14. These figures show the trend of voltages V_C1_p to V_C16_p across capacitors C1p to C16p in the positive array, and voltages V_C1_n to V_C16_n across capacitors C1n to C16n in the negative array.

[0091] FIG. 10 depicts the evaluation of the C16 capacitance error. It shows the drive signals for both the positive array (left) and negative array (right) during the calibration phase ADC_TEST_CAP<16>. Likewise, FIG. 11 shows the evaluation of the C15 capacitance error, showing the drive signals for the positive array (left) and negative array (right) during the calibration phase ADC_TEST_CAP<15>. Additionally, FIG. 12 shows the evaluation of the C14 capacitance error, showing the drive signals for the positive array (left) and negative array (right) during the calibration phase ADC_TEST_CAP<14>. Moreover, FIG. 13 shows the evaluation of the C9 capacitance error, presenting the drive signals for the positive array (left) and negative array (right) during the calibration phase ADC_TEST_CAP<9>. Furthermore, FIG. 14 shows the evaluation of the C8 capacitance error, showing the drive signals for the positive array (left) and negative array (right) during the calibration phase ADC_TEST_CAP<8>.

[0092] Driving the capacitances according to the waveforms shown in FIGS. 10-14, the equations showing the evaluation of the error are as follows:

[00003]${\mathrm{DCAL}}_{C16}-\frac{\left(\left(C16p+C16n\right)-\left(C15p+C15n\right)-\left(C14p+C14n\right)-\left(C13p+C13n\right)-\left(C12p+C12n\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}-\frac{\left(-\left(C11p+C11n\right)-\left(C10p+C10n\right)-\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$${\mathrm{DCAL}}_{C15}-\frac{\left(\left(C15p+C15n\right)-\left(C14p+C14n\right)-\left(C13p+C13n\right)-\left(C12p+C12n\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}-\frac{\left(-\left(C11p+C11n\right)-\left(C10p+C10n\right)-\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$$\frac{\left(\left(C14p+C14n\right)-\left(C13p+C13n\right)-\left(C12p+C12n\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}-\frac{\left(-\left(C11p+C11n\right)-\left(C10p+C10n\right)-\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$${\mathrm{DCAL}}_{C13}-\frac{\left(\left(C13p+C13n\right)-\left(C12p+C12n\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}-\frac{\left(-\left(C11p+C11n\right)-\left(C10p+C10n\right)-\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$${\mathrm{DCAL}}_{C14}-$${\mathrm{DCAL}}_{C12}-\frac{\left(\left(C12p+C12n\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}-\frac{\left(\left(C11p+C11n\right)-\left(C10p+C10n\right)-\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$${\mathrm{DCAL}}_{C11}-\frac{\left(\left(C11p+C11n\right)-\left(C10p+C10n\right)-\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$${\mathrm{DCAL}}_{C10}-\frac{\left(\left(C10p+C10n\right)-\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$${\mathrm{DCAL}}_{C9}-\frac{\left(\left(C9p+C9n\right)-C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$${\mathrm{DCAL}}_{C8}-\frac{\left(C8p-\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$$\mathrm{where}:$$\begin{array}{c}\left(C16p+C15p+C14p+C13p+C12p+C11p+C10p+C9p+C8p\right)+\mathrm{Cu}+\mathrm{Ccomp},p\\ \left(C16n+C15n+C14n+C13n+C12n+C11n+C10n+C9n+C8n\right)+\mathrm{Cu}+\mathrm{Ccomp},n\\ {\mathrm{CDAC}}_{\mathrm{Upper}}\end{array}$$C7p,\mathrm{eq}\frac{\left(\left(1/2\mathrm{Cu}\right).Math.\mathrm{Vref}\right)}{\left(C16p+C15p+C14p+C13p+C12p+C11p+C10p+C9p+C8p\right)+\mathrm{Cu}+\mathrm{Ccomp},p}$$C7n,\mathrm{eq}\frac{\left(-\left(1/2\mathrm{Cu}\right).Math.\mathrm{Vref}\right)}{\left(C16n+C15n+C14n+C13n+C12n+C11n+C10n+C9n+C8n\right)+\mathrm{Cu}+\mathrm{Ccomp},n}$$C7p,\mathrm{eq}C7n,\mathrm{eq}1/2\mathrm{Cu}$

[0093] A specific example will now be provided. Suppose the following errors are to be calibrated: (C16p+C16n)=128Cu+128Cu+2.Math.C=256Cu+2.Math.C

[00004]$\left(C15p+C15n\right)=64\mathrm{Cu}+64\mathrm{Cu}-1.Math.C=128\mathrm{Cu}-1.Math.C$$\left(C14p+C14n\right)=32\mathrm{Cu}+32\mathrm{Cu}+0.Math.C=64\mathrm{Cu}+0.Math.C$$\left(C13p+C13n\right)=16\mathrm{Cu}+16\mathrm{Cu}+1.Math.C=32\mathrm{Cu}+1.Math.C$$\left(C12p+C12n\right)=8\mathrm{Cu}+8\mathrm{Cu}-1.Math.C=16\mathrm{Cu}-1.Math.C$$\left(C11p+C11n\right)=4\mathrm{Cu}+4\mathrm{Cu}-2.Math.C=8\mathrm{Cu}-2.Math.C$$\left(C10p+C10n\right)=2\mathrm{Cu}+2\mathrm{Cu}-3.Math.C=4\mathrm{Cu}-3.Math.C$$\left(C9p+C9n\right)=1\mathrm{Cu}+1\mathrm{Cu}+1.Math.C=2\mathrm{Cu}+1.Math.C$$C8p=1\mathrm{Cu}+2.Math.C$$\left(C7p,\mathrm{eq}+C7n,\mathrm{eq}\right)=1\mathrm{Cu}+0.Math.C$

[0094] The calibration values DCAL resulting from the calibration then become:

[00005]$\mathrm{DCAL},C16=-\frac{(\left(2-\left(-1+0+2-1-2-3+1+2+0\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(-4.Math.C\right)$$\mathrm{DCAL},C15=-\frac{\left(\left(-1-\left(0+2-1-2-3+1+2+0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(0.Math.C\right)$$\begin{array}{c}\mathrm{DCAL},C14=-\frac{\left(\left(0-\left(2-1-2-3+1+2+0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(-1.Math.C\right)\mathrm{DCAL},C13\\ =-\frac{\left(\left(2-\left(-1-2-3+1+2+0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(-5.Math.C\right)\mathrm{DCAL},C12\\ =-\frac{\left(\left(-1-\left(-2-3+1+2+0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(-1.Math.C\right)\end{array}$$\mathrm{DCAL},C11=-\frac{\left(\left(-2-\left(-3+1+2+0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(2.Math.C\right)$$\mathrm{DCAL},C10=-\frac{\left(\left(-3-\left(1+2+0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(6.Math.C\right)$$\mathrm{DCAL},C9=-\frac{\left(\left(1-\left(2+0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(1.Math.C\right)$$\mathrm{DCAL},C8=-\frac{\left(\left(2-\left(0\right)\right).Math.C\right).Math.\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}=\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}\left(-2.Math.C\right)$

[0095] From these DCAL values, the capacitance errors can be calculated as:

[00006]$\mathrm{DACerr\_C16}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C16\right)$$\mathrm{DACerr\_C15}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C15-\mathrm{DACerr\_C16}\right)$$\mathrm{DACerr\_C14}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C14-\mathrm{DACerr\_C15}-\mathrm{DACerr\_C16}\right)$$\mathrm{DACerr\_C13}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C13-\mathrm{DACerr\_C14}-\mathrm{DACerr\_C15}-\mathrm{DACerr\_C16}\right)$$\mathrm{DACerr\_C12}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C12-\mathrm{DACerr\_C13}-\mathrm{DACerr\_C14}-\mathrm{DACerr\_C15}-\mathrm{DACerr\_C16}\right)$$\mathrm{DACerr\_C11}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C11-\mathrm{DACerr\_C12}-\mathrm{DACerr\_C13}-\mathrm{DACerr\_C14}-\mathrm{DACerr\_C15}-\mathrm{DACerr\_C16}\right)$$\mathrm{DACerr\_C10}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C10-\mathrm{DACerr\_C11}-\mathrm{DACerr\_C12}-\mathrm{DACerr\_C13}-\mathrm{DACerr\_C14}-\mathrm{DACerr\_C15}-\mathrm{DACerr\_C16}\right)$$\mathrm{DACerr\_C9}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C9-\mathrm{DACerr\_C10}-\mathrm{DACerr\_C11}-\mathrm{DACerr\_C12}-\mathrm{DACerr\_C13}-\mathrm{DACerr\_C14}-\mathrm{DACerr\_C15}-\mathrm{DACerr\_C16}\right)$$\mathrm{DACerr\_C8}\frac{1}{2}.Math.\left(-\mathrm{DCAL},C8-\mathrm{DACerr\_C9}-\mathrm{DACerr\_C10}-\mathrm{DACerr\_C11}-\mathrm{DACerr\_C12}-\mathrm{DACerr\_C13}-\mathrm{DACerr\_C14}-\mathrm{DACerr\_C15}-\mathrm{DACerr\_C16}\right)$

[0096] Plugging in the previously calculated values of DCAL for each capacitor yields:

[00007]$\mathrm{DACerr\_C16}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(2.Math.C\right)$$\mathrm{DACerr\_C15}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(-1.Math.C\right)$$\mathrm{DACerr\_C14}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(0.Math.C\right)$$\mathrm{DACerr\_C13}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(2.Math.C\right)$$\mathrm{DACerr\_C12}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(-1.Math.C\right)$$\mathrm{DACerr\_C11}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(-2.Math.C\right)$$\mathrm{DACerr\_C10}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(-3.Math.C\right)$$\mathrm{DACerr\_C9}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(1.Math.C\right)$$\mathrm{DACerr\_C8}\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}.Math.\left(2.Math.C\right)$

[0097] The results of the calibration process aligns with the unknowns that were intended to be estimated. These results demonstrate that the calibration process successfully estimates the errors of the DAC capacitances. The equations for DACerr_C8 through DACerr_C16 show how the error of each capacitor is quantified in terms of

[00008]$\frac{\mathrm{Vref}}{{\mathrm{CDAC}}_{\mathrm{Upper}}}$ and C.

[0098] In the implementation, these quantities are quantized by the ADC without losing accuracy in the correction, using 7 bits for each capacitance. The ADC phase control circuit 21 provides the ADC_TEST_CAPS signals that enable the estimation of MSB, MSB-1, and so on down to MSB-8 errors. The total number of bits required for the DACerr_C8 through DACerr_C16 is 63 bits, calculated as 7 bits multiplied by 9 capacitors. These 63 bits, calculated according to the previously explained equations, are stored in registers 22 at the end of the calibration procedure. During operational use, these stored bits are provided to the ADC 10 as a static correction.

[0099] The successive approximation process proceeds through several steps, starting with the most significant bit (MSB). In the first approximation, the capacitor C16p in switched capacitor circuit 15(16) of DAC 13 and C16n in switched capacitor circuit 35(16) of DAC 33, associated with the MSB and controlled by ADC_D<16:1>, are connected to VREF, which corresponds to the full scale of the ADC 10. Simultaneously, the calibration DACs 43 and 53 inject a correction equal to DACerr_C16. This forms a capacitive 1:1 divider with the rest of the matrix, resulting in a voltage at the comparator 11 input equal to Vin+VREF/2. The comparator 11 then returns a value of 1 or 0, depending on whether Vin is greater or less than VREF/2, and ADC_D<16:1> is set to this binary value.

[0100] In the second approximation, the capacitors C15p in switched capacitor circuit 15(15) of DAC 13 and C15n in switched capacitor circuit 35(15) of DAC 33, associated with MSB-1 and controlled by ADC_D<15:1>, are connected to VREF/2. The calibration DACs 43 and 53 inject a correction equal to DACerr_C15, which depends on the result from ADC_D<16:1>, i.e., the result of the previous approximation.

[0101] This pattern continues for the following approximations. In each step, the corresponding capacitors are connected to progressively smaller fractions of VREF: VREF/4 for the third approximation, VREF/8 for the fourth, and so on. The calibration DACs 43 and 53 inject corrections (DACerr_C14, DACerr_C13, etc.) that depend on the results of all previous approximations.

[0102] By the eighth approximation, the capacitors C9p in switched capacitor circuit 15(9) of DAC 13 and C9n in switched capacitor circuit 35(9) of DAC 33, associated with MSB-7 and controlled by ADC_D<9:1>, are connected to VREF/128. The calibration DACs 43 and 53 inject a correction equal to DACerr_C9, which depends on the results from ADC_D<16:1> through ADC_D<10:1>. For the remaining approximations, from the ninth to the sixteenth, the capacitors C8p to C1p in switched capacitor circuits 15(8) to 14(1) of DAC 13 and C8n to C1n in switched capacitor circuits 35(8) to 34(1) of DAC 33, associated with MSB-8 through the LSB respectively, are controlled by ADC_D<8:1> through ADC_D<1:1>. These are connected to voltages ranging from VREF/256 for the ninth approximation to VREF/32768 for the sixteenth approximation. Concurrently, the calibration DACs 43 and 53 continue to operate in conjunction with the main DACs 13 and 33 to apply the appropriate corrections throughout these final approximation steps.

[0103] Note that while these capacitors (C8p to C1p and C8n to C1n) participate in the conversion process, they are not individually calibrated. Instead, during these final steps, the calibration DACs 43 and 53 inject a common correction equal to DACerr_C8 for all of these less significant bits. This correction depends on the results from ADC_D<16:1> through ADC_D<9:1>, i.e., the outcomes of the eight most significant bit decisions.

[0104] In this ADC 10 design, individual linearity correction is applied only to the 8 most significant capacitors (C16p to C9p and C16n to C9n), while a common correction factor is used for the remaining less significant capacitors. This balances accuracy with efficiency in the calibration process, as it has been found sufficient to achieve the desired performance while simplifying the calibration procedure and reducing the amount of calibration data that needs to be stored.

[0105] This method ensures that the most impactful errors (those in the most significant bits) are precisely corrected, while still providing some level of correction for the less significant bits. The result is an optimized balance between conversion accuracy and calibration complexity.

[0106] Finally, it is evident that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of this disclosure.

[0107] Although this disclosure has been described with a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, can envision other embodiments that do not deviate from the disclosed scope. Furthermore, skilled persons can envision embodiments that represent various combinations of the embodiments disclosed herein made in various ways.