Seed substrate for epitaxial growth use and method for manufacturing same, and semiconductor substrate and method for manufacturing same

Abstract

A seed substrate for epitaxial growth has a support substrate, a planarizing layer of 0.5 to 3 m provided on the top surface of the support substrate, and a seed crystal layer provided on the top surface of the planarizing layer. The support substrate includes a core of group III nitride polycrystalline ceramics and a 0.05 to 1.5 m encapsulating layer that encapsulates the core. The seed crystal layer is provided by thin-film transfer of 0.1 to 1.5 m of the surface layer of Si<111> single crystal with oxidation-induced stacking faults (OSF) of 10 defects/cm.sup.2 or less. High-quality, inexpensive seed substrates with few crystal defects for epitaxial growth of epitaxial substrates and solid substrates of group III nitrides such as AlN, AlxGa1-xN (0<X<1) and GaN are obtained.

Claims

1. A seed substrate for epitaxial growth comprising: a support substrate; a planarizing layer provided on an upper surface of the support substrate, the planarizing layer having a thickness of 0.5 to 3.0 m; and a seed crystal layer provided on an upper surface planarizing layer, wherein the support substrate comprises: a core formed by group III nitride polycrystalline ceramics; and an encapsulating layer that encapsulates the core, the encapsulating layer having a thickness of 0.05 to 1.5 m, and the seed crystal layer is provided by thin-film transfer of 0.1 to 1.5 m of a surface layer of Si<111> single crystal with oxidation-induced stacking faults of no more than 10 defects/cm.sup.2.

2. A seed substrate for epitaxial growth comprising: a support substrate; a planarizing layer provided on an upper surface of the support substrate, the planarizing layer having a thickness of 0.5 to 3.0 m; and a seed crystal layer provided on an upper surface planarizing layer, wherein the support substrate comprises: a core formed by group III nitride polycrystalline ceramics; and an encapsulating layer that encapsulates the core, the encapsulating layer having a thickness of 0.05 to 1.5 m, and the seed crystal layer has oxidation-induced stacking faults of no more than 10 defects/cm.sup.2, and the thickness of the seed crystal layer is 0.1 to 1.5 m.

3. The seed substrate for epitaxial growth as claimed in claim 1, wherein the group III nitride polycrystalline ceramics forming the core are AlN ceramics.

4. The seed substrate for epitaxial growth as claimed in claim 1, wherein the encapsulating layer includes at least a layer of Si.sub.3N.sub.4.

5. The seed substrate for epitaxial growth as claimed in claim 1, wherein the planarizing layer comprises SiO.sub.2 and/or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) or AlAs.

6. The seed substrate for epitaxial growth as claimed in claim 1, wherein the electrical resistivity (at room temperature) of Si<111> forming the seed crystal layer is 1 k-cm or higher.

7. The seed substrate for epitaxial growth as claimed in claim 1, further comprises a stress-adjusting layer on the bottom surface of the support substrate.

8. The seed substrate for epitaxial growth as claimed in claim 7, wherein the stress-adjusting layer has a thermal expansion coefficient that enables further correction of the warpage after the planarizing layer is provided, and consists of polycrystalline Si prepared by a method selected from at least the sputtering, plasma CVD, and LPCVD.

9. The seed substrate for epitaxial growth as claimed in claim 7, wherein the stress-adjusting layer is provided as polycrystalline Si with SiO.sub.2 and/or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) interposing just below the bottom surface of the support substrate.

10. The seed substrate for epitaxial growth as claimed in claim 1, wherein the encapsulation layer is deposited by LPCVD.

11. The seed substrate for epitaxial growth as claimed in claim 1, wherein the planarizing layer is formed by depositing SiO.sub.2 and/or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) or AlAs on one or all sides of the top surface of the support substrate by one of plasma CVD, LPCVD, and low-pressure MOCVD.

12. The seed substrate for epitaxial growth as claimed in claim 1, wherein the seed crystal layer is provided by ion implanting hydrogen and/or He into Si<111> single crystal with oxidation-induced stacking faults of 10 defects/cm.sup.2 or less and electrical resistivity (at room temperature) of 1 k-cm or higher, followed by transferring a thin film of the Si<111> single crystal of 0.1 to 1.5 m by physical means at 450 C. or lower.

13. A semiconductor substrate on which a III-V semiconductor thin film is deposited on the top surface of a seed substrate for epitaxial growth according to claim 1.

14. The semiconductor substrate as claimed in claim 13, wherein the III-V semiconductor thin film is a nitride semiconductor thin film containing Ga and/or Al.

15. A manufacturing method of seed substrate for epitaxial growth comprising: preparing a core consisting of group III nitride polycrystalline ceramics; obtaining a support substrate by depositing an encapsulating layer so as to wrap the core, the encapsulating layer having a thickness of 0.05 to 1.5 m; depositing a planarizing layer on an upper surface of the support substrate, the planarizing layer having a thickness of 0.5 to 3.0 m; and providing a seed crystal layer by thin-film transfer of 0.1 to 1.5 m of the surface layer of Si<111> single crystal with oxidation-induced stacking faults of no more than 10 defects/cm.sup.2 on the top surface of the planarizing layer.

16. The manufacturing method of seed substrate for epitaxial growth as claimed in claim 15, wherein the encapsulation layer is deposited by the LPCVD.

17. The manufacturing method of seed substrate for epitaxial growth as claimed in claim 15, wherein the planarizing layer is formed by depositing SiO.sub.2 and/or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) or AlAs on one or all sides of the top surface of the support substrate by one of plasma CVD, LPCVD, and low-pressure MOCVD.

18. The manufacturing method of seed substrate for epitaxial growth as claimed in claim 15, wherein in the step of providing the seed crystal layer, the seed crystal layer is provided by ion implanting hydrogen and/or He into Si<111> single crystal with oxidation-induced stacking faults of 10 defects/cm.sup.2 or less and electrical resistivity (at room temperature) of 1 k-cm or more, followed by transferring a thin film of the Si<111> single crystal of 0.1 to 1.5 m by physical means at 450 C. or less.

19. The manufacturing method of seed substrate for epitaxial growth as claimed in claim 15, further providing a stress-adjusting layer on the bottom surface of the support substrate.

20. The manufacturing method of seed substrate for epitaxial growth as claimed in claim 19, wherein the stress-adjusting layer has a thermal expansion coefficient that enables further correction of the warpage after the planarizing layer is provided, and consists of polycrystalline Si prepared by a method selected from at least the sputtering, plasma CVD, and LPCVD.

21. A manufacturing method of semiconductor substrate comprising: manufacturing a seed substrate for epitaxial growth by the manufacturing method of seed substrate for epitaxial growth as claimed in claim 15; and depositing a III-V semiconductor thin film on the top surface of the seed substrate for epitaxial growth.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram showing the cross-sectional structure of a seed substrate 1.

(2) FIG. 2 is a diagram showing the procedure for manufacturing the seed substrate 1.

EMBODIMENTS OF THE INVENTION

(3) The embodiments of the present invention will be described in detail hereinafter, but the present invention is not limited thereto.

(4) FIG. 1 shows a cross-sectional structure of a seed substrate for epitaxial growth of group III nitrides (hereinafter simply referred to as seed substrate) 1. The seed substrate 1 shown in FIG. 1 has a structure in which a planarizing layer 4 and a Si<111> seed crystal layer 2 are stacked on a support substrate 3. In addition, if necessary, the stress-adjusting layer 5 is provided on the surface (bottom surface) of the support substrate 3 opposite the surface on which the planarizing layer 4 is stacked.

(5) The support substrate 3 has a core 31 serving as the core material of the support substrate 3, and an encapsulating layer 32 covering the core 31.

(6) The core 31 is formed by group III nitride polycrystalline ceramics. Specifically, AlN, Si.sub.3N.sub.4, GaN, or a mixture of these materials can be used. Polycrystalline AlN ceramics are suitable because they have the lattice constant and thermal expansion coefficient close to those of the target group III nitride crystal, have high thermal conductivity, and are inexpensive. In terms of device processing, wafers with a mirror finish of 200 to 1000 m thickness should be selected, which can be handled in semiconductor production lines. There are various manufacturing methods for AlN ceramics, but because of their productivity, the so-called sheet forming/atmospheric pressure sintering method is commonly used. In the sheet forming/atmospheric pressure sintering method, AlN powder, sintering agent, organic binders, and solvents are mixed to create wafer-like green sheets, which are then defatted, sintered in an N.sup.2 atmosphere, and polished to make products. The sintering agent may be selected from Y.sub.2O.sub.3, Al.sub.2O.sub.3, CaO, and the like, but Y.sub.2O.sub.3 is usually suitable because it exhibits the highest thermal conductivity in the substrate after sintering.

(7) If AlN ceramic is used as the core 31 as it is, metallic impurities in the raw materials AlN and Y.sub.2O.sub.3 powder, as well as carbon, oxygen, and other impurities from insulation materials, furnace materials, containers, etc. during sintering become a source of contamination, causing adverse effects such as crystal defects and coloration in the target single crystal.

(8) Therefore, an encapsulating layer 32 is provided that wraps and encapsulates the polycrystalline ceramic core 31. Specifically, when encapsulating the core 31 with the encapsulating layer 32, each layer comprising the encapsulating layer 32 must be considered in terms of its composition and thickness so that thermal stress is as small as possible and thermal conduction is as large as possible. In the present invention, it is preferable to optimize the total thickness of the encapsulating layer 32 in the range of 0.05 to 1.5 m from a manufacturing cost standpoint.

(9) The composition of the encapsulation layer 32 can be selected appropriately in consideration of thermal expansion coefficient and thermal conductivity, but to enhance its impurity diffusion prevention ability, it is preferable to cover and encapsulate the entire core at least with a film consisting of silicon nitride (Si.sub.3N.sub.4).

(10) This encapsulating layer 32 may be provided with p-Si as a layer for electrostatic chucking, if necessary, for example, if the use of electrostatic chucking is desired. This p-Si layer may be deposited between the AlN ceramics and the Si.sub.3N.sub.4 layer, or possibly together with or under the stress-adjusting layer 5 described below. In such cases, if adhesion between p-Si and AlN core and Si.sub.3N.sub.4 is insufficient, a film of SiO.sub.2 or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) with high adhesion properties may be interposed, taking into account the affinity and thermal expansion coefficient between each layer.

(11) For seed substrates for epitaxial growth of group III nitrides such as GaN for high-frequency applications, especially for very high-frequency applications such as Giga Hz wave or millimeter wave, in order to avoid high-frequency losses in devices fabricated using epitaxial layers grown on the seed substrates, the electrical resistivity (room temperature) of the above Si<111> seed crystal layer 2 is preferably 1 K-cm or more. This is because the Si<111> seed crystal layer 2 with an electrical resistivity (at room temperature) of 1 K-cm or less would cause high-frequency losses due to giga Hz wave or millimeter wave, resulting in device heat generation and high power consumption, and would not provide sufficient characteristics.

(12) When a p-Si film is provided for the electrostatic chuck, its resistance should be as high as possible to provide the necessary adsorption force. The p-Si film may be deposited on the lower layer of core 31, as far away as possible from the seed crystal layer 2 on which the epitaxial film is stacked, or on the lower part of the stress-adjusting layer 5, or may be multi-layered deposited simultaneously with the stress-adjusting layer 5. High-resistance p-Si has a low high-frequency loss, and when placed at the bottom of the support substrate 3, it is close to the electrostatic chuck, so even with high resistance, sufficient electrostatic force is available. Therefore, substrate adsorption is possible sufficiently without doping. To further reduce high-frequency losses, it is more desirable to remove the p-Si layer by back-grinding the substrate at the end of device fabrication. When the stress-adjusting layer 5 is provided, it is preferable to maintain the p-Si resistance as high as possible, but the minimum amount of boron (B), phosphorus (P), or other doping necessary to generate the required electrostatic force is not restricted.

(13) In the encapsulating layer 32, if the thickness of each layer becomes too thick, the stress between the layers increases due to the difference in thermal expansion coefficient, causing delamination between the layers. Therefore, even if films of various compositions are selected and combined, it is not desirable for the thickness of the encapsulating layer 32 to be more than 1.5 m. On the other hand, in terms of the function of sealing impurities, a thickness of 0.05 m or less is insufficient to prevent the diffusion of impurities. From the above, the thickness of the encapsulating layer 32 is preferably in the range of 0.05 to 1.5 m. The deposition method for the encapsulation layer can be selected from conventional deposition methods such as MOCVD, atmospheric pressure CVD, LPCVD, sputtering, etc. The LPCVD is particularly preferred because of the film quality, the film coverage, and the impurity diffusion prevention ability.

(14) A planarizing layer 4 of 0.5 to 3 m is stacked on the encapsulating layer 32 at least on the top surface of the support substrate 3. The planarizing layer 4 is selected from ordinary ceramic film materials such as SiO.sub.2, Al.sub.2O.sub.3, Si.sub.3N.sub.4, SiC, or silicon oxynitride (Si.sub.xO.sub.yN.sub.z), etc., or Si, GaAs, AlAs, etc., which are often used as sacrificial layers for etching, etc. It is preferable to select SiO.sub.2 and/or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) or AlAs, which are easy to grind or polish during planarization and easy to separate when obtaining solid substrates.

(15) The planarizing layer 4 is normally stacked only on one side of the encapsulating layer 32 from a cost standpoint, but if the warpage is large, it can be deposited to cover the entire encapsulating layer 32. The thickness of the planarizing layer 4 must be thick enough to fill voids and irregularities in the core 31 and encapsulating layer 32, etc., and smooth enough to transfer seed crystals. However, a planarizing layer 4 that is too thick is undesirable because it can cause warping and cracking of the seed substrate 1. Therefore, it is suitable to provide a planarizing layer with a thickness of 0.5 to 3 m on at least the top surface of the support substrate. This is because if the thickness is less than 0.5 m, it is almost impossible to fill the voids and irregularities in the AlN ceramics core 31 and encapsulating layer 32, and if the thickness is 3 m or more, warping by the planarizing layer 4 is likely to occur.

(16) Plasma CVD, LPCVD, or low-pressure MOCVD are suitable for the deposition of the planarizing layer 4 in terms of their required film quality and deposition efficiency. The stacked SiO.sub.2 and/or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) or AlAs are heat treated for quenching or CMP polished for smoothness, depending on the film conditions, to prepare for thin-film transfer of the seed crystal layer 2 described below.

(17) The seed crystal is selected to be a substrate with a crystal structure similar to group III nitrides such as AlN, Al.sub.xGa.sub.1-xN (0<X<1), GaN, etc., which are the subject of the present invention. Therefore, Si<111>, SiC, SCAM, AlN, AlGaN, sapphire, etc. are candidates, but Si<111> is suitable from the viewpoints of ease of large-diameter production, availability of commercial products, and low cost. Among Si<111> crystals, Si<111> single crystals with oxidation-induced stacking faults (OSF) of 10 defects/cm.sup.2 or less are particularly suitable, as described above.

(18) This is because when the OSF of Si<111> seed crystal, which is the seed for the next process of epitaxial deposition, is 10 defects/cm.sup.2 or less, the epitaxially deposited crystal has fewer defects following the seed crystal, resulting in superior device characteristics and high yield, which leads to low cost. On the other hand, when the OSF exceeds 10 defects/cm.sup.2, defects in the epitaxially deposited crystal increase greatly, resulting in poor device characteristics, which inevitably worsen yield and lead to high costs.

(19) When the epitaxial substrates and solid substrates obtained by epitaxial deposition on the seed substrates 1 are used for high-frequency devices, especially for 5G and beyond, it is preferable to select Si<111> seed crystals with an electrical resistivity (room temperature) of 1 K-cm or higher. This is because if the electrical resistivity (at room temperature) of the Si<111> seed crystal is less than 1 K-cm, its resistance causes high-frequency loss, which increases power consumption and generates heat, degrading device characteristics.

(20) Ion implantation limited to hydrogen and/or helium (He) ion species that have little effect on the electrical resistance of the single crystal substrate is performed on the Si<111> seed crystal, and then the ion-implanted surface of the Si<111> seed crystal is bonded to the top surface of the planarizing layer 4, and a thin film of 0.1 to 1.5 m is peeled off and transferred to the planarizing layer 4 using physical means such as a nail at 450 C. or lower to form the seed crystal layer 2. Unlike heavy elements such as boron (B), light elements such as hydrogen and He are suitable for ion implantation into seed crystals because ion implantation causes little damage to the seed crystal and does not lower its electrical resistance. In addition, peeling and transferring at low temperatures below 450 C. prevents thermal damage to the Si<111> seed crystals, which is unavoidable in the usual smart-cut method of thermal peeling and transferring at high temperatures above 700 C.

(21) The transfer thickness of the seed crystal layer 2 is preferably 0.1 to 1.5 m. In the ion implantation, the damage layer alone has a thickness of nearly 0.1 m, and a suitable seed crystal cannot be obtained if the thickness is less than 0.1 m. In addition, the ion implant machine requires high output ion energy for transfer thicknesses of 1.5 m or more, and the ion implanter becomes huge in size, requiring a huge investment, which is not economical. Although it may be difficult to measure the defect density directly when the thickness of the seed crystal layer 2 becomes thin (e.g., 1.0 m or less), the defect density is not expected to change due to thin film transfer, so the OSF defect density in the seed crystal layer 2 is estimated to be 10 defects/cm.sup.2 or less, the same as that of Si<111> seed crystal.

(22) To be more specific, after ion implanting hydrogen and/or He into the seed crystal to a depth of 0.2 to 3.5 m, the top surface of the aforementioned planarizing layer 4 and the ion-implanted surface of the seed crystal are bonded. Then, the seed crystal may be peeled off by gas pressure, a nail, or other physical methods at temperatures below 450 C. This is because stress and thermal damage caused by impurity diffusion and thermal stress can easily occur in the seed crystal of the transferred thin film at high temperatures above 450 C.

(23) The top surface of the transferred thin film may then be CMP polished and/or lightly etched with chemicals to remove the inevitable ion implantation damage layer to obtain a seed single-crystal thin film (seed crystal layer 2) with a thickness of 0.1 to 1.5 m. If higher uniformity is required for ion implantation, SiO.sub.2, etc. can be deposited on the ion implantation surface of the seed substrate before ion implantation, if necessary.

(24) In the present invention, a stress-adjusting layer 5 may be further added to the bottom surface of the support substrate 3, if necessary. For the stress-adjusting layer 5, film material and thickness with a thermal expansion coefficient that enables correction of warpage of the seed substrate 1 caused by forming the planarizing layer 4 are selected. For example, the stress-adjusting layer 5 can be selected from SiO.sub.2, Si.sub.3N.sub.4, amorphous Si, polycrystalline Si, etc. alone or in combination. Here, when considering even the compatibility to the electrostatic chuck of the process equipment in the device manufacturing process, polycrystalline Si prepared at least by a method selected from sputtering, plasma CVD, and LPCVD is suitable for the bottom layer of the support substrate. Generally, it is suitable to deposit polycrystalline Si (p-Si) as the stress-adjusting layer 5, which is also compatible with the electrostatic chuck. SiO.sub.2 and/or silicon oxynitride (Si.sub.xO.sub.yN.sub.z) or the like may be interposed between the polycrystalline Si and the encapsulating layer from the viewpoint of warpage correction and affinity with the encapsulating layer 32. When a polycrystalline Si film that also serves as a chucking film for the electrostatic chuck is used as the stress-adjusting layer 5, polycrystalline Si may be deposited directly, or amorphous Si may be deposited and then polycrystallized by heating or laser irradiation. By providing a polycrystalline Si film as the lowest layer, the distance between the electrostatic chuck surface and the chuck-compatible film can be shortened, and the resistivity of the film can be lowered to increase the electrostatic adsorption force.

(25) Then, with reference to FIG. 2, the procedure for the manufacturing method of the seed substrate for group III nitride epitaxial growth according to the embodiment of the present invention will be described. If a suitable method for forming each layer has already been described in conjunction with the composition of each part of the seed substrate 1, a redundant explanation here is omitted.

(26) First, the core 31 consisting of nitride ceramics is prepared (S01 in FIG. 2). Next, the encapsulating layer 32 with a thickness of 0.05 to 1.5 m, is deposited so as to wrap in the core 31 and the support substrate 3 is obtained (S02 in FIG. 2). In this case, the encapsulating layer 32 may be deposited by using an LPCVD. Next, the planarizing layer 4 with a thickness of 0.5 to 3.0 m, is deposited on the upper surface of the support substrate 3 (S03 in FIG. 2). If necessary, the stress-adjusting layer 5 is deposited on the bottom surface of the support substrate 3 (S04 in FIG. 2). The planarizing layer 4 and the stress-adjusting layer 5 may be deposited at the same time.

(27) Apart from S01-S04, a Si<111> single-crystal substrate 20, which is a seed crystal for peeling transfer of the seed crystal layer 2, is prepared (S11 in FIG. 2). Next, ion implantation is performed from one surface (ion implantation surface) of the single crystal substrate 20, and a peeling position (embrittlement layer) 21 is formed in the single crystal substrate 20 (S12 in FIG. 2).

(28) Next, the ion implantation surface of the single crystal substrate 20 is bonded to the planarizing layer 4 formed on the support substrate 3 to obtain a bonded substrate (S21 in FIG. 2). Then, the single crystal substrate 20 is separated at the peeling position 21 of the single crystal substrate 20 in the bonded substrate (S22 in FIG. 2). In this way, a single-crystal film of Si<111> is thinly transferred as a seed crystal layer 2 onto the planarizing layer 4 on the support substrate 3. On the other hand, the remaining section of the separated Si<111> single crystal substrate 20 can be repeatedly utilized for transferring a seed crystal layer when fabricating another group III nitride composite substrate by polishing the surface again to make an ion implantation surface.

(29) The above describes the configuration and manufacturing method of the seed substrate 1 for epitaxial growth. The present invention is a synergistic effect of two essential components: 1) minimization of thermal stress between each layer, especially by optimizing the composition and thickness of the encapsulating layer, and 2) growth of excellent epitaxial film crystals by using excellent seed crystals. Secondarily, 3) further stress reduction with a stress-adjusting layer if necessary, and 4) ion implantation limited to light elements of hydrogen and/or He and thin film transfer by physical means such as nails at 450 C. or lower are also effective. The present invention makes it possible to economically obtain epitaxial substrates and solid substrates with very little warpage, voids, crystal defects, etc., and very little high-frequency loss in devices.

(30) The substrate, according to the present invention significantly improves the characteristics of devices, such as light-emitting diodes used in the deep ultraviolet region (UVC; 200-280 nm), high-frequency devices for 5G communications and EV vehicles, and high-voltage devices, while also significantly improving device manufacturing yields.

EXAMPLES

(31) The present invention will be described more specifically hereinafter by citing examples and comparative examples below, but the present invention is not limited to these examples.

Example 1

(32) Preparation of Supporting Substrate

(33) A support substrate 3 with a polycrystalline ceramic core 31 covered with a sealing layer 32 was prepared. A commercially available AlN substrate was used for the polycrystalline ceramic core 31. The AlN substrate was made by mixing 100 wt % AlN powder and 5 wt % Y.sub.2O.sub.3 as a sintering agent with organic binders and solvents to make a green sheet, which was then degreased and sintered at 1900 C. under an N.sub.2 atmosphere. Both sides polished to 8 inchest725 m piece was used. The encapsulating layer 32 was formed by covering the entire AlN ceramic core 31 with a 0.1-m-thick silicon oxynitride layer by LPCVD, and then encapsulating the entire core with a 0.4-m-thick Si.sub.3N.sub.4 layer using another LPCVD apparatus. The total thickness of the encapsulating layer 32 was 0.5 m. For the purpose of planarization, a 6 m thick SiO.sub.2 was further stacked on the Si.sub.3N.sub.4 layer only on one side of the top surface by using the plasma CVD (ICP-CVD apparatus). Then, after baking at 1000 C., the SiO.sub.2 was planarized by CMP polishing to a thickness of 2 m (Ra=0.2 nm) in preparation for thin film transfer of the seed crystal.

(34) Preparation of Seed Crystal

(35) A Si<111> single-crystal substrate of 8 inches in diameter and 725 m in thickness was prepared as the seed crystal substrate. This Si<111> single-crystal substrate had oxidation-induced stacking faults (OSF) of 8 defects/cm.sup.2 and an electrical resistivity (room temperature) of 1.5 K-cm by the evaluation method described in Patent Document 3. Ion implantation of hydrogen was carried out on the Si substrate at 100 keV, at a depth of 0.6 m, and with a dose of 810.sup.17 cm.sup.2.

(36) A 0.6 m portion of the surface layer of this ion-implanted Si<111> single crystal was thinly transferred to the planarizing layer 4 (2 m thickness) of the previously prepared support substrate 3. The section of the Si<111> single crystal, which was damaged during ion implantation and transfer, was lightly polished with CMP, and the thickness of the Si<111> single crystal layer was reduced to 0.4 m, which was used as seed crystal layer 2. The resulting seed substrate 1 was free of cracks, delamination, and warpage as a result of ensuring that the film thicknesses were balanced with respect to the thermal stresses between each layer of the encapsulating layer 32, the encapsulating layer 32, the planarizing layer 4, and the seed crystal layer 2.

(37) The remaining Si<111> single-crystal substrate after thin-film transfer could be used repeatedly as many seed crystals by repeated ion implantation, which was extremely economical.

(38) A seed substrate 1 with a 2 m-thick planarizing layer 4 and a 0.4 m-thick Si<111> single-crystal seed crystal layer 2 on a support substrate 3 with an AlN ceramic core 31 and encapsulating layer 32 was obtained. The following brief evaluation of the characteristics of this seed substrate 1 as a seed substrate for epitaxial growth of GaN was performed.

(39) The above seed substrate 1 was placed in the reactor of the MOCVD apparatus, and epitaxial growth was performed. In this process, the epitaxial layers were deposited in the order of AlN and AlGaN from the seed substrate 1 side toward the growth direction, followed by the epitaxial growth of GaN. The structure of the epitaxial layers is not limited to this, for example, AlGaN may not be deposited, or AlN may be deposited further after AlGaN deposition. In this evaluation, 100 nm of the AlN layer and 150 nm of the AlGaN layer were formed. The total thickness of the epitaxial layer was 5 m. During epitaxial growth, TMAl (trimethylaluminum) can be used as the Al source, TMGa (trimethylgallium) can be used as the Ga source, and NH3 can be used as the N source, but not limited to these. The carrier gas can be N.sub.2 and H.sub.2 or any of them. The process temperature preferably be around 900-1200 C.

(40) Then, to evaluate dislocation density, etch pits were generated by a molten alkali (KOH) etching method, and etch pit density (EPD) was measured. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate the crystallinity.

(41) As a result, the EPD showed an extremely low dislocation density of 0.210.sup.4 cm.sup.2. The XRC measurements on a Ga (0002) plane of the substrate yielded a half-value width FWHM (hereafter simply referred to as FWHM of 0002XRC) of 135 arcsecs, resulting in a high-quality GaN single crystal. These results show that seed substrate 1 in this example has excellent characteristics as a seed substrate for epitaxial growth. When this epitaxial substrate with an epitaxial layer on the seed substrate 1 was used for a 30 GHz/20 Gbps high-frequency device, the surface temperature of the device was 43 C., and there was no temperature increase due to high-frequency loss that would cause a significant problem.

Comparative Example 1

(42) A single-crystal Si<111> single-crystal substrate of 8 inches in diameter with oxidation-induced stacking faults (OS F) of 16 defects/cm.sup.2 and an electrical resistivity (room temperature) of 0.2 K-cm was used as the seed substrate, and a seed crystal layer 2 with a thickness of 1.3 m was thinly transferred. Other than that, seed substrate 1 was fabricated under the same conditions as in Example 1. In the same way as in Example 1, 5 m of GaN was deposited on this seed substrate 1 by MOCVD. As a result, the EPD showed an extremely large dislocation density of 1510.sup.4 cm.sup.2. In addition, the FWHM of the 0002 XRC was 930 arcsec, resulting in a GaN single crystal with poor crystallinity compared to Example 1. When this epitaxial substrate was used for 30 GHz/20 Gbps high-frequency devices, the surface temperature of the device reached as high as 125 C. due to high-frequency loss, thus long-term use was not possible.

Example 2

(43) Preparation of Supporting Substrate

(44) A support substrate 3 with a polycrystalline ceramic core 31 covered with a sealing layer 32 was prepared. A commercially available AlN substrate as in Example 1 was used for the polycrystalline ceramic core 31. The encapsulating layer 32 was formed by covering the entire AlN ceramic core 31 with a 0.3-m-thick SiO.sub.2 layer by LPCVD, and then encapsulating the entire core with a 0.8-m-thick Si.sub.3N.sub.4 layer using another LPCVD apparatus. The total thickness of the encapsulating layer 32 was 1.1 m. For further planarization, 5 m of silicon oxynitride was stacked on this Si.sub.3N.sub.4 layer by LPCVD only on the upper layer of the encapsulating layer 32. After that, the silicon oxynitride layer was CMP polished to a thickness of 2.5 m. At this stage, the entire substrate warped significantly, approximately 30 m. To correct the warpage, a 5 m-thick of silicon oxide layer and a 0.2 m-thick of non-doped polycrystalline Si layer, which also serves as an electrostatic chuck adsorption layer, were deposited as a stress-adjusting layer 5 on the bottom surface by plasma CVD. As a result, the warpage was eliminated, and sufficient attachment and removal could be performed for the electrostatic chuck.

(45) Preparation of Seed Crystal

(46) A Si<111> single-crystal substrate of 8 inches in diameter and 725 m in thickness was prepared as the seed crystal substrate. This Si<111> single-crystal substrate had oxidation-induced stacking faults (OSF) of 0 defects/cm.sup.2 and an electrical resistivity (room temperature) of 2.3 K-cm by the evaluation method described in Patent Document 3. Ion implantation of hydrogen was carried out on the Si substrate at 130 keV, at a depth of 1.4 m, and with a dose of 9.510.sup.17 cm.sup.2.

(47) A 1.4 m portion of the surface layer of this ion-implanted Si<111> single crystal was thinly transferred to the planarizing layer 32 (2.5 m thickness) of the previously prepared support substrate 3. The section of the Si<111> single crystal, which was damaged during ion implantation and transfer, was lightly polished with CMP, and the thickness of the Si<111> single crystal layer was reduced to 1 m, which was used as seed crystal layer 2. The resulting seed substrate 1 was free of cracks, delamination, and warpage as a result of ensuring that the film thicknesses were balanced with respect to the thermal stresses between each layer of the encapsulating layer 32, the encapsulating layer 32, the planarizing layer 4, and the seed crystal layer 2.

(48) As in Example 1, the remaining Si<111> single-crystal substrate after thin-film transfer could be used repeatedly as many seed crystals by repeated ion implantation, which was extremely economical.

(49) A seed substrate 1 with a 2.5 m-thick planarizing layer 4 and a 1 m-thick Si<111> single-crystal seed crystal layer 2 on a support substrate 3 with an AlN ceramic core 31 and encapsulating layer 32 was obtained. The following brief evaluation of the characteristics of this seed substrate 1 as a seed substrate for epitaxial growth of AlN was performed.

(50) A 600 m single crystal of AlN was deposited on this seed substrate 1 by THVPE using AlCl.sub.3 and NH.sub.3 as raw materials. The deposited AlN single crystals were cut into pieces with a wire saw and polished to make smooth 0-inch substrates. The cut AlN single-crystal substrates had no coloration, and the transmittance of light at a wavelength of 220 nm was about 80% with a film thickness of 100 m. Then, the following brief evaluation was conducted using this substrate as a seed substrate for epitaxial growth of AlN.

(51) 2 m of AlN was deposited on the substrate by MOCVD, and as in the evaluation in Example 1, etch pits were generated by molten alkali (KOH) etching method to evaluate dislocation density, and EPD was measured. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate the crystallinity.

(52) As a result, the EPD showed an extremely low dislocation density of 0.510.sup.4 cm.sup.2. In addition, the FWHM of the 0002 XRC was 110 arcsec, resulting in a high-quality AlN single crystal. This AlN single-crystal substrate has very few defects as an LED substrate for the deep-ultraviolet region and is an excellent substrate with excellent device characteristics and low cost.

Example 3

(53) The planarization layer 4 was a two-layer SiO.sub.2/AlAs structure with a total thickness of 2.5 m, consisting of a 2-m-thick AlAs bottom layer and a 0.5-m-thick SiO2 top layer. Other than that, seed substrate 1 for epitaxial growth was obtained under the same conditions as in Example 1.

(54) The remaining Si<111> single-crystal substrate after thin-film transfer could be used repeatedly as many seed crystals by repeated ion implantation, which was extremely economical.

(55) A seed substrate 1 with a support substrate 3 having a structure of AlN ceramic core 31 and encapsulating layer 32, a composite planarizing layer 4 of SiO.sub.2/AlAs with a total thickness of 2.5 m, and a 0.4 m thick Si<111> single crystal seed crystal layer 2 thereon was obtained. Using this seed substrate 1 as a seed substrate for epitaxial growth of GaN, a thick film of GaN was epitaxially grown.

(56) After depositing a 30 m GaN film on the above seed substrate 1 by MOCVD, the planarizing layer 4 of SiO.sub.2/AlAs was dissolved in HF solution to obtain a solid GaN substrate with an approximate thickness of 30 m.

(57) To evaluate the dislocation density of this solid GaN substrate, etch pits were generated by the molten alkali (KOH) etching method, and EPD was measured, as in the evaluation in Example 1. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate the crystallinity.

(58) As a result, the EPD showed an extremely low dislocation density of 0.0510.sup.4 cm.sup.2. In addition, the FWHM of the 0002 XRC was 101 arcsec, resulting in a high-quality GaN single crystal. These figures show that the seed substrate 1 in this example is extremely excellent as a seed substrate for epitaxial growth to obtain a solid substrate. The solid GaN substrate obtained by epitaxial growth using this seed substrate 1 was used for high-frequency devices at 30 GHz/20 Gbps. The surface temperature of the device was 38 C., indicating that the substrate was excellent with low heat generation due to high-frequency loss.

REFERENCE SIGNS LIST

(59) 1 Seed substrate 2 Seed crystal layer 3 Supporting substrate 4 Planarizing layer 5 Stress-adjusting layer 20 Single crystal substrate of a seed crystal 21 Peeling position