ReRAM Device and Method for Manufacturing the Same

Abstract

The present application discloses a ReRAM device, the bottom surface of a first resistance switching layer is connected with a bottom electrode, and a first groove is formed in the center of the top surface of the first resistance switching layer. A second resistance switching layer is formed on the first resistance switching layer, the center of the bottom surface of the second resistance switching layer is filled downwards into the first groove, and the top surface of the second resistance switching layer is connected with a top electrode. The material of the second resistance switching layer is more conductive than the material of the first resistance switching layer. The present application can maintain the stability of the central conductive filament in the low resistance state. The present application further discloses a method for manufacturing the ReRAM device.

Claims

1. A resistive random access memory (ReRAM) device, wherein the ReRAM device comprises a first resistance switching layer, a second resistance switching layer, a bottom electrode, and a top electrode; a bottom surface of the first resistance switching layer is connected with the bottom electrode, and a first groove is formed in a center of a top surface of the first resistance switching layer; the second resistance switching layer is formed on the first resistance switching layer, a center of a bottom surface of the second resistance switching layer is filled downwards into the first groove in the center of the top surface of the first resistance switching layer, and a top surface of the second resistance switching layer is connected with the top electrode; and a material of the second resistance switching layer is more conductive than a material of the first resistance switching layer.

2. The ReRAM device according to claim 1, wherein the first resistance switching layer is SrTiO.sub.3, SrZrO.sub.3, NiO, TiO.sub.2, TaO, TaO.sub.2, Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2, or Ta.sub.2O; and the second resistance switching layer is SrTiO.sub.3, SrZrO.sub.3, NiO, TiO.sub.2, TaO, TaO.sub.2, Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2, or Ta.sub.2O.

3. The ReRAM device according to claim 1, wherein a second groove is formed in a center of the top surface of the second resistance switching layer; a transverse dimension of the second groove is smaller than a transverse dimension of the first groove and the second groove is located right above the first groove; and the top electrode is filled downwards into the second groove in the center of the top surface of the second resistance switching layer.

4. The ReRAM device according to claim 3, wherein the first resistance switching layer is Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2, or Ta.sub.2O; and the second resistance switching layer is TaO.sub.2 or TaO.

5. The ReRAM device according to claim 3, wherein a depth of the first groove is ½-⅘ of a thickness of the first resistance switching layer; and a thickness of a part outside the first groove of the second resistance switching layer is 1-1.5 times the depth of the first groove.

6. The ReRAM device according to claim 3, wherein a depth of the second groove is ½-⅘ of a thickness of a part outside the first groove of the second resistance switching layer.

7. The ReRAM device according to claim 3, wherein the transverse dimension of the second groove is ⅓-⅔ of the transverse dimension of the first groove.

8. The ReRAM device according to claim 3, wherein a thickness of the first resistance switching layer is 3 nm-30 nm.

9. The ReRAM device according to claim 3, wherein a material of a surface of the top electrode in contact with the top surface of the second resistance switching layer is Ag, Pt, Ta, Ti, or TiN; and a material of a surface of the bottom electrode in contact with the bottom surface of the first resistance switching layer is Ag, Pt, Ta, Ti, or TiN.

10. A method for manufacturing the ReRAM device according to claim 1, comprising: step 1: performing a metal layer process to form a metal layer of a bottom electrode of the ReRAM device on a wafer, the wafer outside a central area of the metal layer of the bottom electrode of the ReRAM device being covered with an isolation dielectric layer; step 2: sequentially depositing a bottom electrode contact surface layer and a first resistance switching layer on the metal layer of the bottom electrode of the ReRAM device and the isolation dielectric layer, a first groove being formed in the first resistance switching layer right above the bottom electrode; step 3: depositing a second resistance switching layer; step 4: performing etching to remove the second resistance switching layer, the first resistance switching layer, and the bottom electrode contact surface layer which cover the isolation dielectric layer outside the metal layer of the bottom electrode and an adjoining area thereof, and reserve the second resistance switching layer, the first resistance switching layer, and the bottom electrode contact surface layer which cover positions right above the metal layer of the bottom electrode and the adjoining area thereof; step 5: depositing a top electrode contact surface layer; and step 6: performing etching to remove the top electrode contact surface layer on outer sides of the second resistance switching layer, the first resistance switching layer, and the bottom electrode contact surface layer.

11. The method for manufacturing the ReRAM device according to claim 10, wherein after step 2, the first resistance switching layer in the center right above the metal layer of the bottom electrode is etched firstly to widen a transverse dimension of the first groove and/or deepen a depth of the first groove, and then step 3 is performed.

12. The method for manufacturing the ReRAM device according to claim 10, wherein the isolation dielectric layer is SiN; the first resistance switching layer is Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2, or Ta.sub.2O; the second resistance switching layer is TiO.sub.2 or TaO; the bottom electrode contact surface layer is formed of Ta, Ti, or TiN; and the top electrode contact surface layer is formed of Ta, Ti, or TiN.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly describe the technical solution of the present application, the drawings required for the present application will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the present application. Those skilled in the art may obtain other drawings based on these drawings without contributing any inventive labor.

[0042] FIG. 1 illustrates a schematic diagram of a structure of a common ReRAM device.

[0043] FIG. 2 illustrates a schematic diagram of a structure of a memory array formed by ReRAM.

[0044] FIG. 3 illustrates a schematic diagram of a structure of a memory cell formed by a ReRAM device.

[0045] FIG. 4 illustrates a schematic diagram of resistance change of a common ReRAM device.

[0046] FIG. 5 illustrates a schematic diagram of a structure of a ReRAM device according to an embodiment of the present application.

[0047] FIG. 6 illustrates a schematic diagram of a structure of a ReRAM device in a low resistance state according to an embodiment of the present application.

[0048] FIG. 7 illustrates a schematic diagram of a metal layer of a bottom electrode formed by adopting a method for manufacturing a ReRAM according to an embodiment of the present application.

[0049] FIG. 8 illustrates a schematic diagram in a step of sequentially depositing a bottom electrode contact surface layer and a first resistance switching layer in a method for manufacturing a ReRAM according to an embodiment of the present application.

[0050] FIG. 9 illustrates a schematic diagram in a step of depositing a second resistance switching layer in a method for manufacturing a ReRAM according to an embodiment of the present application.

[0051] FIG. 10 illustrates a schematic diagram in a step of forming a resistance switching layer in a method for manufacturing a ReRAM according to an embodiment of the present application.

[0052] FIG. 11 illustrates a schematic diagram in a step of forming a top electrode contact surface layer in a method for manufacturing a ReRAM according to an embodiment of the present application.

DESCRIPTION OF REFERENCE SIGNS

[0053] 5—first resistance switching layer; 6—second resistance switching layer; 1—bottom electrode; 2—top electrode; 3—isolation dielectric layer; 9—wafer; 11—bottom electrode metal layer; 12—bottom electrode contact surface layer; 22—top electrode contact surface layer.

DETAILED DESCRIPTION

[0054] The technical solution of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without contributing any inventive labor still fall within the scope of protection of the present application.

Embodiment 1

[0055] Referring to FIG. 5 and FIG. 6, a Resistive RAM (ReRAM) device includes a first resistance switching layer 5, a second resistance switching layer 6, a bottom electrode 1 and a top electrode 2;

[0056] a bottom surface of the first resistance switching layer 5 is connected with the bottom electrode 1, and a first groove is formed in a center of a top surface;

[0057] the second resistance switching layer 6 is formed on the first resistance switching layer 5, a center of a bottom surface of the second resistance switching layer 6 is filled downwards into the first groove in the center of the top surface of the first resistance switching layer 5, and a top surface of the second resistance switching layer 6 is connected with the top electrode 2;

[0058] the material of the second resistance switching layer 6 is more conductive than the material of the first resistance switching layer 5.

[0059] Further, the first resistance switching layer 5 is SrTiO.sub.3, SrZrO.sub.3, NiO, TiO.sub.2, TaO, TaO.sub.2, Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2 or Ta.sub.2O.

[0060] Further, the second resistance switching layer 6 is SrTiO.sub.3, SrZrO.sub.3, NiO, TiO.sub.2, TaO, TaO.sub.2, Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2 or Ta.sub.2O.

[0061] In the ReRAM device according to embodiment 1, the second resistance switching layer is formed on the first resistance switching layer, and the center of its bottom surface extends downwards and is filled into the first groove in the center of the top surface of the first resistance switching layer; the material of the second resistance switching layer is more conductive than the material of the first resistance switching layer. Starting from the structural aspect to improve the stability of the low resistance state, by forming the “concave” first resistance switching layer, the area most likely to form the conductive filament is in the central area of the resistance switching layer, which is not vulnerable to the influence of surrounding ions. The first resistance switching layer surrounds the downwards extending part of the center of the bottom surface of the second resistance switching layer. Since the first resistance switching layer is less conductive and the thickness of the surrounding part is larger than that of the central part, the surrounding part of the first resistance switching layer is difficult to be conducted completely, but it can effectively adsorb the surrounding ions. Therefore, each set can form incompletely conducted vacancies around the conductive filament, which can continuously adsorb the surrounding ions, thus maintaining the stability of the central conductive filament in the low resistance state, and solving the problem that the conductive thin layer (resistance switching layer) of the existing ReRAM device is vulnerable to the influence of surrounding ions, which makes the low resistance state unstable.

Embodiment 2

[0062] Based on the ReRAM device according to embodiment 1, a second groove is formed in a center of the top surface of the second resistance switching layer 6;

[0063] the transverse dimension of the second groove is smaller than the transverse dimension of the first groove and the second groove is located right above the first groove;

[0064] the top electrode 2 is filled downwards into the second groove in the center of the top surface of the second resistance switching layer 6.

[0065] In the ReRAM device according to embodiment 2, the center of the bottom surface of the second resistance switching layer 6 extends downwards and is filled into the first groove in the center of the top surface of the first resistance switching layer 5, and the top electrode 2 is filled downwards into the second groove in the center of the top surface of the second resistance switching layer 6. By forming the “concave” first resistance switching layer 5 and second resistance switching layer 6, it is ensured that the area most likely to form the conductive filament is in the center of the resistance switching layer, thus avoiding the influence of surrounding ions.

Embodiment 3

[0066] Based on the ReRAM device according to embodiment 2, referring to FIG. 5, the first resistance switching layer 5 is Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2 or Ta.sub.2O;

[0067] the second resistance switching layer 6 is TaO.sub.2 or TaO.

[0068] Further, the depth of the first groove is ½-⅘ of the thickness H1 of the first resistance switching layer 5;

[0069] the thickness H2 of the part outside the first groove of the second resistance switching layer 6 is 1-1.5 times the depth of the first groove.

[0070] Further, the depth of the second groove is ½-⅘ of the thickness H2 of the second resistance switching layer.

[0071] Further, the transverse dimension of the second groove is ⅓-⅔ of the transverse dimension of the first groove.

[0072] Further, the thickness of the first resistance switching layer is 3 nm-30 nm.

[0073] Further, the material of a surface of the top electrode 2 in contact with the top surface of the second resistance switching layer 6 is Ag, Pt, Ta, Ti or TiN;

[0074] the material of a surface of the bottom electrode 1 in contact with the bottom surface of the first resistance switching layer 5 is Ag, Pt, Ta, Ti or TiN.

[0075] In the ReRAM device according to embodiment 3, the first resistance switching layer 5 surrounds the downwards extending part of the center of the bottom surface of the second resistance switching layer 6. Since the first resistance switching layer 5 is less conductive and the thickness of the surrounding part is larger than that of the central part, the surrounding part of the first resistance switching layer 5 is difficult to be conducted completely, but it can effectively adsorb the surrounding ions. Therefore, referring to FIG. 6, each set can form incompletely conducted vacancies around the conductive filament, which can continuously adsorb the surrounding ions, thus maintaining the stability of the central conductive filament in the low resistance state, and solving the problem that the conductive thin layer of the existing ReRAM device is vulnerable to the influence of surrounding ions, which makes the low resistance state unstable.

Embodiment 4

[0076] A method for manufacturing the ReRAM device according to any one of embodiments 1-3 includes the following steps:

[0077] step 1: performing a metal layer process to form a metal layer 11 of a bottom electrode 1 of the ReRAM device on a wafer 9, the wafer 9 outside a central area of the metal layer 11 of the bottom electrode 1 of the ReRAM device being covered with an isolation dielectric layer 3, as illustrated in FIG. 7;

[0078] step 2: sequentially depositing a bottom electrode contact surface layer 12 and a first resistance switching layer 5 on the metal layer 11 of the bottom electrode 1 of the ReRAM device and the isolation dielectric layer 3, a first groove being formed in the first resistance switching layer 5 right above the bottom electrode 1, as illustrated in FIG. 8;

[0079] step 3: depositing a second resistance switching layer 6, as illustrated in FIG. 9;

[0080] step 4: performing etching to remove the second resistance switching layer 6, the first resistance switching layer 5 and the bottom electrode contact surface layer 12 which cover the isolation dielectric layer 3 outside the metal layer 11 of the bottom electrode 1 and an adjoining area thereof, and reserve the second resistance switching layer 6, the first resistance switching layer 5 and the bottom electrode contact surface layer 12 which cover positions right above the metal layer 11 of the bottom electrode 1 and the adjoining area thereof, as illustrated in FIG. 10;

[0081] step 5: depositing a top electrode contact surface layer 22;

[0082] step 6: performing etching to remove the top electrode contact surface layer 22 on outer sides of the second resistance switching layer 6, the first resistance switching layer 5 and the bottom electrode contact surface layer 12, as illustrated in FIG. 11.

[0083] Further, after step 2, the first resistance switching layer 5 in the center right above the metal layer 11 of the bottom electrode 1 is etched firstly to widen the transverse dimension of the first groove and/or deepen the depth of the first groove, and then step 3 is performed.

[0084] Further, the isolation dielectric layer 3 is SiN.

[0085] Further, the first resistance switching layer 5 is Ta.sub.2O.sub.6, Ta.sub.2O.sub.5, Ta.sub.2O.sub.4, Ta.sub.2O.sub.3, Ta.sub.2O.sub.2 or Ta.sub.2O;

[0086] the second resistance switching layer is TiO.sub.2 or TaO.

[0087] Further, the bottom electrode contact surface layer 12 is formed of Ta, Ti or TiN;

[0088] the top electrode contact surface layer 22 is formed of Ta, Ti or TiN.

[0089] What are described above are only preferred embodiments of the present application, which, however, are not used to limit the present application. Any modification, equivalent replacement, improvement and the like made within the essence and principle of the present application shall be included in the scope of protection of the present application.