APPARATUS AND METHODS FOR NONLINEARITY CANCELLATION IN ELECTRONIC SYSTEMS

Abstract

Apparatus and methods for nonlinearity cancellation in electronic systems are disclosed. In certain embodiments, an electronic system includes two or more circuit channels that process a common input signal in parallel and that each include at least one instantiation of a circuit that behaves nonlinearly. Thus, the nonlinear circuit is replicated and included at least once in each circuit channel. Each of the circuit channels has an input scaling factor and an output scaling factor that can vary from one circuit channel to another. The output signals from the circuit channels after scaling are combined to generate a combined output signal. The input and output scaling factors are selected to cancel or reduce nonlinearities.

Claims

1. An electronic system comprising: two or more circuit channels configured to process an input signal in parallel to generate two or more output signals, wherein the two or more circuit channels comprise: a first circuit channel including a first circuit block configured to receive the input signal scaled by a first input scaling factor, the first circuit channel configured to generate a first output signal based on scaling an output of the first circuit block by a first output scaling factor; and a second circuit channel including a second circuit block configured to receive the input signal scaled by a second input scaling factor, the second circuit channel configured to generate a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have a nonlinearity; and an output combiner configured to combine the two or more output signals including the first output signal and the second output signal to generate a combined output signal in which the nonlinearity is canceled.

2. The electronic system of claim 1, wherein the two or more circuit channels further comprise: a third circuit channel including a third circuit block configured to receive the input signal scaled by a third input scaling factor, the third circuit channel configured to generate a third output signal of the two or more output signals based on scaling an output of the third circuit block by a third output scaling factor.

3. The electronic system of claim 1, wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.

4. The electronic system of claim 3, wherein the input signal is an analog or radio frequency signal and the output signal is a digital signal.

5. The electronic system of claim 1, wherein a plurality of input scaling factors including the first input scaling factor and the second input scaling factor define a matrix, and wherein a plurality of output scaling factors including the first output scaling factor and the second output scaling factor are based on an inverse of the matrix.

6. The electronic system of claim 1, wherein the nonlinearity is a harmonic distortion component.

7. The electronic system of claim 1, further comprising a calibration circuit configured to calibrate the first output scaling factor based on a detected value of the first input scaling factor, and to calibrate the second output scaling factor based on a detected value of the second input scaling factor.

8. The electronic system of claim 1, wherein the second circuit channel further includes one or more additional circuit blocks in parallel with the second circuit block, each of the one or more additional circuit blocks receiving the input signal scaled by the second input scaling factor.

9. The electronic system of claim 8, wherein the second circuit channel is further configured to generate the second output signal based on combining an output of each of the one or more additional circuit blocks with the output of the second circuit block.

10. The electronic system of claim 1, wherein the second circuit block is a replica of the first circuit block.

11. The electronic system of claim 1, implemented in a phased array antenna.

12. A method of nonlinearity cancellation, the method comprising: processing an input signal in parallel using two or more circuit channels to generate two or more output signals, wherein processing the input signal includes: scaling the input signal by a first input scaling factor to generate a first scaled input signal for a first circuit block of a first circuit channel; generating a first output signal based on scaling an output of the first circuit block by a first output scaling factor; scaling the input signal by a second input scaling factor to generate a second scaled input signal for a second circuit block of a second circuit channel; generating a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have a nonlinearity; and combining the two or more output signals including the first output signal and the second output signal using an output combiner to generate a combined output signal in which the nonlinearity is canceled.

13. The method of claim 12, further comprising: scaling the input signal by a third input scaling factor to generate a third scaled input signal for a third circuit block of a third circuit channel; and generating a third output signal of the two or more output signals based on scaling an output of the third circuit block by a third output scaling factor.

14. The method of claim 12, wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.

15. The method of claim 14, wherein the input signal is an analog or radio frequency signal and the output signal is a digital signal.

16. The method of claim 12, wherein a plurality of input scaling factors including the first input scaling factor and the second input scaling factor define a matrix, and wherein a plurality of output scaling factors including the first output scaling factor and the second output scaling factor are based on an inverse of the matrix.

17. The method of claim 12, wherein the nonlinearity is a harmonic distortion component.

18. The method of claim 12, further comprising calibrating the first output scaling factor based on a detected value of the first input scaling factor and calibrating the second output scaling factor based on a detected value of the second input scaling factor.

19. The method of claim 12, wherein the second circuit channel further includes one or more additional circuit blocks in parallel with the second circuit block, the method further comprising providing each of the one or more additional circuit blocks the input signal scaled by the second input scaling factor, and generating the second output signal based on combining an output of each of the one or more additional circuit blocks with the output of the second circuit block.

20. The method of claim 12, wherein the second circuit block is a replica of the first circuit block.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1A is a schematic diagram of an electronic system according to one embodiment.

[0007] FIG. 1B is a schematic diagram of an electronic system according to another embodiment.

[0008] FIG. 2 is a schematic diagram of a data conversion system according to one embodiment.

[0009] FIG. 3A is a schematic diagram of a data conversion system according to another embodiment.

[0010] FIG. 3B is a schematic diagram of a data conversion system according to another embodiment.

[0011] FIG. 4 is a schematic diagram of an electronic system according to another embodiment.

[0012] FIG. 5A is a schematic diagram of one embodiment of a phased array antenna system.

[0013] FIG. 5B is a schematic diagram of one embodiment of a receive slice for the phased array antenna system of FIG. 5A.

DETAILED DESCRIPTION

[0014] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to drawings. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

[0015] Apparatus and methods for nonlinearity cancellation in electronic systems are disclosed. In certain embodiments, an electronic system includes two or more circuit channels that process a common input signal in parallel and that each include at least one instantiation of a circuit that behaves nonlinearly. Thus, the nonlinear circuit is replicated and included at least once in each circuit channel. Each of the circuit channels has an input scaling factor and an output scaling factor that can vary from one circuit channel to another. The output signals from the circuit channels after scaling are combined to generate a combined output signal. The input and output scaling factors are selected to cancel or reduce nonlinearities.

[0016] Accordingly, by selecting suitable values of the input scaling factors and output scaling factors, nonlinear cancellation can be achieved. For example, the teachings herein can be used to cancel or reduce various nonlinearities including, but not limited to, third-order nonlinearity such as third-order harmonic distortion.

[0017] In contrast to calibration schemes which suffer from additive sequences and/or a convergence delay, the nonlinearity cancellation schemes herein can have relatively low complexity and/or high speed.

[0018] The nonlinearity cancellation techniques can be applied to a wide variety of electronic systems, including, for example, data conversion systems. For instance, in some implementations, the circuit that behaves nonlinearly corresponds to an analog-to-digital converter (ADC) that is replicated and included in the circuit channels.

[0019] Another application of the teachings herein is to mitigate the effects of harmonic distortion in a phased array antenna system. For example, a phased array antenna system can include multiple transmit and/or receive channels for processing an input signal received from an antenna array. Although the number of receivers in a phased array system can be increased to boost array gain and improve noise and single-tone spurious performance, intermodulation products can remain correlated and thus not improve with array gain. Accordingly, nonlinearity such as intermodulation distortion can be an increasingly dominant performance concern in phased array systems. The teachings herein can be used in phased arrays and/or other electronic systems to cancel or reduce intermodulation distortion.

[0020] FIG. 1A is a schematic diagram of an electronic system 10 according to one embodiment. The electronic system 10 includes input modulators 3a, 3b, . . . 3k, circuit blocks 6a, 6b, . . . 6k, output modulators 4a, 4b, . . . 4k, and an output combiner 5.

[0021] In the illustrated embodiment, the electronic system 10 includes J+1 circuit channels, where J is an integer greater than or equal to 1. Each circuit channel includes a corresponding input modulator, circuit block, and output modulator. Additionally, each of the circuit blocks 6a, 6b, . . . 6k are replicas of one another, and can correspond to a circuit that ideally has a linear relationship. However, due to various nonidealities, the circuit blocks 6a, 6b, . . . 6k exhibit nonlinear characteristics.

[0022] As shown in FIG. 1A, the electronic system 10 includes an input that receives an input signal x.sub.in, which in certain implementations is an analog or radio frequency (RF) signal. The input signal x.sub.in is provided to each of the input modulators 3a, 3b, . . . 3k, which scale the input signal x.sub.in by input scaling factors S.sub.0,0, S.sub.1,0 . . . S.sub.J,0, respectively. The input scaling factors S.sub.0,0, S.sub.1,0 . . . S.sub.J,0 are also referred to herein as modulation factors.

[0023] With continuing reference to FIG. 1A, the scaled input signals are provided to the circuit blocks 6a, 6b, . . . 6k, which can correspond to a wide variety of types of electronic circuits including, but not limited to, ADCs. The circuit blocks 6a, 6b, . . . 6k generate output signals that are provided to the output modulators 4a, 4b, . . . 4k, which scale the output signals by output scaling factors S.sub.0,1, S.sub.1,1 . . . S.sub.J,1, respectively. The output scaling factors S.sub.0,1, S.sub.1,1 . . . S.sub.J,1, are also referred to herein as demodulation factors.

[0024] As shown in FIG. 1A, the scaled output signals are combined by the output combiner 5 to generate a combined output signal y.sub.out at an output.

[0025] In the illustrated embodiment, the circuit blocks 6a, 6b, . . . 6k correspond to replicas of one another and process the same input signal x.sub.in in parallel but with different input scaling factors. Although the transfer function of the circuit blocks 6a, 6b, . . . 6k behaves nonlinearly, the values of the input scaling factors S.sub.0,0, S.sub.1,0 . . . S.sub.J,0 and the output scaling factors S.sub.0,1, S.sub.1,1 . . . S.sub.J,1 can be selected to cancel or otherwise reduce nonlinearities. For example, by appropriate selection of the scaling factors, the combined output signal y.sub.out can have an improved linear relationship with respect to the input signal x.sub.in even though each of the circuit blocks 6a, 6b, . . . 6k has a nonlinear transfer function. Accordingly, appropriate selection of the scaling factors results in one or more nonlinearities being canceled from the combined output signal y.sub.out.

[0026] Selection of suitable scaling factors to achieve nonlinearity cancellation will be discussed in detail further below with reference to the examples of FIGS. 3A-3B.

[0027] FIG. 1B is a schematic diagram of an electronic system 20 according to another embodiment. The electronic system 20 includes input modulators 3a, 3b, . . . 3k, circuit blocks 6a1, 6a2, . . . 6ax, 6b1, 6b2, . . . 6by, . . . 6k1, 6k2, . . . 6kz, combiners 7a, 7b, . . . 7k, output modulators 4a, 4b, . . . 4k, and an output combiner 5. The values of x, y, and z and the corresponding number of circuit blocks can be selected to be any positive integer values desired for a particular application. The values of x, y, and z can be the same or different, depending on implementation. The values of x, y, and z are also referred to as the number of subchannels associated with each of the channels.

[0028] The electronic system 20 of FIG. 1B is similar to the electronic system 10 of FIG. 1A, except that the electronic system 20 of FIG. 1B includes multiple circuit blocks that are placed in parallel in each circuit channel and scaled by the same input scaling factor and output scaling factor. For example, the electronic system 20 of FIG. 1B includes J+1 circuit channels, with each circuit channel including multiple copies of the nonlinear circuit block in parallel to operate as subchannels.

[0029] For example, in the embodiment of FIG. 1B, the circuit blocks 6a1, 6a2, . . . 6ax are each scaled by a scaling factor S.sub.0,0 using the input modulator 3a. Additionally, the output signals from the circuit blocks 6a1, 6a2, . . . 6ax are combined using the combiner 7a and thereafter scaled by a scaling factor S.sub.0,1 using the output modulator 4a. Similarly, the circuit blocks 6b1, 6b2, . . . 6by are each scaled by a scaling factor S.sub.1,0 using the input modulator 3b. The output signals from the circuit blocks 6b1, 6b2, . . . 6by are combined using the combiner 7b and thereafter scaled by a scaling factor S.sub.1,1 using the output modulator 4b. Furthermore, the circuit blocks 6k1, 6k2, . . . 6kz are each scaled by a scaling factor S.sub.J,0 using the input modulator 3k. The output signals from the circuit blocks 6k1, 6k2, . . . 6kz are combined using the combiner 7k and thereafter scaled by a scaling factor S.sub.J,1 using the output modulator 4k.

[0030] By including multiple circuit blocks in parallel and scaled using the same scaling factors, the noise per channel can be reduced. Furthermore, parallelizing the circuit blocks in this manner can change the path gain and therefore change the scaling factors needed to achieve nonlinearity cancellation. Thus, the number of circuit blocks in parallel for each circuit channel can be strategically selected based on constraints on noise and/or desired scaling factors associated with a particular application.

[0031] Any of the embodiments herein can include one or more circuit channels in which nonlinear circuit blocks are connected in parallel.

[0032] FIG. 2 is a schematic diagram of a data conversion system 40 according to one embodiment. The data conversion system 40 includes input modulators 3a, 3b, . . . 3k, ADCs 26a, 26b, . . . 26k, output modulators 4a, 4b, . . . 4k, and an output combiner 5.

[0033] The data conversion system 40 of FIG. 2 is similar to the electronic system 10 of FIG. 1A, except that the data conversion system 40 of FIG. 2 implements the electronic circuits 6a, 6b, . . . 6k of FIG. 1A as ADCs 26a, 26b, . . . 26k. Thus, each circuit channel includes an ADC, in this embodiment.

[0034] The ADCs 26a, 26b, . . . 26k operate in parallel with one another to process an analog input signal x(t) to generate a digital output signal y[n]. The ADCs 26a, 26b, . . . 26k are associated with any desired number of parallel subchannels N.sub.0, N.sub.1, . . . N.sub.J, respectively. The ADCs 26a, 26b, . . . 26k are modeled using switches 31a, 31b, . . . 31k, transfer functions 32a, 32b, . . . 32k, delta scale factors 33a, 33b, . . . 33k, and additive error sources 34a, 34b, . . . 34k. Additionally, the delta scale factors 33a, 33b, . . . 33k provide 1/ scaling, while the additive error sources 34a, 34b, 34k provide additive noise e.sub.0,1[n], e.sub.1,i[n], . . . e.sub.J,i[n], respectively. The delta scale factors 33a, 33b, . . . 33k and the additive error sources 34a, 34b, 34k collectively represent quantizers of the ADCs 26a, 26b, . . . 26k, respectively.

[0035] The transfer functions 32a, 32b, . . . 32k of FIG. 2 can be represented as f(w)=w+a.sub.2w.sup.2+a.sub.3w.sup.3+ . . . , and the harmonic distortion (HD) components desired to be canceled can correspond to HDp.sub.0, . . . HDp.sub.J-1, where p.sub.0, . . . p.sub.J-1 are integers greater than 1. Additionally, the output signal y[n] of the data conversion system 40 can be represented using Equation 1 below.

[00001]$\begin{array}{cc}y\left[n\right]=\frac{1}{}x\left[n\right]\left(N_0{S}_{0,0}{S}_{0,1}+.Math.+N_J{S}_{J,0}{S}_{J,1}\right)+\frac{a_2}{}{x}^2\left[n\right]\left(N_0{S}_{0,0}^2{S}_{0,1}+.Math.+N_J{S}_{J,0}^2{S}_{J,1}\right)+\frac{a_3}{}{x}^3\left[n\right]\left(N_0{S}_{0,0}^3{S}_{0,1}+.Math.+N_J{S}_{J,0}^3{S}_{J,1}\right)+.Math.+S_{0,1}\underset{i=0}{\overset{N_0-1}{.Math.}}{e}_{0,i}\left[n\right]+S_{1,1}\underset{i=0}{\overset{N_1-1}{.Math.}}{e}_{1,i}\left[n\right]+.Math.+S_{J,1}\underset{i=0}{\overset{N_J-1}{.Math.}}{e}_{J,i}\left[n\right]& \mathrm{Equation}1\end{array}$

[0036] The expression above for Equation 1 can be more compactly written using Equation 2 below.

[00002]$\begin{array}{cc}y\left[n\right]=\frac{1}{}\underset{p=1}{\overset{}{.Math.}}{a}_p{x}^p\left[n\right]\left(N_0{S}_{0,0}^p{S}_{0,1}+.Math.+N_J{S}_{J,0}^p{S}_{J,1}\right)+\underset{j=0}{\overset{J}{.Math.}}\underset{i=0}{\overset{N_j-1}{.Math.}}{S}_{j,1}{e}_{j,i}\left[n\right]& \mathrm{Equation}2\end{array}$

[0037] In Equation 2, the term

[00003]$\left(N_0{S}_{0,0}^p{S}_{0,1}+.Math.+N_J{S}_{J,0}^p{S}_{J,1}\right)$

is desired to be 1 for p=1 and 0 for p=p.sub.0, . . . p.sub.J-1. This can be expressed using Equation 3 below, where a matrix S is defined.

[00004]$\begin{array}{cc}\underset{\stackrel{}{=}S}{\underset{}{\left[\begin{array}{cccc}{S}_{0,0}& S_{1,0}& .Math.& S_{J,0}\\ S_{0,0}^{p_0}& S_{1,0}^{p_0}& .Math.& S_{J,0}^{p_0}\\ .Math.& .Math.& & .Math.\\ S_{0,0}^{p_{J-1}}& S_{1,0}^{p_{J-1}}& .Math.& S_{J,0}^{p_{J-1}}\end{array}\right]}}\left[\begin{array}{c}{N}_0{S}_{0,1}\\ N_1{S}_{1,1}\\ .Math.\\ N_J{S}_{J,1}\end{array}\right]=\left[\begin{array}{c}1\\ 0\\ .Math.\\ 0\end{array}\right]& \mathrm{Equation}3\end{array}$

[0038] Accordingly, arbitrary values of the input scaling factors S.sub.0,0, S.sub.1,0 . . . S.sub.J,0 can be selected so long as the matrix S is invertible. Additionally, the output scaling factors S.sub.0,1, S.sub.1,1 . . . S.sub.J,1 for nonlinearity cancellation can be expressed using Equation 4 below.

[00005]$\begin{array}{cc}\left[\begin{array}{c}{N}_0{S}_{0,1}\\ N_1{S}_{1,1}\\ .Math.\\ N_J{S}_{J,1}\end{array}\right]=S^{-1}\left[\begin{array}{c}1\\ 0\\ .Math.\\ 0\end{array}\right]& \mathrm{Equation}4\end{array}$

[0039] With continuing reference to FIG. 2, the scaling factors can be selected to achieve cancellation of unwanted harmonic distortion components.

[0040] In certain embodiments, J+1 circuit channels are used to cancel J harmonic distortion components.

[0041] For instance, in a first example, two circuit channels (for instance, each including an ADC) are used to cancel third-order harmonic distortion (HD.sub.3).

[0042] In a second example, three circuit channels are used to cancel both second-order harmonic distortion (HD.sub.2) and HD.sub.3.

[0043] In a third example, three circuit channels are used to cancel both HD.sub.3 and fifth-order harmonic distortion (HD.sub.5).

[0044] In a fourth example, four circuit channels are used, with S.sub.0,0=1, S.sub.0,1=1, S.sub.1,0=1 and S.sub.1,1=1, S.sub.2,0=i and S.sub.2,1=i, S.sub.3,0=i and S.sub.3,1=i. Implementing the coefficients in this manner can cancel all HD components except the 5th, the 9th, the 13th, etc. In this example, the coefficients for nonlinearity cancellation include complex numbers.

[0045] FIG. 3A is a schematic diagram of a data conversion system 60 according to another embodiment. The data conversion system 60 includes a first input modulator 3a, a second input modulator 3b, a first data conversion channel 52a, a second data conversion channel 52b, a first output modulator 4a, a second output modulator 4b, and an output combiner 5b. The first data conversion channel 52a includes a first ADC represented by a switch 53a and a transfer function 54a, while the second data conversion channel 52b includes a second ADC represented by a switch 53b and a transfer function 54b.

[0046] As shown in FIG. 3A, the first input modulator 3a provides a scaling factor S.sub.0,0, while the second input modulator 3b provides a scaling factor S.sub.1,0. Additionally, the first output modulator 4a provides a scaling factor S.sub.0,1, while the second output modulator 4b provides a scaling factor S.sub.1,1.

[0047] In the illustrated embodiment, the transfer functions 54a/54b are represented as w+a.sub.3w.sup.3, and the input and output scaling factors are selected to achieve cancellation of HD.sub.3. For example, the output signal y[n] can be given by Equation 5 below.

[00006]$\begin{array}{cc}y\left[n\right]=x\left[n\right]\left(S_{0,0}{S}_{0,1}+S_{1,0}{S}_{1,1}\right)+a_3{x}^3\left[n\right]\left(S_{0,0}^3{S}_{0,1}+S_{1,0}^3{S}_{1,1}\right)& \mathrm{Equation}5\end{array}$

[0048] To achieve cancellation of HD.sub.3, the Equation 6 can be solved.

[00007]$$\begin{gathered} \begin{array}{cc}{S}_{0,0}{S}_{0,1}+S_{1,0}{S}_{1,1}=1 \\ {S}_{0,0}^3{S}_{0,1}+S_{1,0}^3{S}_{1,1}=0& \mathrm{Equation}6\end{array} \end{gathered}$$

[0049] The expression of Equation 6 can be represented in matrix form using Equation 7 below, where a matrix S is defined.

[00008]$\begin{array}{cc}\underset{\stackrel{}{=}S}{\underset{}{\left[\begin{array}{cc}{S}_{0,0}& S_{1,0}\\ S_{0,0}^3& S_{1,0}^3\end{array}\right]}}\left[\begin{array}{c}{S}_{0,1}\\ S_{1,1}\end{array}\right]=\left[\begin{array}{c}1\\ 0\end{array}\right]& \mathrm{Equation}7\end{array}$

[0050] With continuing reference to FIG. 3A, the values of the output scaling factors S.sub.0,1 and S.sub.1,1 can be found by solving Equation 8 below. The values of the input scaling factors S.sub.0,0 and S.sub.1,0 can be selected to be any values, so long as the matrix S is invertible.

[00009]$\begin{array}{cc}\left[\begin{array}{c}{S}_{0,1}\\ S_{1,1}\end{array}\right]=S^{-1}\left[\begin{array}{c}1\\ 0\end{array}\right]& \mathrm{Equation}8\end{array}$

[0051] For example, when the input scaling factors S.sub.0,0=1 and S.sub.1,0=0.5, then the values of the output scaling factors to achieve HD.sub.3 cancellation correspond to S.sub.0,1=0.3334 and S.sub.1,1=2.6667, as annotated in FIG. 3A. In another example, when the input scaling factors S.sub.0,0=1 and S.sub.1,0=1.5, then the values of the output scaling factors to achieve HD.sub.3 cancellation correspond to S.sub.0,1=1.8 and S.sub.1,1=0.5334.

[0052] Accordingly, the selection of the input scaling factors and/or the number of circuit channels can be selected such the matrix S is invertible (for example, having a condition number less than a threshold). Further, the selection of the input scaling factors can be made to provide output scaling factors of desired values for nonlinearity cancellation. For example, certain scaling factors can be more suitable for implementation in an electronic system due to circuit design considerations and/or other factors.

[0053] FIG. 3B is a schematic diagram of a data conversion system 70 according to another embodiment. The data conversion system 70 includes a first input modulator 3a, a second input modulator 3b, a first data conversion channel 62a, a second data conversion channel 62b, a first output modulator 4a, a second output modulator 4b, and an output combiner 5b. The first data conversion channel 62a includes a first ADC represented by a switch 63a and a transfer function 64a, while the second data conversion channel 52b includes a second ADC and a third ADC in parallel. The second ADC is represented by a switch 63b1 and a transfer function 64b1, while the third ADC is represented by a switch 63b2 and a transfer function 64b2. The output of the second ADC and the third ADC are combined using combiner 65.

[0054] The data conversion system 70 of FIG. 3B is similar to the data conversion system 60 of FIG. 3A, except that the data conversion system 70 implements the second data conversion channel 62b using two parallel ADCs.

[0055] By implementing the second data conversion channel in this manner, the transfer function of the data conversion system 70 is changed, which results in a different selection of scaling factors to achieve HD.sub.3 cancellation.

[0056] For example, when representing the transfer functions 64a/64b as w+a.sub.3w.sup.3, the output signal y[n] can be given by Equation 9 below.

[00010]$\begin{array}{cc}y\left[n\right]=x\left[n\right]\left(S_{0,0}{S}_{0,1}+2S_{1,0}{S}_{1,1}\right)+a_3{x}^3\left[n\right]\left(S_{0_{}0}^3{S}_{0_{}1}+2S_{1_{}0}^3{S}_{1,1}\right)& \mathrm{Equation}9\end{array}$

[0057] To achieve HD.sub.3 cancellation, the scaling factors can be selected in accordance with Equation 10 below.

[00011]$$\begin{gathered} \begin{array}{cc}{S}_{0,0}{S}_{0,1}+2S_{1,0}{S}_{1,1}=1 \\ {S}_{0,0}^3{S}_{0,1}+2S_{1,0}^3{S}_{1,1}=0& \mathrm{Equation}10\end{array} \end{gathered}$$

[0058] The expression of Equation 10 can be represented in matrix form using Equation 11, which defines a matrix S.

[00012]$\begin{array}{cc}\underset{\stackrel{}{=}S}{\underset{}{\left[\begin{array}{cc}{S}_{0,0}& S_{1,0}\\ S_{0,0}^3& S_{1,0}^3\end{array}\right]}}\left[\begin{array}{c}{S}_{0,1}\\ 2S_{1,1}\end{array}\right]=\left[\begin{array}{c}1\\ 0\end{array}\right]& \mathrm{Equation}11\end{array}$

[0059] The values of the output scaling factors S.sub.0,1 and S.sub.1,1 can be found by solving Equation 12 below. The values of the input scaling factors S.sub.0,0 and S.sub.1,0 can be selected to be any values, so long as the matrix S is invertible.

[00013]$\begin{array}{cc}\left[\begin{array}{c}{S}_{0,1}\\ 2S_{1,1}\end{array}\right]=S^{-1}\left[\begin{array}{c}1\\ 0\end{array}\right]& \mathrm{Equation}12\end{array}$

[0060] For example, when the input scaling factors S.sub.0,0=1 and S.sub.1.0=0.5, then the values of the output scaling factors to achieve HD.sub.3 cancellation correspond to S.sub.0,1=0.3334 and S.sub.1,1=1.3334, as annotated in FIG. 3B.

[0061] As shown by a comparison of the example scaling factors annotated in 3A and FIG. 3B, the scaling factors for HD.sub.3 cancellation can change when circuit blocks are placed in parallel for a given circuit channel. Thus, parallelization of circuit blocks, such as ADCs, is an effective technique to achieve output scaling factors desired for a particular application. Further, placing the circuit blocks in parallel can achieve a reduction in noise.

[0062] FIG. 4 is a schematic diagram of an electronic system 100 according to another embodiment. The electronic system 100 includes input modulators 3a, 3b, . . . 3k, circuit blocks 6a, 6b, . . . 6k, output modulators 4a, 4b, . . . 4k, an output combiner 5, and a calibration circuit 91.

[0063] The electronic system 100 of FIG. 4 is similar to the electronic system 10 of FIG. 1, except that the electronic system 100 further includes the calibration circuit 91.

[0064] In the illustrated embodiment, the calibration circuit 91 detects the values of input scaling factors S.sub.0,0, S.sub.1,0 . . . S.sub.J,0 including any variation in the input scaling factors arising from process, temperature, and/or voltage (PVT) variation. Additionally, the detected input scaling factors are used to generate output scaling factors S.sub.0,1, S.sub.1,1 . . . S.sub.J,1, which are calibrated to account for the PVT variation.

[0065] FIG. 5A is a schematic diagram of one embodiment of a phased array antenna system 110. The phased array antenna system 110 includes a digital processing circuit 101, a data conversion circuit 102, a transceiver 103, RF front ends 105a, 105b, . . . 105n, and an antenna array including antennas 106a, 106b, . . . 106n. Although an example system with three RF front ends and three antennas is illustrated, the phased array antenna system 110 can include more or fewer RF front ends and/or more or fewer antennas as indicated by the ellipses. Furthermore, in certain implementations, the phased array antenna system 110 is implemented with separate antennas for transmitting and receiving signals.

[0066] The phased array antenna system 110 illustrates one embodiment of an electronic system that can be implemented with nonlinearity cancellation in accordance with the teachings herein. For example, although the number of receivers in a phased array system can be increased to boost array gain and improve noise and single-tone spurious performance, intermodulation products can remain correlated and thus not improve with array gain. Accordingly, nonlinearity such as intermodulation distortion can be an increasingly dominant performance concern in phased array systems. The teachings herein can be used in such a phased array antenna system to cancel or reduce nonlinearities including, but not limited to, HD.sub.3.

[0067] Although nonlinearity cancellation can be applied to phased array antenna system 110, the nonlinearity cancellation schemes disclosed herein can be used in a wide range of electronics. A phased array antenna system is also referred to herein as an active scanned electronically steered array or beamforming communication system.

[0068] As shown in FIG. 5A, the transceiver 103 is coupled to antennas 106a, 106b, . . . 106n through RF front ends 105a, 105b, . . . 105n, respectively. The transceiver 103 includes a frequency up/down conversion circuit 108 and a phase and amplitude control circuit 109, in this embodiment. The transceiver 103 provides RF signal processing of RF signals transmitted and received. In the illustrated embodiment, each communication channel is associated with a corresponding RF front end and antenna. However, other implementations are possible.

[0069] With continuing reference to FIG. 5A, the digital processing circuit 101 generates digital transmit data for controlling a transmit beam radiated from the antennas 106a, 106b, . . . 106n. The digital processing circuit 101 also processes digital receive data representing a receive beam received by the antennas 106a, 106b, . . . 106n in response to a received radio wave. In certain implementations, the digital processing circuit 101 includes one or more baseband processors.

[0070] As shown in FIG. 5A, the digital processing circuit 101 is coupled to the data conversion circuit 102, which can include digital-to-analog converter (DAC) circuitry for converting digital transmit data to one or more baseband transmit signals and analog-to-digital converter (ADC) circuitry for converting one or more baseband receive signals to digital receive data.

[0071] The frequency up/down conversion circuit 108 provides frequency upshifting from baseband to RF and frequency downshifting from RF to baseband, in this embodiment. However, other implementations are possible, such as configurations in which the phased array antenna system 110 operates in part at an intermediate frequency (IF) or in which RF data converters provide direct conversion between digital and RF.

[0072] The transceiver 103 also includes the phase and/or amplitude control circuit 109 for controlling gain and phase for beamforming and/or other desired functions, in this embodiment. However other implementations are possible. For example, beamforming can be implemented in all or part in the digital domain (for instance, in the digital processing circuit 101).

[0073] With respect to signal transmission, the RF signals radiated from the antennas 106a, 106b, . . . 106n aggregate through constructive and destructive interference to collectively generate a transmit beam having a particular direction. With respect to signal reception, a receive beam is generated by combining the RF signals received from the antennas 106a, 106b, . . . 106n after amplitude scaling and/or phase shifting.

[0074] Phased array antenna systems are used in a wide variety of applications including, but not limited to, mobile communications, military and defense systems, and/or radar technology.

[0075] FIG. 5B is a schematic diagram of one embodiment of a receive slice 130 for the phased array antenna system 110 of FIG. 5A. The receive slice 130 is coupled to an antenna 116, and includes a digital processing circuit 111, a data conversion circuit 112, an RF downconversion circuit 113, and a front-end 115.

[0076] In the illustrated embodiment, the front-end system includes a low noise amplifier 122 and a transmit/receive switch 121 for selectively connecting an input of the low noise amplifier 122 to the antenna 116. The RF downconversion circuit 113 includes an input filter 123, a downconverting mixer 124, a receive amplifier 125, an output filter 126, and a local oscillator 127. The input filter 123 is coupled to an output of the low noise amplifier 122, and generates a filtered RF receive signal that is provided to the downconverting mixer 124. The downconverting mixer 124 downconverts the filtered RF receive signal using a local oscillator clock signal from the local oscillator 127 to generate a downconverted receive signal. The downconverted receive signal is amplified by the receive amplifier 125 and filtered by the output filter 126 to generate an input signal x.sub.in for the data conversion circuit 112.

[0077] With continuing reference to FIG. 5B, the conversion circuit 112 is implemented using input modulators 3a, 3b, . . . 3k for scaling the input signal x.sub.in provided to ADCs 26a, 26b, . . . 26k. Additionally, the digital processing circuit 111 includes output modulators 4a, 4b, . . . 4k for scaling the output signals from each of the ADCs 26a, 26b, . . . 26k, respectively, and a combiner 5 for combing the scaled output signals to generate an output signal y.sub.out.

[0078] By selecting suitable scaling factors, nonlinear components (for instance, HD.sub.3 or other harmonic distortion components) can be reduced or eliminated from the output signal y.sub.out.

CONCLUSION

[0079] The foregoing description may refer to elements or features as being connected or coupled together. As used herein, unless expressly stated otherwise, connected means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, coupled means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

[0080] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

[0081] Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.