SEMICONDUCTOR DEVICE

Abstract

A semiconductor device may include a substrate, source/drain electrodes on the substrate, a channel layer on the source/drain electrodes, a barrier film on the channel layer, a gate electrode on the barrier film, and an intermediate layer between a corresponding one of the source/drain electrodes and the channel layer, the intermediate layer including metal oxide, wherein the channel layer may include an oxide semiconductor material, and the oxide semiconductor material may include tellurium (Te) oxide and one or more oxides of sulfur (S) or selenium (Se).

Claims

1. A semiconductor device comprising: a substrate; source/drain electrodes on the substrate; a channel layer on the source/drain electrodes; a barrier film on the channel layer; a gate electrode on the barrier film; and an intermediate layer between a corresponding one of the source/drain electrodes and the channel layer, the intermediate layer including metal oxide, wherein the channel layer includes an oxide semiconductor material, and the oxide semiconductor material includes tellurium (Te) oxide and one or more oxides of sulfur (S) or selenium (Se).

2. The semiconductor device of claim 1, wherein a work function of the intermediate layer is smaller than a work function of the channel layer and greater than a work function of the gate electrode.

3. The semiconductor device of claim 1, wherein a ratio (W.sub.I/W.sub.C) of a work function (W.sub.I) of the intermediate layer to a work function (W.sub.C) of the channel layer is 0.5 or more and less than 1.

4. The semiconductor device of claim 1, wherein a ratio (W.sub.I/W.sub.G) of a work function (W.sub.I) of the intermediate layer to a work function (W.sub.G) of the gate electrode is more than 1 and 2 or less.

5. The semiconductor device of claim 1, wherein the metal oxide has an oxygen deficient composition.

6. The semiconductor device of claim 5, wherein the metal oxide includes one or more selected from the group consisting of WOx, MoOx, InOx, SnOx, and GaOx.

7. The semiconductor device of claim 1, wherein a ratio (T1/T2) of a thickness (T1) of the intermediate layer to a thickness (T2) of the channel layer is 0.001 or more and 10 or less.

8. The semiconductor device of claim 1, wherein a thickness of the intermediate layer of 0.1 nm or more and 10 nm or less.

9. The semiconductor device of claim 1, wherein a thickness (T1) of the intermediate layer is smaller than a thickness (T2) of the channel layer.

10. The semiconductor device of claim 1, wherein the intermediate layer surrounds at least a portion of the source/drain electrodes.

11. The semiconductor device of claim 1, wherein the oxide semiconductor material is of a p-type.

12. The semiconductor device of claim 1, wherein the oxide semiconductor material is amorphous.

13. The semiconductor device of claim 1, wherein the oxide semiconductor material has an oxygen-deficient composition.

14. The semiconductor device of claim 13, wherein moles of oxygen (O) per one mole of tellurium (Te) in the oxide semiconductor material are 0.8 to 1.7.

15. The semiconductor device of claim 1, wherein the oxide semiconductor material is represented by the following Chemical formula 1:
Te.sub.aQ.sub.bO.sub.x[Chemical Formula 1] in Chemical formula 1, Q is one or more of sulfur (S) or selenium (Se), and 0<a1, 0<b1, and 0<x4.

16. The semiconductor device of claim 15, wherein the oxide semiconductor material includes Q in an amount of 0.5 at % to 5 at % relative to a total number of atoms of tellurium (Te), Q, and oxygen (O).

17. The semiconductor device of claim 1, wherein tellurium (Te) included in the oxide semiconductor material includes ionized tellurium and non-ionized tellurium.

18. The semiconductor device of claim 1, wherein the oxide semiconductor material includes selenium (Se), and the selenium (Se) includes ionized selenium.

19. A semiconductor device comprising: a substrate; an insulating layer on the substrate; source/drain electrodes on the substrate; a channel layer on the source/drain electrodes; a barrier film on the channel layer; a gate electrode on the barrier film; and an intermediate layer between a corresponding one of the source/drain electrodes and the channel layer, the intermediate layer including metal oxide, wherein the channel layer includes an oxide semiconductor material that includes one or more of sulfur (S), selenium (Se) or tellurium (Te) and has an oxygen-deficient composition.

20. A semiconductor device comprising: a substrate; an insulating layer on the substrate; source/drain electrodes on the insulating layer; a channel layer on the source/drain electrodes; a barrier film on the channel layer; a gate electrode on the barrier film; and an intermediate layer between a corresponding one of the source/drain electrodes and the channel layer, the intermediate layer surrounding at least a portion of the source/drain electrodes, the intermediate layer including metal oxide having an oxygen-deficient composition, wherein the channel layer includes a p-type oxide semiconductor material that includes one or more of sulfur (S), selenium (Se) or tellurium (Te), and has an oxygen-deficient composition and an amorphous structure, and a work function of the intermediate layer is smaller than a work function of the channel layer and greater than a work function of the gate electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings shown in the present disclosure are according to some example embodiments, and ratios of the width, height or thickness of each component is for describing the present disclosure in detail, and the ratio may be different from the actual ones. In addition, each component illustrated in the drawings may be exaggerated to describe the present disclosure in detail. In addition, in a coordinate system shown in the drawing, each axis may be perpendicular to the others, a direction pointed by an arrow may be a + direction, and a direction opposite to the direction pointed by the arrow (a direction rotated by 180 degrees) may be a direction, in which:

[0011] FIG. 1 is a plan view showing at least a portion of a semiconductor device according to an example embodiment of the present disclosure; and

[0012] FIG. 2 is an enlarged view of area A in FIG. 1.

DETAILED DESCRIPTION OF EMBODIMENTS

[0013] Unless specifically limited in the present specification, the units of properties may follow the International System of Units (SI).

[0014] As used herein, expressions such as one of, one or more of, any one of, and at least one of, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, both at least one of A, B, or C and at least one of A, B, and C mean either A, B, C or any combination thereof. Likewise, A and/or B means A, B, or A and B.

[0015] While the term same, equal or identical is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., 10%).

[0016] When the term about, substantially or approximately is used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., 10%) around the stated numerical value. Moreover, when the word about, substantially or approximately is used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as about or substantially, it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., 10%) around the stated numerical values or shapes.

[0017] FIG. 1 is a plan view showing at least a portion of a semiconductor device 10 according to an example embodiment of the present disclosure. FIG. 2 is an enlarged view of area A of FIG. 1.

[0018] In an example embodiment of the present specification, a first direction D1 may refer to a direction perpendicular to a surface 100S of a substrate 100. The second direction D2 may intersect the first direction D1. In one example, the second direction D2 may refer to a direction parallel to the surface 100S of the substrate 100.

[0019] In one example, a semiconductor device 10 may include a substrate 100, source/drain electrodes 120, a channel layer 130, a barrier film 140, a gate electrode 150, and an intermediate layer 200.

[0020] In one example, the semiconductor device 10 may be applied to the semiconductor field, the display field, or the solar cell field. In one example, the semiconductor device 10 may be one selected from the group consisting of a system large scale integration (LSI), flash memory, dynamic random-access memory (DRAM), state RAM (SRAM), electrically erasable programmable read-only-memory (EEPROM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), and resistive RAM (RRAM). In one example, the semiconductor device 10 may include a plurality of individual devices of various types. The plurality of individual devices may not be particularly limited as the devices are those used in the art, and may, for example, include a metal-oxide-semiconductor field effect transistor (MOSFET), such as a complementary metal-oxide semiconductor (CMOS) transistor or the like or an image sensor, such as a CMOS imaging sensor (CIS) or the like, an active device, a passive device, or the like. In one example, the semiconductor device 10 may include a thin film transistor (TFT), and the structure of the thin film transistor in one example may refer to FIG. 1.

[0021] In one example, the substrate 100 may be a silicon semiconductor substrate, a plastic substrate, a glass substrate, a compound semiconductor substrate, a ceramic substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. In one example, the substrate 100 may include, although not illustrated separately, an impurity region by doping, a peripheral circuit for selecting and controlling a memory cell, or the like.

[0022] In one example, the semiconductor device 10 may include an insulating film 110 disposed on the substrate 100. The insulating film 110 may include an insulating material. In the present specification, the insulating material may include one or more selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, low-k materials, and high-k materials, but is not limited thereto. In the present specification, the low-k material may have a permittivity less than 3.9, and may include, for example, one or more selected from the group consisting of fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), Bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethyleyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilil phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silazen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogels, silica xerogels, and mesoporous silica, but is not limited thereto. In the present specification, the high-k material may have a permittivity of 3.9 or higher, and may include, for example, one or more selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but is not limited thereto.

[0023] In one example, the source/drain electrodes 120 may be disposed on the substrate 100. The source/drain electrodes 120 may be disposed on the insulating film 110. There may be a plurality of source/drain electrodes 120, and each source/drain electrode 120 may be spaced apart from the other. Some of the plurality of source/drain electrodes 120 may be source electrodes and others may be drain electrodes.

[0024] In one example, the source/drain electrodes 120 may include impurities. Impurities may vary depending on the type of conductivity. For example, n-type source/drain electrodes 120 may include an n-type dopant, which is an impurity including at least one of phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). In addition, for example, p-type source/drain electrodes 120 may include a p-type dopant, which is an impurity including at least one of boron (B) or gallium (Ga). At least some of the plurality of source/drain electrodes 120 may be of an n-type or p-type. Some of the plurality of source/drain electrodes 120 may be of an n-type and the others may be of a p-type.

[0025] In one example, the source/drain electrodes 120 may include one or more selected from the group consisting of silicon, silicon doped with impurities, metal, metal nitride, metal silicide, and metal oxide. In the present specification, the metal may include one or more selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), calcium (Ca), ytterbium (Yb), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), rubidium (Ru), tungsten (W), molybdenum (Mo), nickel (Ni), tin (Sn), palladium (Pd), lead (Pb), and cobalt (Co). In the present specification, the metal nitride may include one or more selected from the group consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), and rubidium titanium nitride (RuTiN). In the present specification, the metal silicide may include one or more selected from the group consisting of titanium silicide (TiSi), tantalum silicide (TaSi), nickel silicide (NiSi), and cobalt silicide (CoSi). In the present specification, the metal oxide may include one or more selected from the group consisting of gold oxide (AuO.sub.x), platinum oxide (PtO.sub.x), silver oxide (AgO.sub.x), palladium oxide (PdO.sub.x), iridium oxide (IrO.sub.x), and rubidium oxide (RuO.sub.x).

[0026] In one example, the barrier film 140 may be disposed on the source/drain electrodes 120. The barrier film 140 may be disposed on the channel layer 130. In one example, the barrier film 140 may include one or more selected from the group consisting of metal oxide, silicon oxide, silicon nitride, silicon oxynitride, a low-k material, and a high-k material, but is not limited thereto. In one example, the metal oxide may include one or more selected from the group consisting of, for example, aluminum oxide (AlO) and tin oxide (SnO).

[0027] In one example, the gate electrode 150 may be disposed on the barrier film 140. The gate electrode 150 may be at least partially in non-contact with the source/drain electrodes 120. In one example, the gate electrode 150 may be electrically connected to a word line. In one example, the gate electrode 150 may include the aforementioned conductive material. In the present specification, the conductive material may include one or more selected from the group consisting of doped polysilicon, metal, metal nitride, metal silicide, and metal oxide.

[0028] In one example, the channel layer 130 may be disposed on the source/drain electrodes 120.

[0029] In one example, the channel layer 130 may include an oxide semiconductor material. The channel layer 130 may include one or more of sulfur (S) or selenium (Se), and may include tellurium (Te).

[0030] In one example, the oxide semiconductor material may include tellurium (Te) oxide. The oxide semiconductor material may include one or more oxides of sulfur (S) or selenium (Se). The oxide semiconductor material may include tellurium (Te) oxide and may further include one or more oxides of sulfur (S) or selenium (Se).

[0031] In one example, the oxide semiconductor material may be of a p type.

[0032] In one example, the oxide semiconductor material may be amorphous. Thereby, an on/off ratio of the semiconductor device 10 may be improved.

[0033] In one example, the oxide semiconductor material may have an oxygen deficient composition. In the present specification, oxygen deficiency may refer to a mismatch state in which a match ratio of an element combined with oxygen and oxygen in an oxide is not satisfied. For example, the mismatch state may refer to a state in which the octet rule or the 18-electron rule is not satisfied. For example, when a mismatch ratio of an element A combined with oxygen and oxygen O in an oxide is A:O=1:2, the oxide with an oxygen-deficient composition may satisfy AO.sub.2-x(0<x<2).

[0034] In one example, the channel layer 130 may include an oxide semiconductor material represented by the following Chemical formula 1.

Te.sub.aQ.sub.bO.sub.x[Chemical formula 1]

[0035] In Chemical formula 1, Q is one or more of sulfur (S) or selenium (Se), and 0<a1, 0<b1, and 0<x4 may be satisfied.

[0036] In Chemical formula 1, 0<a1, 0<b1, and 0<x<4 may be satisfied.

[0037] In Chemical formula 1, 0.8a/b1.2, 0.9a/b1.1, or 0.95a/b1.05 may be satisfied.

[0038] As described above, the oxide semiconductor material may include one or more of sulfur (S) or selenium (Se) and include tellurium (Te), and ratios a, b, and x between the elements and oxygen may be appropriately adjusted, thereby improving the hole field effect mobility and/or improving the on/off ratio of the semiconductor device 10.

[0039] In one example, the oxide semiconductor material may include the Q in Chemical formula 1 in an amount of about 0.5 at % to about 5 at %, about 1 at % to about 4.5 at %, or about 1.5 at % to about 4 at % relative to the total number of atoms of tellurium (Te), the Q, and the oxygen O. Thereby, the hole field effect mobility may be improved and/or the on/off ratio of the semiconductor device 10 may be improved.

[0040] In one example, moles of the oxygen O per one mole of tellurium (Te) in the oxide semiconductor material may be about 0.8 to about 1.7, about 1 to about 1.5, or about 1.1 to about 1.4. The oxide semiconductor material having a ratio of tellurium (Te) and oxygen (O) satisfying the above-described range may improve hole field effect mobility and/or improve the on/off ratio of the semiconductor device 10.

[0041] In one example, the tellurium (Te) included in the oxide semiconductor material may include ionized tellurium (Te) and non-ionized tellurium (Te). The ionized tellurium (Te) may include, for example, one or more of Te.sup.4+ or Te.sup.2+. The non-ionized tellurium (Te) may be represented as Te.sup.0. Thereby, a shallow acceptor state formed by the 5p orbital of tellurium (Te) may be used as a hole conduction channel.

[0042] In one example, the oxide semiconductor material may include selenium (Se), and the selenium (Se) may include ionized selenium. The ionized selenium (Se) may include, for example, Se.sup.2+. Therefore, the ionized selenium (Se) may passivate an oxygen-deficient portion, allowing a partially empty 4P state to be used as the hole conduction channel.

[0043] In one example, a thickness of the channel layer 130 may be about 2 nm or more and about 100 nm or less, about 3 nm or more and about 50 nm or less, about 4 nm or more and about 20 nm or less, or about 5 nm or more and about 15 nm or less, but is not particularly limited thereto. Thereby, the hole field effect mobility may be improved. The thickness of the channel layer 130 may refer to the length in the first direction D1, for example, with reference to FIG. 2.

[0044] In one example, the channel layer 130 may have a work function of about 4 eV or more and about 8 eV or less, about 4.5 eV or more and about 7.5 eV or less, about 5 eV or more and about 7 eV or less, or about 6 eV or more and about 6.95 eV or less. Thereby, the hole field effect mobility may be improved and/or the on/off ratio of the semiconductor device 10 may be improved.

[0045] In one example, the channel layer 130 may be formed by deposition, and the deposition may be performed through chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like.

[0046] For example, the channel layer 130 may be formed by thermal evaporation or sputtering. In one example, one or more of thermal evaporation or sputtering may be performed at a temperature of the substrate 100 of about 15 C. to about 35 C., for example, at room temperature. In one example, one or more of the thermal evaporation or sputtering may be performed under a vacuum pressure of less than about 10.sup.3 Torr to reduce or minimize impurities.

[0047] In one example, when forming the channel layer 130 through thermal evaporation, a thermal evaporation speed may be controlled to about 1 /s to about 100 /s in order to reduce or prevent a surface roughness of the channel layer 130 from increasing while reducing or minimizing a process time.

[0048] In one example, when forming the channel layer 130 through sputtering, a molar ratio of tellurium (Te) and oxygen (O) in the channel layer 130 may be controlled by adjusting a partial pressure of oxygen (O.sub.2) and argon (Ar) plasma. Then, the channel layer 130 formed through sputtering may be annealed in an air or oxygen atmosphere, depending on the case, and the annealing may be performed at a temperature of about 100 C. to about 300 C. Then, the annealing may be performed at a temperature ranging from room temperature to about 300 C. in air.

[0049] In one example, the intermediate layer 200 may be disposed between the source/drain electrodes 120 and the channel layer 130. The intermediate layer 200 may include metal oxide.

[0050] In one example, a work function of the intermediate layer 200 may be smaller than the work function of the channel layer 130 and greater than a work function of the gate electrode 150. Thereby, the problem of increased contact resistance (R.sub.cnt) due to the difference in work function between the channel layer 130 and the source/drain electrodes 120 may be reduced or prevented.

[0051] In one example, a ratio (W.sub.I/W.sub.C) of a work function W.sub.I of the intermediate layer 200 to a work function W.sub.C of the channel layer 130 may be about 0.5 or more and less than about 1, about 0.6 or more and about 0.95 or less, about 0.7 or more and about 0.9 or less, or about 0.8 or more and 0.88 or less. In one example, the ratio (W.sub.I/W.sub.G) of the work function W.sub.I of the intermediate layer 200 to the work function W.sub.G of the gate electrode 150 may be more than about 1 and about 2 or less, about 1.1 or more and about 1.8 or less, about 1.2 or more and about 1.6 or less, or about 1.3 or more and about 1.5 or less. Thereby, the problem of increased contact resistance (R.sub.cnt) due to the difference in work function between the channel layer 130 and the source/drain electrodes 120 may be reduced or prevented.

[0052] In one example, the intermediate layer 200 may have the work function of about 3 eV or more and about 7 eV or less, about 3.5 eV or more and about 6.8 eV or less, about 4 eV or more and about 6.7 eV or less, about 4.5 eV or more and about 6.6 eV or less, about 5 eV or more and about 6.4 eV or less, or about 5.5 eV or more and about 6.2 eV or less. Thereby, the problem of increased contact resistance (R.sub.cnt) due to the difference in work function between the channel layer 130 and the source/drain electrodes 120 may be reduced or prevented.

[0053] In one example, the metal oxide may have an oxygen deficient composition. The metal oxide may include one or more selected from the group consisting of tungsten oxide (WOx), molybdenum oxide (MoOx), indium oxide (InOx), tin oxide (SnOx), and gallium oxide (GaOx), but is not limited thereto. In the above-mentioned materials, x may be a number that does not satisfy a mismatch ratio of oxygen and the combined metal element.

[0054] In one example, the thickness of the intermediate layer 200 may be about 0.1 nm or more and about 10 nm or less, about 0.2 nm or more and about 9 nm or less, about 0.3 nm or more and about 8 nm or less, about 0.4 nm or more and about 7 nm or less, about 0.5 nm or more and about 6 nm or less, about 0.6 nm or more and about 5 nm or less, about 0.7 nm or more and about 4 nm or less, about 0.8 nm or more and about 3 nm or less, about 0.9 nm or more and about 2 nm or less, or about 0.95 nm or more and about 1.5 nm or less. Thereby, the hole field effect mobility may be improved and/or the on/off ratio of the semiconductor device 10 may be improved. The thickness of the intermediate layer 200 may refer to the length in the first direction D1, for example, with reference to FIG. 2.

[0055] In one example, a ratio (T1/T2) of a thickness T1 of the intermediate layer 200 to a thickness T2 of the channel layer 130 is about 0.001 or more and about 10 or less, about 0.01 or more and about 9 or less, about 0.05 or more and about 8 or less, about 0.1 or more and about 7 or less, about 0.3 or more and about 6 or less, about 0.5 or more and about 5 or less, about 0.6 or more and about 4 or less, about 0.7 or more and about 3 or less, about 0.8 or more and about 2 or less, or about 0.9 or more and about 1 or less, or 0.9.

[0056] In one example, the thickness T1 of the intermediate layer 200 may be smaller than the thickness T2 of the channel layer 130. In this case, for example, the ratio (T1/T2) of the thickness T1 of the intermediate layer 200 to the thickness T2 of the channel layer 130 may be about 0.001 or more to less than about 1, about 0.005 or more to less than about 1, about 0.01 or more to less than about 1, about 0.02 or more to less than about 1, about 0.03 or more to less than about 1, about 0.04 or more to less than about 1, about 0.05 or more to less than about 1, about 0.06 or more to less than about 1, about 0.07 or more to less than about 1, about 0.08 or more to less than about 1, about 0.09 or more to less than about 1, or about 0.1 or more to less than about 1.

[0057] In one example, the intermediate layer 200 may surround at least a portion of the source/drain electrodes 120. The intermediate layer 200 may be at least partially in contact with the source/drain electrodes 120. The channel layer 130 may not be in contact with the source/drain electrodes 120 due to the presence of the intermediate layer 200. In one example, the source/drain electrodes 120 may be at least partially in contact with the insulating layer 110. The intermediate layer 200 may be in contact with the source/drain electrodes 120 in at least some of regions that are not in contact with the insulating layer 110.

[0058] The present disclosure can provide a semiconductor device that secures good hole mobility characteristics and/or a high on/off ratio and/or reduces or minimizes leakage current.

[0059] Effects of the present disclosure are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0060] In the above, some example embodiments of the present disclosure have been described with reference to the accompanying drawings, but example embodiments of the present disclosure are not limited to the above example embodiments and may be manufactured in various different forms and those of ordinary skill in the art to which the present disclosure pertains may understand that the additional or alternative example embodiments may be embodied in other specific forms without departing from the technical spirit or essential features of the present disclosure. Therefore, it is to be appreciated that the example embodiments described above are intended to be illustrative in all respects and not restrictive.