ELECTRONIC COMPONENT

Abstract

A chip resistor comprises an insulating substrate (component body) on which a resistor is formed, a connection terminal (front electrodes, end face electrodes, and back electrodes) formed at both end portions of the insulating substrate, an under layer formed by electrolytic plating to cover the connection terminal, a barrier layer formed by electrolytic plating to cover the under layer, and an external connection layer which is mainly composed of tin and formed on a surface of the barrier layer, wherein the barrier layer is made of alloy plating mainly composed of nickel and containing 3% to 15% of phosphorus, and the under layer is formed of a copper plated layer that is at least either more malleable or more ductile than the barrier layer.

Claims

1. An electronic component comprising: a component body; a connection terminal formed on the component body; an under layer formed by electrolytic plating so as to cover the connection terminal; a barrier layer formed by electrolytic plating so as to cover the under layer; and an external connection layer which is mainly composed of tin and formed on a surface of the barrier layer, wherein the barrier layer is made of alloy plating in which 3% to 15% of phosphorus is added to nickel, and the under layer is a metal layer that is at least either more malleable or more ductile than the barrier layer.

2. The electronic component according to claim 1, wherein the under layer is made of copper or an alloy mainly composed of copper.

3. The electronic component according to claim 1, wherein a film thickness of the under layer is 3 μm to 25 μm.

4. The electronic component according to claim 1, wherein a magnetic layer is formed between the connection terminal and the barrier layer.

5. The electronic component according to claim 2, wherein a film thickness of the under layer is 3 μm to 25 μm.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a cross-sectional view of a chip resistor according to a first embodiment of the present invention.

[0016] FIG. 2A to 2F are a cross-sectional view illustrating producing processes of the chip resistor.

[0017] FIG. 3 is a cross-sectional view of a chip resistor according to a second embodiment of the present invention.

[0018] FIG. 4A to 4E are a cross-sectional view illustrating producing processes of the chip resistor.

DESCRIPTION OF EMBODIMENTS

[0019] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a chip resistor according to a first embodiment of the present invention.

[0020] As illustrated in FIG. 1, a chip resistor 10, which is an example of an electronic component, mainly includes a rectangular parallelepiped insulating substrate 1, a pair of front electrodes 2 formed at both end portions in the longitudinal direction on a surface of the insulating substrate 1, a resistor 3 formed so as to bridge between the pair of front electrodes 2, a protective layer 4 covering the entire of the resistor 3 and a portion of the front electrodes 2, a pair of back electrodes 5 formed at both end portions in the longitudinal direction on the back surface of the insulating substrate 1, a pair of end face electrodes 6 formed on both end faces in the longitudinal direction of the insulating substrate 1, each of which conducts between the corresponding one of the front electrodes 2 and the corresponding one of the back electrodes 5, a pair of under layers 7 each of which covers the corresponding one of the front electrodes 2, the corresponding one of the back electrodes 5, and the corresponding one of the end face electrodes 6, a pair of barrier layers 8 each of which covers the corresponding one of the under layers 7, and a pair of external connection layers 9 each of which covers the corresponding one of the barrier layers 8.

[0021] The insulating substrate 1 is a component body formed of ceramics and the like. A large-sized substrate, which will be described later, is divided into a plurality of pieces along a vertically extending groove and a horizontally extending groove, whereby the insulating substrate 1 is obtained.

[0022] The pair of front electrodes 2 is formed on the opposite short sides of the insulating substrate 1 with a predetermined interval therebetween. The pair of front electrodes 2 is obtained by screen-printing the Ag paste and drying and firing the printed paste.

[0023] The resistor 3 is obtained by screen-printing the resistive paste such as ruthenium oxide and drying and firing the printed paste. Both end portions of the resistor 3 overlap the front electrodes 2. A trimming groove (not illustrated) is formed in the resistor 3, thereby adjusting a resistance value of the resistor 3.

[0024] The protective layer 4 is composed of a double layer structure including an undercoat layer 4a and an overcoat layer 4b. The undercoat layer 4a is obtained by screen-printing and firing the glass paste, and is formed so as to cover the resistor 3 before the trimming groove is formed. The overcoat layer 4b is obtained by screen-printing the epoxy resin paste and heating and curing the printed paste, and is formed, after the trimming groove is formed on the resistor 3 from above the undercoat layer 4a, so as to cover, as a whole, the resistor 3 including the trimming groove, and the undercoat layer 4a.

[0025] The back electrodes 5 are formed on the back surface of the insulating substrate 1 at positions corresponding to the positions of the front electrodes 2 with a predetermined interval therebetween. The pair of back electrodes 5 is obtained by screen-printing the Ag paste and drying and firing the printed paste.

[0026] The pair of end face electrodes 6 is obtained by sputtering Ni—Cr on the end faces of the insulating substrate 1, or applying the Ag paste on the end faces of the insulating substrate 1 and heating and curing the applied paste. Each of the end face electrodes 6 is formed so as to conduct the corresponding one of the front electrodes 2 and the corresponding one of the back electrodes 5. The corresponding one of the front electrodes 2, the corresponding one of the end face electrodes 6, and the corresponding one of the back electrodes 5 constitute a connection terminal having a U-shaped cross section.

[0027] The pair of under layers 7 is a copper plated layer formed by electrolytic plating so as to cover the connection terminals. Forming the under layers 7 enables relaxation of the internal stress caused by formation of the barrier layers 8 by plating performed in the later process. Here, the under layers 7 having insufficient film thickness cause insufficient exhibition of effect of stress relaxation, while the under layers 7 formed so thick cause deterioration of cost and productivity. Accordingly, the film thickness of the under layers 7 is set in the range of 3 μm to 25 μm. The under layers 7 may be gold, silver, platinum, or an alloy containing either of them as a main component as long as they are formed as metal layers that are at least either more malleable or more ductile than the barrier layers 8, however, using copper or an alloy containing copper as a main component is more advantageous in terms of cost as compared to using the metals described above. Thus, in the present embodiment, layers formed of copper or an alloy containing copper as a main component are used.

[0028] The pair of barrier layers 8 is an alloy-plated layer (Ni—P plated layer) composed of mainly nickel (Ni) and containing phosphorus (P), which is formed by electrolytic plating so as to cover the under layers 7. The thickness of the barrier layers 8 is set in the range from 2 μm to 15 μm. Here, in the alloy plated layers forming the barrier layers 8, the more nickel contains phosphorus, the more diffusion toward the tin-plated layers forming the external connection layers 9 can be suppressed, while nickel having an insufficient content of phosphorus causes insufficient exhibition of effect of diffusion suppression. However, too much content of phosphorus increases the internal stress such that it cannot be relaxed even if providing the under layers 7. Accordingly, the content rate of phosphorus with respect to nickel in the barrier layer 8 is set in the range of 3% to 15%.

[0029] The pair of external connection layers 9 is a tin (Sn) plated layer formed by electrolytic plating so as to cover the barrier layers 8, and the thickness thereof is set in the range of 2 μm to 15 μm.

[0030] Next, a method of producing the chip resistor 10 having the structure described above will be described with reference to FIG. 2A to 2F.

[0031] Firstly, a large-sized substrate from which a plurality of pieces of insulating substrates 1 can be obtained is prepared. In the large-sized substrate, the primary division groove and the secondary division groove are provided in advance to form a grid pattern, and each one of the grids divided by the primary division groove and the secondary division groove serves as a single chip region. FIG. 2A to 2F illustrate a large-sized substrate 10A corresponding to a single chip region as a representative example, but practically, each process which will be described below is collectively performed with respect to the large-sized substrate corresponding to a plurality of pieces of chip regions.

[0032] That is, as illustrated in FIG. 2A, the Ag—Pd paste is screen-printed on a surface of the large-sized substrate 10A and then dried so as to form the pair of front electrodes 2, which faces each other with a predetermined interval therebetween, at both end portions in the longitudinal direction of each chip forming region. At the same time or around the same time, the Ag paste is screen-printed on the back surface of the large-sized substrate 10A and then dried so as to form the pair of back electrodes 5, which faces each other with a predetermined interval therebetween, at both end portions in the longitudinal direction of each chip forming region.

[0033] Next, as illustrated in FIG. 2B, the resistive paste containing ruthenium oxide or the like is screen-printed on the surface of the large-sized substrate 10A and then dried so as to form the resistor 3 whose both end portions overlap the front electrodes 2. Thereafter, the resistor 3 is fired at a high temperature of about 850° C. Next, the glass paste is screen-printed on an area covering the resistor 3 and then dried so as to form the undercoat layer 4a covering the resistor 3. Thereafter, the undercoat layer 4a is fired at a temperature of about 600° C. Next, a laser beam is irradiated from above the undercoat layer 4a so as to form a trimming groove (not illustrated) on the resistor 3, whereby a resistance value is adjusted. Thereafter, the epoxy-based resin paste is screen-printed from above the undercoat layer 4a, and then heated and cured at a temperature of about 200° C. so as to form the overcoat layer 4b. Thus, the protective layer 4 that is composed of a double layer structure including the undercoat layer 4a and the overcoat layer 4b is formed.

[0034] Next, the large-sized substrate 10A is primary-divided along the primary division groove to obtain a strip-shaped substrate 10B, then Ni/Cr is applied on the divided faces of the strip-shaped substrate 10B by sputtering. Thus, as illustrated in FIG. 2C, the end face electrodes 6 for connecting between the front electrodes 2 and the back electrodes 5 which are provided on both the front and back surfaces of the strip-shaped substrate 10B are formed. Note that the end face electrodes 6 may be formed by, instead of performing Ni/Cr sputtering, applying the Ag paste and heating and curing the applied paste.

[0035] Next, the strip-shaped substrate 10B is secondary-divided along the secondary division groove to obtain a plurality of chip-shaped substrates 10C, and then electrolytic plating is applied on these chip-shaped substrates 10C. Thus, as illustrated in FIG. 2D, the under layers 7 covering the connection terminals (front electrodes 2, end face electrodes 6, and back electrodes 5) are formed at both end portions of each of the chip-shaped substrates 10C. The under layers 7 are formed of copper plated layers, and the film thickness thereof is set in the range of 3 μm to 25 μm (10 μm in the present embodiment).

[0036] Next, electrolytic plating is applied on the chip-shaped substrates 10C, whereby, as illustrated in FIG. 2E, the barrier layers 8 covering the under layers 7 are formed. The barrier layers 8 are formed of alloy plated layers (Ni—P plated layers) comprising nickel (Ni) as a main component and containing phosphorus (P), and the thickness thereof is set in the range of 2 μm to 15 μm (5 μm in the present embodiment). The content rate of phosphorus relative to nickel in the barrier layers 8 is set in the range of 3% to 15% (5% in the present embodiment), and thus even if the internal stress is caused due to addition of phosphorus into nickel, the stress is relaxed by the under layers 7.

[0037] Next, electrolytic plating is applied on the chip-shaped substrates 10C, whereby, as illustrated in FIG. 2F, the external connection layers 9 covering the surfaces of the barrier layers 8 are formed. The external connection layers 9 are Sn plated layers mainly composed of tin (Sn), and the thickness thereof is set in the range of 2 μm˜15 μm. In this way, a terminal electrode structure including the barrier layers 8, the external connection layers 9, etc., thus exceling in heat resistance, is formed, and as a result, the chip resistor 10 illustrated in FIG. 1 can be obtained.

[0038] As described above, in the chip resistor 10 according to the first embodiment, the barrier layers 8 covered by the external connection layers 9 formed by tin plating are formed by alloy (Ni—P) plating mainly composed of nickel (Ni) and containing 3% to 15% of phosphorus (P). Applying this alloy plating results in slower diffusion toward tin than using nickel, and accordingly, it is possible to obtain sufficient heat resistance during solder mounting or in the use environment even without forming the barrier layers 8 so thick. Furthermore, since the copper plated layers are formed by electrolytic plating as the under layers 7 of the barrier layers 8, even if the internal stress increases due to addition of phosphorus to nickel, the stress can be relaxed by the under layers 7, thereby making it possible to suppress cracks caused by the internal stress.

[0039] Furthermore, the under layers 7, the barrier layers 8, and the external connection layers 9 are formed by electrolytic plating so as to be dense films. This enables maximizing of the characteristics (stress relaxation, barrier function, solderability) of each of the layers and also realizes a series of plating operations. Thus, it is possible to obtain the adhesion at the boundaries between layers and also the productivity while preventing corrosion due to an environment during the plating processes of forming each of the layers as much as possible.

[0040] FIG. 3 is a cross-sectional view of a chip resistor 20 according to a second embodiment of the present invention. The chip resistor 20 according to the second embodiment is basically the same as the chip resistor 10 according to the first embodiment, but is different therefrom in that magnetic layers 11 are formed between the connection terminals (front electrodes 2, end face electrodes 6, and back electrodes 5) and the barrier layers 8.

[0041] That is, as illustrated in FIG. 3, the chip resistor 20 mainly includes a rectangular parallelepiped insulating substrate 1, the pair of front electrodes 2 formed at both end portions in the longitudinal direction on a surface of the insulating substrate 1, the resistor 3 formed so as to bridge between the pair of front electrodes 2, the protective layer 4 covering the entire of the resistor 3 and a portion of the front electrodes 2, the pair of back electrodes 5 formed at both end portions in the longitudinal direction on the back surface of the insulating substrate 1, the pair of end face electrodes 6 formed on both end faces in the longitudinal direction of the insulating substrate 1, each of which conducts between the corresponding one of the front electrodes 2 and the corresponding one of the back electrodes 5, a pair of under layers 11 each of which covers the corresponding one of the front electrodes 2, the corresponding one of the back electrodes 5, and the corresponding one of the end face electrodes 6, the pair of under layers 7 each of which covers the corresponding one of the magnetic layers 11, the pair of barrier layers 8 each of which covers the corresponding one of the under layers 7, and the pair of external connection layers 9 each of which covers the corresponding one of the barrier layers 8.

[0042] The pair of magnetic layers 11 is a nickel (Ni) plated layer formed by electrolytic plating so as to cover the connection terminals, and the thickness thereof is set in the range of 2 μm to 15 μm. Providing the magnetic layers 11 can enhance the magnetic properties of the barrier layers 8 which have been reduced due to addition of phosphorus to nickel. The magnetic layers 11 may be formed between the under layers 7 and the barrier layers 8. Other than being provided with the magnetic layers 11, the structure according to the second embodiment is the same as that of the first embodiment, and accordingly, the components thereof are designated by the same reference signs as provided in FIG. 1 will not be described again.

[0043] Next, a method of producing the chip resistor 20 having the structure described above will be explained with reference to cross-sectional views illustrated in FIG. 4A to 4E. Note that, in the producing processes illustrated in FIG. 4A to 4E, FIG. 4A corresponds to FIG. 2C of the first embodiment, and the processes therebefore are the same as those of the first embodiment.

[0044] That is, after the front electrodes 2, the resistor 3, the protective layer 4 (undercoat layer 4a and overcoat layer 4b), and the back electrodes 5 are formed on a large-sized substrate (not illustrated), Ni/Cr is deposited by sputtering on the divided faces of the strip-shaped substrate 10B obtained by primary-dividing the large-sized substrate. Thus, as illustrated in FIG. 4A, the end face electrodes 6 for connecting the front electrodes and the back electrodes, which are provided on the front and back surfaces of the strip-shaped substrate 10B are formed.

[0045] Next, after the strip-shaped substrate 10B is secondary-divided along the secondary division groove to obtain a plurality of chip-shaped substrates 10C, electrolytic plating is applied on each of the chip-shaped substrates 10C. Thus, as illustrated in FIG. 4B, the magnetic layers 11 covering the connection terminals (front electrodes 2, end face electrodes 6, and back electrodes 5) are formed on both end portions of each of the chip-shaped substrate 10C. The magnetic layers 11 are formed of a nickel (Ni) plated layer, and the thickness thereof is set in the range of 2 μm to 15 μm (5 μm in the present embodiment).

[0046] Next, electrolytic plating is applied to each of the chip-shaped substrates 10C, whereby, as illustrated in FIG. 4C, the under layers 7 covering the magnetic layers 11 are formed at both end portions of each of the chip-shaped substrates 10C. The under layers 7 are formed of copper plated layers, and the film thickness thereof is set in the range of 3 μm to 25 μm (10 μm in the present embodiment).

[0047] Next, electrolytic plating is applied to each of the chip-shaped substrates 10C, whereby, as illustrated in FIG. 4D, the barrier layers 8 covering the under layers 7 are formed. The barrier layers 8 are formed of alloy-plating layers (Ni—P plated layers) mainly composed of nickel (Ni) and containing phosphorus (P), and the thickness thereof is set in the range from 2 μm to 15 μm (5 μm in the present embodiment). Furthermore, the content rate of phosphorus with respect to nickel in the barrier layers 8 is set in the range of 3% to 15% (5% in the present embodiment).

[0048] Next, electrolytic plating is applied to each of the chip-shaped substrates 10C, whereby, as illustrated in FIG. 4E, the external connection layers 9 covering surfaces of the barrier layers 8 are formed. The external connection layers 9 are Sn plated layers mainly composed of tin (Sn), and the thickness thereof is set in the range of 2 μm to 15 μm. In this way, a terminal electrode structure including the barrier layers 8, the external connection layers 9, etc., thus exceling in heat resistance, is formed, and as a result, the chip resistor 20 illustrated in FIG. 3 can be obtained.

[0049] As described above, in the chip resistor 20 according to the second embodiment, the magnetic layers 11 formed of nickel plated layers are formed between the connection terminals (front electrodes 2, end face electrodes 6, and back electrodes 5) and the barrier layers 8. Accordingly, using the magnetic properties of the magnetic layers 11 enables, for example, stabilizing of a position of a product in a taping process for storing the product in a tape-like package or when taking out the product from a package and mounting it on a circuit board.

[0050] In the chip resistor 20 according to the second embodiment, the magnetic layers 11 are formed between the connection terminals (front electrodes 2, end face electrodes 6, and back electrodes 5) and the under layers 7, meanwhile, the present invention is not limited thereto as long as the magnetic layers 11 are formed between the connection terminals and the barrier layers 8. That is, the magnetic layers 11 may be formed between the under layers 7 and the barrier layers 8, or the magnetic layers 11 may be formed both between the connection terminals and the under layers 7 and between the under layers 7 and the barrier layers 8.

[0051] Furthermore, in each of the embodiments described above, the case that the present invention is applied to the chip resistors which are examples of a surface mount component has been described, meanwhile, the present invention can also be applied to electronic components other than chip resistors, for example, a lead component having a pin-shaped connection terminal such as a connector.

REFERENCE SIGNS LIST

[0052] 1 insulating substrate (component body) [0053] 2 front electrode (connection terminal) [0054] 3 resistor [0055] 4 protective layer [0056] 4a undercoat layer [0057] 4b overcoat layer [0058] 5 back electrode (connection terminal) [0059] 6 end face electrode (connection terminal) [0060] 7 under layer [0061] 8 barrier layer [0062] 9 external connection layer [0063] 10 chip resistor (electronic component) [0064] 11 magnetic layer