METHOD FOR ON-SILICON INTEGRATION OF A COMPONENT III-V AND ON-SILICON INTEGRATED COMPONENT III-V

Abstract

A method for on-silicon integration of a III-V-based material component includes providing a first substrate having a silicon-based optical layer including a waveguide, transferring a second substrate of III-V-based material on the optical layer, and forming the III-V component from the second substrate, so as to enable a coupling between the waveguide and the III-V component, by preserving a III-V-based material layer extending laterally. The method also includes forming by epitaxy from the III-V layer, an InP:Fe-based structure laterally bordering the III-V component, forming a layer including contacts configured to contact the III-V component, and transferring a third silicon-based substrate onto the layer including the contacts.

Claims

1. A method for on-silicon integration of a III-V-based material component comprising: providing a first substrate comprising a silicon-based optical layer, said optical layer comprising at least one waveguide, transferring a second III-V-based material substrate on the optical layer, forming the component from the second substrate, in a proximity of the waveguide so as to enable a coupling between the waveguide and the component, by preserving a III-V-based material layer extending laterally from the component, forming by epitaxy from the III-V-based material layer an InP:Fe-based structure laterally bordering the component, forming a layer comprising contacts configured to electrically contact the component, on a face of the component opposite the optical layer, and transferring a third silicon-based substrate on the layer comprising the contacts.

2. The integration method according to claim 1, further comprising, after transfer of the third silicon-based substrate: removing the first substrate and preserving the optical layer, and forming at least one interconnection level on the optical layer, the at least one interconnection level comprising interconnections electrically connecting the contacts.

3. The integration method according to claim 2, wherein removing the first substrate is performed so as to expose the optical layer, the method further comprising, after removing the first substrate, doping of a silicon-based zone of the optical layer.

4. The integration method according to claim 3, further comprising, before the doping, at least one step carried out at a temperature greater than or equal to 600° C.

5. The integration method according to claim 2, wherein the first substrate is a substrate of the on-insulator semi-conductive type comprising a buried oxide layer between a first silicon bulk part and a second semi-conductor-based thin part, and wherein removing the first substrate comprises removing the first bulk part and the buried oxide layer.

6. The integration method according to claim 1, wherein forming the component comprises: thinning the second III-V-based material substrate so as to preserve a III-V-based material germination layer, and forming the component by localised epitaxy only on one part of the germination layer.

7. The integration method according to claim 1 wherein forming the component comprises: thinning the second III-V-based material substrate so as to preserve a III-V-based material germination layer, forming by epitaxy of a stack of III-V-based material functional layers on the germination layer, and etching a part of the stack so as to form the component and the III-V-based material layer extending laterally from the component.

8. The integration method according to claim 6, wherein the second III-V-based material substrate comprises a sacrificial layer inserted between a bulk part of the second substrate and a part configured to form the germination layer, and wherein the thinning comprises: at least one from among a mechanical cropping of the bulk part of the second substrate and a selective chemical etching of the bulk part of the second substrate visà-vis the sacrificial layer, and selective etching of the sacrificial layer vis-à-vis the layer configured to form the germination layer.

9. The integration method according to claim 1, wherein forming the component comprises forming AlInGaAs or GaInAsP alloy-based quantum wells.

10. The integration method according to claim 1, further comprising, before transferring the third substrate, forming a thermal conduction layer on at least one from among the layer comprising the contacts and the third substrate, so as to insert said thermal conduction layer between the third substrate and the layer comprising the contacts.

11. The integration method according to claim 1, wherein the III-V-based material layer extending laterally from the component is N-doped InP-based.

12. An integration system comprising, as a stack in a direction: a silicon-based substrate, a layer comprising contacts configured to electrically contact a III-V-based material component, the component being laterally bordered by an InP:Fe-based structure, a III-V-based material layer covering the component III-V and the InP:Fe-based structure, and a silicon-based optical layer comprising a waveguide coupled to the component.

13. The integration system according to claim 12, further comprising, on the silicon-based optical layer, an interconnection level comprising a first interconnection part electrically connecting the contacts and a second interconnection part configured to connect silicon-based components disposed on the interconnection level.

14. The integration system according to claim 13 wherein the optical layer further comprises at least one other silicon-based component connected to the interconnection level.

15. The integration system according to claim 12, wherein the III-V-based material layer covering the component is N-doped InP-based, and wherein the component comprises a P-doped InP-based part, and wherein AlInGaAs or GaInAsP alloy-based quantum wells are inserted between the P-doped InP-based part and the N-doped InP-based layer.

16. The integration method according to claim 3, wherein doping the silicon-based zone comprises implantation of doping species.

17. The integration system according to claim 14 wherein the at least one other silicon-based component comprises a PN junction phase modulator.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0036] The aims, objectives, as well as the features and advantages of the invention will best emerge from the detailed description of embodiments of the latter, which are illustrated by the following accompanying drawings, wherein:

[0037] FIGS. 1A to 1N schematically illustrate, as a transverse cross-section, steps of an embodiment of an integration system according to an embodiment of the present invention.

[0038] FIG. 2 schematically illustrates, as a transverse cross-section, an integration system according to another embodiment of the present invention.

[0039] The drawings are given as examples and are not limiting of the invention. They constitute principle schematic representations intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, on the principle diagrams, the dimensions of the different elements (components, interconnections, layers and levels, control electronics, etc.) are not representative of reality.

DETAILED DESCRIPTION

[0040] Before starting a detailed review of embodiments of the invention, optional features are stated below, which can optionally be used in association or alternatively:

[0041] According to an example, the method further comprises, after transfer of the third silicon-based substrate, the following steps: [0042] Removing the first substrate by preserving the optical layer, [0043] Forming at least one interconnection level on the optical layer, said interconnection level comprising interconnections electrically connecting the contacts III-V.

[0044] According to an example, the removal of the first substrate is done so as to expose the optical layer, the method further comprising, after removal of the first substrate, a doping of a silicon-based zone of the optical layer. The doping can typically be done by implantation of doping species, followed by a thermal activation annealing.

[0045] According to an example, the method further comprises, before implantation of doping species, at least one other step carried out at a temperature greater than or equal to 600° C.

[0046] According to an example, the first substrate is an on-insulator semi-conductor type substrate, comprising a buried oxide layer between a first silicon bulk part and a second semi-conductor-based thin part. The semi-conductor can be typically taken from among the semi-conductors IV-IV, in particular silicon, germanium, silicon-germanium.

[0047] According to an example, the removal of the first substrate is configured to remove the first silicon bulk part and the buried oxide layer.

[0048] According to an example, the formation of the component III-V comprises: [0049] A thinning of the second material III-V-based substrate so as to preserve a material III-V-based germination layer, [0050] A formation of the component III-V by localised epitaxy only on a part of the germination layer.

[0051] According to an example, the formation of the component III-V comprises: [0052] A thinning of the second material III-V-based substrate so as to preserve a material III-V-based germination layer, [0053] A formation by epitaxy of a stack of material III-V-based functional layers, on the germination layer, [0054] An etching of a part of the stack so as to form the component III-V and the material III-V-based layer extending laterally from the component III-V.

[0055] According to an example, the second material III-V-based substrate comprises a sacrificial layer inserted between a so-called bulk part of the second substrate and a part intended to form the germination layer.

[0056] According to an example, the thinning comprises: [0057] At least one from among a mechanical cropping of the bulk part of the second substrate and/or a selective chemical etching of the bulk part of the second substrate visà-vis the sacrificial layer, [0058] A selective etching of the sacrificial layer visà-vis the layer intended to form the germination layer.

[0059] According to an example, the selective chemical etching of the bulk part of the second substrate vis-à-vis the sacrificial layer is carried out by wet etching on the basis of a hydrochloric (HCl) acid and phosphoric (H3PO4) acid mixture, for example in proportions HCl:H3PO4 of 1:10.

[0060] According to an example, the formation of the component III-V comprises a formation of quantum wells on the basis of an AlInGaAs or InGaAsP alloy.

[0061] According to an example, the method further comprises, before transfer of the third substrate, a formation of a thermal conduction layer on at least one from among the layer comprising the contacts III-V and the third substrate, so as to insert said thermal conduction layer between the third substrate and the layer comprising the contacts III-V.

[0062] According to an example, the material III-V-based layer extending laterally from the component III-V is N-doped InP-based.

[0063] According to an example, the integration system further comprises, on the silicon-based optical layer, an interconnection level comprising a first interconnection part electrically connecting the contacts III-V, and a second interconnection part intended to connect silicon-based components disposed on said interconnection level.

[0064] According to an example, the optical layer further comprises at least one other silicon-based component, for example a PN junction phase modulator, connected to the interconnection level.

[0065] According to an example, the material III-V-based layer covering the component III-V is N-doped InP-based.

[0066] According to an example, the component III-V comprises a P-doped InP-based part, and quantum wells on the basis of an AlInGaAs or GaInAsP alloy inserted between the P-doped InP-based part and the N-doped InP-based layer.

[0067] Except for being incompatible, technical features described in detail for a given embodiment can be combined with the technical features described in the context of other embodiments described as an example and in a non-limiting manner, so as to form another embodiment which is not necessarily illustrated or described. Such an embodiment is not obviously excluded from the invention.

[0068] In the scope of the present invention, a heat dissipation structure is implemented. This structure can also ensure an electrical insulation function. It can thus be called a “semi-insulating” structure, in the direction where this structure has a low electrical conductivity, but a high thermal conductivity. Typically, the electrical resistivity of such a structure is greater than 10.sup.7 Ω.Math.cm, for example of around 10.sup.8 Ω.Math.cm for an InP:Fe-based structure. Typically, the thermal conductivity of such a structure is greater than 0.5 W.Math.cm.sup.−1.Math.K.sup.−1, for example of around 0.68 W.Math.cm.sup.−1.Math.K.sup.−1 for an InP:Fe-based structure.

[0069] It is specified that, in the scope of the present invention, the terms “on”, “surmounts”, “covers”, “underlying”, “visà-vis” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition of a first layer on a second layer, does not necessarily mean that the two layers are directly in contact with one another, but means that the first layer covers at least partially the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0070] A layer can moreover be composed of several sublayers made of one same material or of different materials.

[0071] By a material A-“based” substrate, element, layer, this means a substrate, an element, a layer comprising this material A only or this material A and optionally other materials, for example, of alloy elements and/or doping elements. Thus, a “silicon-based” substrate can comprise a silicon bulk part, and a thin silicon or germanium, or SiGe alloy layer. A “silicon-based” optical layer can comprise a first silicon element, and/or a second germanium element, and/or a third SiGe element. An “InP-based” layer can comprise InP, InP:Fe comprising N- or P-doped Fe, InP impurities.

[0072] By “selective etching vis-à-vis” or “etching having a selectivity visà-vis”, this means an etching configured to remove a material A or a layer A visà-vis a material B or a layer B, and having an etching speed of the material A greater than the etching speed of the material B. The selectivity is the ratio between the etching speed of the material A over the etching speed of the material B.

[0073] A preferably orthonormal marker, comprising the axes x, y, z is represented in the accompanying figures. When one single marker is represented on one same set of figures, this marker is applied to all the figures of this set.

[0074] The relative terms such as “on”, “surmounts”, “under”, “underlying” refer to positions taken in the direction z. This list of terms is not exhaustive. Other relative terms can be easily specified if needed, by referring to the accompanying drawings.

[0075] In the present patent application, the height and the depth are taken along z.

[0076] The terms “vertical”, “vertically” refer to a direction along z. The terms “horizontal”, “horizontally” refer to a direction in the plane xy. The terms “lateral”, “laterally”, when this relates to a movement, an extension or a positioning, refer also to a direction in the plane xy, typically the direction x.

[0077] An element located “in vertical alignment with” or “to the right of” another element means that these two elements are both located on one same line oriented vertically in the figures. This does not necessarily mean that these two elements are centred with respect to a vertical axis.

[0078] By material III-V, this means an alloy comprising elements of the columns IIIB and VB of the periodic table of elements (block p).

[0079] In a non-limiting manner, the materials III-V implemented in the method and the integration system comprise: InP, AlN, InGaAs, AlInGaAs.

[0080] FIGS. 1A to 1N illustrate an embodiment of an architecture enable the hetero-integration of a component III-V coupled to a silicon waveguide, with an improved heat dissipation.

[0081] As illustrated in FIG. 1A, a first substrate 1 of SOI (Silicon On Insulator) type is typically provided. This substrate 1 typically comprises in a stack along z, a so-called bulk silicon part 10, a so-called BOX buried oxide layer 11, and a superficial layer 12, also called top Si.

[0082] The thickness e.sub.11 of the BOX 11 is typically around 1 μm to 2 μm. The thickness e.sub.12 of the top Si 12 is typically around 300 nm to 600 nm, for example around 500 nm. This thickness e.sub.12 of 500 nm can be obtained by silicon regrowth from a thin silicon layer of an SOI substrate having a standard thickness of top Si of 100 nm or 200 nm.

[0083] As illustrated in FIG. 1B, the top Si layer 12 is etched over a depth e.sub.120 typically of between 200 nm and 300 nm, so as to form a waveguide structure 120 at the edge.

[0084] As illustrated in FIG. 1C, the structure obtained is then covered by a silicon oxide-based encapsulation layer 121, before being planarised in a known manner by chemical-mechanical polishing (CMP). This makes it possible to obtain a surface state compatible with the gluing of another platelet or substrate also called wafer. The encapsulation layer 121 and the remaining part of the top Si 12 comprising the waveguide 120 form an optical layer 122. The optical layer 122 thus has a silicon oxide SiO2-based surface 212c. The waveguide 120 is typically buried under the surface 212c at a depth of around 10 nm to 150 nm.

[0085] As illustrated in FIG. 1D, a second substrate 2 is brought facing the optical layer 122. This substrate 2 typically comprises in stack along z, a thin InP-based germination layer 22, an InGaAs-based sacrificial layer 21, and an InP-based bulk part 20.

[0086] The thickness e.sub.22 of the germination layer 22 is typically around 100 nm to 300 nm. The thickness e.sub.21 of the sacrificial layer 21 is typically around 200 nm to 400 nm. The thickness e.sub.20 of the bulk part 20 can be around a few microns to a few tens of microns, even a few hundred microns.

[0087] This stack of material III-V-based layers is rotated so as to have the germination layer 22 facing the optical layer 122, then glued, for example by direct hydrophilic gluing. For this type of gluing, the surfaces 220c, 212c are made hydrophilic by adapted surface treatments. The surface 220c of the InP-based germination layer 22 is typically cleaned beforehand by a hydrofluoric acid-based solution, then exposed to an oxygen plasma and/or ozone. The SiO2-based surface 212c of the optical layer 122 is typically exposed to an oxygen plasma and/or ozone. After assembly of the surfaces 220c, 212c thus prepared, a thermal annealing of around 300° is carried out so as to finalise this direct hydrophilic gluing.

[0088] As illustrated in FIG. 1E, after gluing, the InP-based bulk part 20 is first removed, then the sacrificial layer 21 is selectively removed at the germination layer 22. The removal of the bulk part 20 can be done by mechanical cropping and/or by chemical etching. The removal of the sacrificial layer 21 is done preferably by selective etching of InGaAs visà-vis InP, for example by wet etching on the basis of a sulphuric acid (H2SO4), oxygenated water (H2O2) and water (H2O) mixture, for example in proportions H2SO4:H2O2:H2O of 1:1:20.

[0089] The germination layer 22 thus exposed makes it possible to perform a regrowth by epitaxy of a material III-V of excellent crystalline quality.

[0090] As illustrated in FIG. 1F, a growth of a structure of laser component III-V can be advantageously performed on this germination layer 22. Preferably, an N-doped InP growth is performed so as to obtain the base layer 221b. AlInGaAs-based quantum wells are then epitaxially grown on this base layer 221b, so as to form the active region 222. The active region 222 can typically comprise a number of quantum wells of between 3 and 20, for example 8. A P-doped InP-based layer 223 is then epitaxially grown. Other layers, for example an InGaAs-based P contact layer, can also be raw on or within this stack, so as to improve the injection of charge carriers, for example.

[0091] These material III-V growth steps are typically carried by Vapour Phase Epitaxy from Metalorganic precursors (MOVPE) at growth temperatures greater than or equal to 600° C. The metalorganic precursors which could be used, are for example Trimethylaluminium (TMAl), Trimethylgallium (TMGa), Trimethylindium (TMIn). The sources of V elements can be hydrides (AsH3, PH3). These growths are preferably performed in a localised manner on the first substrate 1, by so-called SAG (Selective Area Growth) techniques.

[0092] As illustrated in FIG. 1G, the P-doped layer 223 and the active region 222 are typically etched so as to form a component 23 having a structure at the edge of width w.sub.23 along x. The width w.sub.23 is typically of between 500 nm and 3 μm. This component 23 is, for example, a material III-V-based laser. This laser can be of the Fabry-Pérot type, or with distributed Bragg mirrors, or with a ring cavity. The etching is configured such that the component 23 is optically coupled with the waveguide 120. The component 23 can thus be substantially centred visà-vis the waveguide 120 along x. According to an example, the component 23 and the waveguide 120 are in vertical alignment with one another. According to a possibility, the component III-V can be an electrooptical phase modulator.

[0093] After etching, a layer 221 coming from the base layer 221b extends typically on either side of the mesa structure 222, 223 of the component 23. This layer 221 is typically intended to form an injection layer for the N-type contact. It has an exposed surface 220. Advantageously, this layer 221 makes it possible to perform an InP:Fe epitaxy on either side of the component 23.

[0094] The component 23 can typically comprise the injection layer 221, the active region 222, the layer 223, and optionally a part of the waveguide 120.

[0095] As illustrated in FIG. 1H, an InP:Fe-based structure 24 is formed from the layer 221, at the edge of the component 23. The structure 24 is typically formed by MOVPE at a temperature greater than or equal to 600° C. This structure 24 is preferably directly in contact with the sides 224 of the component 23. According to another possibility, a thin layer, also called liner, can be inserted between the structure 24 and the sides 224. This structure 24 advantageously forms a SIBH heat dissipation structure for the component 23. After growth of InP:Fe on the layer 221, a planarisation, for example by chemical-mechanical polishing, is preferably carried out so as to expose the tip 230 of the component 23. A flat surface 230, 225 is thus obtained.

[0096] According to an alternative possibility, the component 23 is formed separately, with or without the SIBH heat dissipation structure, and directly transferred onto the optical layer 122. The number of growth steps at a high temperature of materials III-V can thus be limited. After transfer, the waveguide 120 can be in a structured part, for example in the direction y.

[0097] As illustrated in FIG. 1I, optionally, an SiO2-based encapsulation layer 25a can be deposited on the flat surface 230, 225 of the level III-V, then planarised. N and P contacts are then formed on the component 23. The P-doped part 223 of the component 23 is thus electrically contacted at a P contact 251, by way of a metal via 251v. The N-doped layer 221 connecting the component 23 is thus electrically contacted at an N contact 252, by way of a metal via 252v. The via 252v passes through the heat dissipation structure 24 and optionally the encapsulation layer 25a.

[0098] As illustrated in FIG. 1J, after formation of the vias 251v, 252v and of the P and N contacts 251, 252, a second SiO2-based encapsulation layer 25b is deposited then planarised. A layer 250 comprising a first level of electrical contacts is thus formed.

[0099] According to a possibility, the encapsulation layers 25a, 25b can be on the basis of an electrically insulating material which is a good thermal conductor, for example of aluminium nitride AlN.

[0100] Optionally, as illustrated in FIG. 1K, a thermal conduction layer 253 can be deposited on the contact layer 250. This thermal conduction layer 253 typically has a high thermal conduction. It can be electrically conductive, for example on the basis of a metal which is compatible with CMOS technology. Such a thermal conduction layer 253, for example gold-based, can also facilitate assembly with another wafer.

[0101] As illustrated in FIG. 1L, a third substrate 3, typically silicon-based, is assembled facing the contact layer 250, optionally by way of the thermal conduction layer 253.

[0102] At this stage, the structure thus formed comprises in a stack, along z: [0103] the first substrate 1 comprising the silicon-based optical layer 122, [0104] a level III-V comprising the component 23 and the heat dissipation structure 24, and possibly one or more through vias, [0105] a contact layer 250, [0106] optionally, a thermal conduction layer 253, [0107] a third silicon-based substrate 3.

[0108] As illustrated in FIG. 1M, the substrate 1 is thus partially removed. In particular, the bulk part and the BOX are removed by cropping and chemical etching, so as to expose the remaining part of the top Si of the optical layer 122.

[0109] This part of the top Si can be advantageously again structured by lithography/etching so as to form a silicon-based component 123. Advantageously, an implantation of doping species can be performed at the level of an implantation zone I. An activation of the doping species by thermal annealing is thus typically performed.

[0110] The prior removal of the BOX in particular makes it possible to perform such an implantation. This also makes it possible to perform a doping by diffusion, according to an alternative possibility. A component 123 having implanted and doped zones is thus advantageously obtained. Such a silicon-based component 123 can be, for example, a PN junction phase modulator, another waveguide. According to another possibility, the BOX is partially removed and thinned so as to enable an implantation of doping species in the implantation zone I through the thinned BOX. The localised doping of the top Si is thus advantageously performed after the InP:Fe epitaxy step requiring a large thermal budget. The high-temperature epitaxy step(s) (SAG, SIBH) therefore does/do not disrupt the doping of the top Si. This makes it possible to better control the doping profiles in the top Si.

[0111] As illustrated in FIG. 1N, one or more interconnection levels 4 can be formed on the optical layer 122, by conventional BEOL (Back End of Line) methods. In the example illustrated, the through vias 451v, 452v connect the material III-V-based component 23. Other vias 453v, 454v connect the silicon-based component 123. According to a possibility, the interconnection level(s) can be applied on the optical layer 122 by way of a silicon-based interposer. This interconnection level is typically slightly thermally conductive.

[0112] The method thus makes it possible to form an optimised architecture for heat dissipation, comprising in a stack along z: [0113] the silicon-based bulk substrate 3 making it possible to discharge the heat produced by the component 23, [0114] an optional thermal conduction layer 253, [0115] a contact layer 250, [0116] a level III-V comprising the component 23 and the heat dissipation structure 24, [0117] the optical layer 122 comprising the waveguide 120 optically coupled to the component 23, [0118] an interconnection level 4.

[0119] The method according to the invention thus makes it possible to vertically integrate photonic silicon structures obtained by standard methods, with components III-V obtained by advanced techniques for epitaxially regrowing materials III-V. Advantageously, the epitaxial growth(s) requiring high temperatures greater than 600° C. are first performed, then the stack is returned so as to perform standard silicon technology steps.

[0120] The heat produced by the component III-V is typically discharged via the dissipation structure 24 and the substrate 3, opposite the waveguide 120 and/or the interconnection level. The optical properties of the waveguide 120 are thus not affected by the heat flow. The interconnection level further forms a heat barrier insulating the upper levels, for example a level comprising control electronics. The component 23 and its control electronics can thus be thermally insulated from one another by the interconnection level.

[0121] FIG. 2 illustrates another example of architecture obtained by this method. In this example, the layer 221 extends laterally from the component 23 dissymmetrically with respect to the sides of the component 23. This makes it possible, for example, to facilitate the formation of the via 451v.

[0122] Control electronics 5 can be assembled to the interconnection level 4 by contact terminals 45. A radiator 50 can be disposed on the control electronics 5 to discharge the heat produced by this control electronics 5. A device 30, for example, a heat dissipator or a Peltier, can be added on the side of the substrate 3 so as to improve the discharging of the heat produced by the component 23. The encapsulation layer part inserted between the substrate 3 and the P contact 251 is advantageously thin, and typically has a thickness less than or equal to 500 nm, preferably less than 200 nm.

[0123] The hetero-integration III-V/silicon architectures proposed in this case enable, in particular: [0124] A better dissipation of heat from the components III-V, and a thermal insulation visà-vis the control electronics and/or the silicon-based waveguide, [0125] A compatibility with standard BEOL CMOS technologies, [0126] A compatibility with (SAG- and/or SIBH-type) advanced regrowth techniques.

[0127] The invention is not limited to the embodiments described above.