REFERENCE VOLTAGE GENERATING SYSTEM AND START-UP CIRCUIT THEREOF

Abstract

A start-up circuit includes series-connected first-type first transistors through which a start-up current flows in a start-up period, being connected between a positive power voltage and an inner node; and a first-type second transistor through which a boost current flows in the start-up period, being connected between the positive power voltage and the inner node, and with a gate connected to an output node that provides a bias voltage.

Claims

1. A reference voltage generating system, comprising: a bandgap voltage reference circuit that generates a bandgap voltage; a start-up circuit that starts the bandgap voltage reference circuit, the start-up circuit providing a bias voltage at an output node to the bandgap voltage reference circuit, and the bandgap voltage being fed to an input node of the start-up circuit, the start-up circuit including: series-connected first-type first transistors through which a start-up current flows in a start-up period, being connected between a positive power voltage and an inner node; and a first-type second transistor through which a boost current flows in the start-up period, being connected between the positive power voltage and the inner node, and with a gate connected to the output node.

2. The system of claim 1, wherein the series-connected first-type first transistors are P-type transistors with gates connected to a negative power voltage.

3. The system of claim 2, wherein the series-connected first-type first transistors comprise: a first transistor with a source connected to the positive power voltage; a second transistor with a source connected to a drain of the first transistor; and a third transistor with a source connected to a drain of the second transistor, and a drain connected to the inner node.

4. The system of claim 1, wherein the first-type second transistor is a P-type transistor with a source connected to the positive power voltage and a drain connected to the inner node.

5. The system of claim 1, wherein the start-up circuit further comprises: a second-type first transistor connected between the inner node and a negative power voltage, and with a gate connected to receive the bandgap voltage; and a second-type second transistor connected between the output node and the negative power voltage, and with a gate connected to the inner node.

6. The system of claim 5, wherein the second-type first transistor is an N-type transistor with a drain connected to the inner node, and a source connected to the negative power voltage.

7. The system of claim 5, wherein the second-type second transistor is an N-type transistor with a drain connected to the output node, and a source connected to the negative power voltage.

8. The system of claim 1, wherein the bandgap voltage reference circuit comprises: an amplifier with an output connected to the output node of the start-up circuit.

9. A start-up circuit, comprising: series-connected first-type first transistors through which a start-up current flows in a start-up period, being connected between a positive power voltage and an inner node; and a first-type second transistor through which a boost current flows in the start-up period, being connected between the positive power voltage and the inner node, and with a gate connected to an output node that provides a bias voltage.

10. The circuit of claim 9, wherein the series-connected first-type first transistors are P-type transistors with gates connected to a negative power voltage.

11. The circuit of claim 10, wherein the series-connected first-type first transistors comprise: a first transistor with a source connected to the positive power voltage; a second transistor with a source connected to a drain of the first transistor; and a third transistor with a source connected to a drain of the second transistor, and a drain connected to the inner node.

12. The circuit of claim 9, wherein the first-type second transistor is a P-type transistor with a source connected to the positive power voltage and a drain connected to the inner node.

13. The circuit of claim 9, further comprising: a second-type first transistor connected between the inner node and a negative power voltage, and with a gate connected to receive a reference voltage; and a second-type second transistor connected between the output node and the negative power voltage, and with a gate connected to the inner node.

14. The circuit of claim 13, wherein the second-type first transistor is an N-type transistor with a drain connected to the inner node, and a source connected to the negative power voltage.

15. The circuit of claim 13, wherein the second-type second transistor is an N-type transistor with a drain connected to the output node, and a source connected to the negative power voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 shows a block diagram illustrating a reference voltage generating system;

[0009] FIG. 2 shows a block diagram exemplifying application of the bandgap voltage reference circuit; and

[0010] FIG. 3 shows a circuit diagram illustrating the reference voltage generating system according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0011] FIG. 1 shows a block diagram illustrating a reference voltage generating system 1000 for generating a reference voltage. The reference voltage generating system 1000 of the embodiment may include a start-up circuit 100 and a bandgap voltage reference circuit 200 which is started by the start-up circuit 100.

[0012] In the embodiment, the start-up circuit 100 and the bandgap voltage reference circuit 200 are connected between a positive power voltage VDDD and a negative power voltage VSSD. The start-up circuit 100 provides a bias voltage Vbias at an output node to the bandgap voltage reference circuit 200, and a bandgap voltage Vbg (of about 1.2 volts) generated by the bandgap voltage reference circuit 200 is fed back to an input node of the start-up circuit 100.

[0013] FIG. 2 shows a block diagram exemplifying application of the bandgap voltage reference circuit 200. Specifically, the bandgap voltage reference circuit 200 provides the bandgap voltage Vbg (i.e., reference voltage) to a voltage regulator 300, such as low-dropout (LDO) regulator, to generate a required constant voltage source. A bias current Ibias may be further provided to the voltage regulator 300 from the output node (i.e., Vbias) of the start-up circuit 100.

[0014] FIG. 3 shows a circuit diagram illustrating the reference voltage generating system 1000 according to one embodiment of the present invention. It is noted that the start-up circuit 100 of the embodiment may be adapted to a circuit other than the bandgap voltage reference circuit 200 as exemplified in FIG. 3. In the embodiment, the start-up circuit 100 may include a plurality of (e.g., three) series-connected first-type (e.g., P-type) first transistors P1-P3, connected between the positive power voltage VDDD and an inner node M, and with gates connected to the negative power voltage VSSD. Specifically, a (first) first-type first transistor P1 has a source connected to the positive power voltage VDDD, and a drain connected to a source of a succeeding (second) first-type first transistor P2; a drain of the first-type first transistor P2 is connected to a source of a succeeding (third) first-type first transistor P3; and a drain of the first-type first transistor P3 is connected to the inner node M. The first-type first transistors P1-P3 and the following transistors may be metal-oxide-semiconductor (MOS) transistors.

[0015] According to one aspect of the embodiment, the start-up circuit 100 may include a first-type (e.g., P-type) second transistor P4 connected between the positive power voltage VDDD and the inner node M, and with a gate connected to an output node (i.e., bias voltage Vbias). Specifically, the first-type second transistor P4 has a source connected to the positive power voltage VDDD, and a drain connected to the inner node M.

[0016] The start-up circuit 100 of the embodiment may include a second-type (e.g., N-type) first transistor N1 connected between the inner node M and the negative power voltage VSSD, and with a gate connected to receive the bandgap voltage Vbg (of the bandgap voltage reference circuit 200). Specifically, the second-type first transistor N1 has a drain connected to the inner node M, and a source connected to the negative power voltage VSSD.

[0017] The start-up circuit 100 of the embodiment may include a second-type (e.g., N-type) second transistor N2 connected between the output node (i.e., bias voltage Vbias) and the negative power voltage VSSD, and with a gate connected to the inner node M. Specifically, the second-type second transistor N2 has a drain connected to the output node M, and a source connected to the negative power voltage VSSD.

[0018] In a start-up period, the positive power voltage VDDD and the negative power voltage VSSD provide to the start-up circuit 100 and the bandgap voltage reference circuit 200. As the positive power voltage VDDD increases, a start-up current Is flows through the series-connected first-type first transistors P1-P3 in a direction from the positive power voltage VDDD to the inner node M. At the same time, according to another aspect of the embodiment, a boost current Ib flows through the first-type second transistor P4 in a direction from the positive power voltage VDDD to the inner node M.

[0019] Next, the second-type second transistor N2 is turned on to pull the bias voltage Vbias (at the output node) down to an objective potential. Accordingly, the bandgap voltage reference circuit 200 can output the expected bandgap voltage Vbg. Finally, the second-type first transistor N1 is turned on, thereby turning off the second-type second transistor N2 and finishing the start-up period.

[0020] The start-up circuit 100 of the embodiment can start the bandgap voltage reference circuit 200 successfully regardless of process, voltage and temperature (PVT) variations. In a low-temperature (e.g., −40° C.) low-voltage (e.g., 1.55V) condition, for example, as a threshold voltage increases, the bias voltage Vbias should be pulled down near the negative power voltage VSSD, thereby decreasing the start-up current Is. Without the boost current Ib flowing through the first-type second transistor P4, the second-type second transistor N2 cannot fully turn on due to the slightly turned-on second-type first transistor N1. Therefore, the bias voltage Vbias cannot be pulled down to the objective potential, and the bandgap voltage Vbg may be kept in an erroneous state.

[0021] In the embodiment, the boost current Ib flowing through the first-type second transistor P4 makes up for insufficient start-up current Is in the start-up period, thereby starting the bandgap voltage reference circuit 200 successfully to generate a correct bandgap voltage Vbg.

[0022] The start-up circuit 100 of the embodiment may be adapted to a high-voltage (e.g., 2.8V) scenario. As shown in FIG. 3, the first-type second transistor P4 is controlled by the bias voltage Vbias, which is further controlled by an output of an amplifier 21 in the bandgap voltage reference circuit 200. Accordingly, an excess of the boost current Ib in a high-voltage condition can be prevented, otherwise the second-type second transistor N2 (of the start-up circuit 100) cannot fully turn off after the start-up period and affects the output of the bandgap voltage Vbg (of the bandgap voltage reference circuit 200).

[0023] Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.