SYNCHRONOUS RECTIFIER CONTROL CIRCUIT AND METHOD

Abstract

In an embodiment, a method for controlling a synchronous rectifier (SR) transistor of a flyback converter includes: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.

Claims

1. A method for controlling a synchronous rectifier (SR) transistor of a flyback converter, the method comprising: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.

2. The method of claim 1, wherein generating the gating signal comprises: determining a reference voltage based on the output voltage; when the first voltage increases above the reference voltage, deasserting the gating signal; and while the gating signal is deasserted, comparing the first voltage with the reference voltage and asserting the gating signal a first delay time after the first voltage drops below the reference voltage.

3. The method of claim 2, wherein turning on the SR transistor comprises turning on the SR transistor when the turn-on signal is asserted while the gating signal is deasserted.

4. The method of claim 2, wherein the first delay time is lower than one quarter of a ringing time of the first voltage.

5. The method of claim 2, wherein the first delay time is between 20 ns and 210 ns.

6. The method of claim 2, wherein the reference voltage is given by
V.sub.ref=(1+k).Math.V.sub.out, where V.sub.ref represents the reference voltage, V.sub.out represents the output voltage, and k is a number higher than 0.

7. The method of claim 6, wherein k is between 0.2 and 0.5.

8. The method of claim 2, wherein generating the gating signal comprises using a gating circuit that comprises: a first comparator having a first input for receiving the first voltage and a second input for receiving the reference voltage; a delay circuit having an input coupled to an output of the first comparator, the delay circuit having a delay time equal to the first delay time; and an OR gate having a first input coupled to the output of the first comparator, a second input coupled to an output of the delay circuit, and an output for providing the gating signal.

9. The method of claim 1, further comprising generating a blanking signal based on the first voltage, wherein turning on the SR transistor is further based on the blanking signal, and wherein turning off the SR transistor is further based on the blanking signal.

10. The method of claim 1, wherein asserting the turn-on signal comprises asserting the turn-on signal when the first voltage drops below a second threshold, and wherein asserting the turn-off signal comprises asserting the turn-off signal when the first voltage increases above a third threshold.

11. The method of claim 1, further comprising operating the flyback converter as a non-complementary active clamp flyback (ACF) converter.

12. The method of claim 1, further comprising operating the flyback converter as an RCD clamp flyback converter in discontinuous conduction mode (DCM).

13. A synchronous rectifier (SR) controller comprising: an output terminal configured to be coupled to a control terminal of an SR transistor of a flyback converter; and an input terminal configured to receive an output voltage of the flyback converter, wherein the SR controller is configured to: determine a first voltage across conduction terminals of the SR transistor; assert a turn-on signal when a body diode of the SR transistor is conducting current; assert a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generate a gating signal based on the output voltage of the flyback converter and on the first voltage; turn on the SR transistor based on the turn-on signal and on the gating signal; and turn off the SR transistor based on the turn-off signal.

14. The SR controller of claim 13, wherein the SR controller is configured to generate the gating signal by: determining a reference voltage based on the output voltage; when the first voltage increases above the reference voltage, deasserting the gating signal; and while the gating signal is deasserted, comparing the first voltage with the reference voltage and asserting the gating signal a first delay time after the first voltage drops below the reference voltage.

15. The SR controller of claim 14, wherein the SR controller is configured to turn on the SR transistor when the turn-on signal is asserted while the gating signal is deasserted.

16. The SR controller of claim 14, further comprising a gating circuit configured to generate the gating signal, the gating circuit comprising: a first comparator having a first input configured to receive the first voltage and a second input configured to receive the reference voltage; a delay circuit having an input coupled to an output of the first comparator, the delay circuit having a delay time equal to the first delay time; and an OR gate having a first input coupled to the output of the first comparator, a second input coupled to an output of the delay circuit, and an output configured to provide the gating signal.

17. The SR controller of claim 16, further comprising; a turn on circuit configured to generate the turn-on signal; a turn-off circuit configured to generate the turn-off signal; a first AND gate having a first input coupled to an output of the turn on circuit, and a second input coupled to an output of the OR gate; and a first flip-flop having a first input coupled to an output of the first AND gate, a second input coupled to an output of the turn-off circuit, and an output coupled to the output terminal.

18. The SR controller of claim 17, further comprising: a blanking circuit having an input couple to the output of the first flip-flop; and a second AND gate having a first input coupled to an output of the blanking circuit, a second input coupled to the output of the turn-off circuit, and an output coupled to the second input of the first flip-flop, wherein the first AND gate comprises a third input coupled to the output of the blanking circuit.

19. The SR controller of claim 17, wherein the turn on circuit comprises a second comparator having a first input configured to receive a second threshold, and a second input configured to receive the first voltage; and wherein the turn off circuit comprises a third comparator having a first input configured to receive a third threshold, and a second input configured to receive the first voltage.

20. A flyback converter comprising: a transformer having first and second windings; an output terminal coupled to the second winding; a first primary transistor coupled to the first winding; a primary controller having an output coupled to a control terminal of the first primary transistor; a synchronous rectifier (SR) transistor coupled to the second winding; and an SR controller configured to: determine a first voltage across conduction terminals of the SR transistor, assert a turn-on signal when a body diode of the SR transistor is conducting current, assert a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold, generate a gating signal based on an output voltage at the output terminal and on the first voltage; turn on the SR transistor based on the turn-on signal and on the gating signal; and turn off the SR transistor based on the turn-off signal.

21. The flyback converter of claim 20, further comprising a second primary transistor coupled to the second winding, wherein the primary controller is configured to control the first and second primary transistor to operate the flyback converter as a non-complementary active clamp flyback (ACF) converter.

22. The flyback converter of claim 20, further comprising a resistor coupled to the first winding, a capacitor coupled in parallel with the resistor, and a diode coupled between the first primary transistor and the capacitor, wherein the primary controller is configured to control the first primary transistor to operate the flyback converter as an RCD clamp flyback converter in discontinuous conduction mode (DCM).

23. The flyback converter of claim 20, wherein the SR transistor is a metal-oxide semiconductor field-effect transistor (MOSFET) or GaN transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0011] FIGS. 1 and 2 show schematic diagrams of exemplary flyback converters;

[0012] FIGS. 3A and 3B show exemplary waveforms associated with operating the flyback converter of FIG. 2 as a complementary ACF converter;

[0013] FIGS. 4A and 4B show exemplary waveforms associated with operating the flyback converter of FIG. 2 as a non-complementary ACF converter;

[0014] FIGS. 5A and 5B show schematic diagrams of an ACF converter, according to an embodiment of the present invention;

[0015] FIG. 5C shows waveforms associated with the ACF converter of FIG. 5A while being operated as a non-complementary ACF converter, according to an embodiment of the present invention;

[0016] FIGS. 6A and 6B show waveforms associated with the SR transistor of the ACF converter of FIG. 5A, according to an embodiment of the present invention;

[0017] FIG. 7 shows a flow chart of an embodiment method for generating a gating signal for controlling the SR transistor of FIG. 5A, according to an embodiment of the present invention;

[0018] FIG. 8 shows a schematic diagram of the SR controller of FIG. 5A, according to an embodiment of the present invention.

[0019] FIGS. 9A and 9B show a schematic diagram of the gating circuit of FIG. 8, and associated waveforms, respectively, according to an embodiment of the present invention;

[0020] FIGS. 10 and 11 show waveforms associated with the SR controller of FIG. 8 and operating at full load and light load, respectively, according to an embodiment of the present invention; and

[0021] FIGS. 12A and 12B show a schematic diagram of a flyback converter, and associated waveforms, respectively, according to an embodiment of the present invention.

[0022] Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0023] The making and using of the embodiments disclosed are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0024] The description below illustrates the various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials and the like. In other cases, known structures, materials or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. References to “an embodiment” in this description indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Consequently, phrases such as “in one embodiment” that may appear at different points of the present description do not necessarily refer exactly to the same embodiment. Furthermore, specific formations, structures or features may be combined in any appropriate manner in one or more embodiments.

[0025] Embodiments of the present invention will be described in specific contexts, e.g., an ACF converter with synchronous rectification for use in applications such as USB-PD type C. Embodiments of the present invention may be used in other types of applications.

[0026] In an embodiment of the present invention, an ACF converter operated as a non-complementary ACF converter includes a synchronous rectifier (SR) transistor that turns on during the main conduction interval (t.sub.A) of secondary current but not during the minor conduction interval (t.sub.B) of secondary current. A gating signal (ON_EN) is generated based on the output voltage of the ACF converter and on the drain-to-source voltage of the SR transistor and prevents the turn on of the SR transistor when the gating signal is asserted (e.g., low).

[0027] ACF converter 200 may be operated as a complementary ACF converter or as a non-complementary ACF converter. FIGS. 3A and 3B show exemplary waveforms associated with operating converter 200 as a complementary ACF converter.

[0028] As shown in FIG. 3A, signals V.sub.G_102 and V.sub.G_208 driving transistors 102 and 108, respectively, turn on and off in a complementary manner. Thus, transistor 102 is turned on when transistor 208 is turned off, and vice versa. As shown in FIG. 3B, when voltage V.sub.1 is high (when transistor 102 is off and transistor 208 is on), the primary current I.sub.p and the secondary current I.sub.s have sinusoidal shapes. When voltage V.sub.1 is low (when transistor 102 is on and transistor 208 is off) primary current I.sub.p has a straight-line shape while the secondary current I.sub.s is zero.

[0029] FIGS. 4A and 4B show exemplary waveforms associated with operating converter 200 as a non-complementary ACF converter. As shown in FIGS. 4A and 4B, transistor 208 is turned on after the secondary current I.sub.s demagnetizes for a period of time to allow the primary current I.sub.p to increase enough to achieve soft switching. As a result, there is simultaneous conduction on the primary and secondary side of the ACF converter 200.

[0030] Advantages of some embodiments operating ACF converters (e.g., 200) in a non-complementary manner (e.g., as illustrated in FIGS. 4A and 4B) include lower RMS current circulating on the primary side, lower power losses, higher efficiency, easy to manage broad input voltage V.sub.in and broad output voltage V.sub.out range, which may be particularly advantageous for applications such as USB Power Delivery (USB-PD).

[0031] In some embodiments, the rectifying diode 116 is replaced with a transistor that is controlled to emulate diode behavior, which may advantageously achieve reduced power losses and increased efficiency.

[0032] FIG. 5A shows a schematic diagram of ACF converter 500, according to an embodiment of the present invention. ACF converter 500 includes transformer 512, capacitors 506 and 514, transistors 502, 508, and 516, and primary controller 510 and synchronous rectifier (SR) controller 518. Capacitor 506 may be referred to as a clamp capacitor. Transistor 516 may be referred to as a synchronous rectifier (SR) transistor.

[0033] Although FIG. 5A illustrate SR transistor 516 disposed on the ground side of secondary winding 512b, in some embodiments, SR transistor 516 may be disposed on the other side of secondary winding 512b.

[0034] Transistors 502, 508, and 512 may be implemented, e.g., as metal-oxide semiconductor field-effect transistors (MOSFETs), for example. Other implementations, such as using GaN transistors, are also possible.

[0035] In some embodiments, primary controller 510 is configured to operate transistors 508 and 502 in a non-complementary manner, e.g., similar to primary controller 210, e.g., as shown in FIGS. 4A and 4B.

[0036] Primary controller 510 may be implemented, e.g., with a general purpose or custom microcontroller or processor, e.g., coupled to a memory and configured to execute instructions stored in the memory. In some embodiments, primary controller 510 may be implemented with logic circuits, such as combinatorial logic, flip-flops, finite state machines, etc. Other implementations are also possible.

[0037] As shown in FIG. 5A, SR controller 518 may sense output voltage V.sub.out and a drain-to-source voltage V.sub.DS_516 for generating voltage V.sub.G_516. SR controller 518 may be implemented, e.g., with a general purpose or custom microcontroller or processor, e.g., coupled to a memory and configured to execute instructions stored in the memory. In some embodiments, SR controller 518 may be implemented with logic circuits, such as combinatorial logic, flip-flops, finite state machines, etc. Other implementations are also possible.

[0038] FIG. 5B shows a schematic diagram of ACF converter 500 illustrating a model for the primary winding 512a, according to an embodiment of the present invention. As shown in FIG. 5B, primary winding 512a may be modeled with inductances 512c, 512d, and 512e.

[0039] FIG. 5C shows waveforms associated with ACF converter 500 while being operated as a non-complementary ACF converter, according to an embodiment of the present invention. FIG. 5C may be understood in view of FIG. 5B.

[0040] As shown in FIG. 5C, during period t.sub.charge, transistor 502 is on, transistor 508 is off, and primary current I.sub.p and magnetization current I.sub.m increase. Once transistor 502 is turned off, clamp current I.sub.clamp spikes and secondary current I.sub.s increases until primary current I.sub.p drops to zero, and then begins to decrease until magnetization current I.sub.m drops to zero. As shown in FIG. 5C, secondary current I.sub.s is non-zero during period t.sub.A.

[0041] During period tc, the drain-to-source voltage of transistors 502 (V.sub.DS_502) and 516 (V.sub.DS_516) resonate until transistor 508 is turned on. Once transistor 508 is turned on, primary current I.sub.p, magnetization current I.sub.m, and clamp current I.sub.clamp begin decreasing below zero, and secondary current I.sub.s begins increasing until transistor 502 is turned on.

[0042] As shown in FIG. 5C, during the time in which transistor 502 is off, there are two conduction intervals of secondary current I.sub.s (periods t.sub.A and t.sub.B). Conduction interval t.sub.A may be referred to as the main conduction interval. Conduction interval t.sub.B (also referred to as the minor conduction interval) occurs when transistor 508 is turned on to let reverse current (I.sub.clamp) flow. Thus, during period t.sub.B, there is simultaneous conduction in the primary and secondary side of converter 500. Although the current peak of secondary current I.sub.s during period t.sub.B is relatively high and may be comparable to the current peak of secondary current I.sub.s during period t.sub.A, the duration of period t.sub.B is shorter than the duration of period t.sub.A.

[0043] In some embodiments, the time between periods t.sub.A and t.sub.B is approximately zero (t.sub.C≈0) at full load (max I.sub.load). As the load decreases (e.g., from max I.sub.load), period tc increases, e.g., to reduce switching frequency and increase light load efficiency.

[0044] In some embodiments, it is desirable to turn on SR transistor 516 during period t.sub.A but not during period t.sub.B. Thus, in some embodiments, secondary current I.sub.s flows through the current path of transistor 516 during period t.sub.A and flows through the body diode of transistor 516 during period t.sub.B. By allowing current I.sub.s to flow through the current path of transistor 516 during period t.sub.A, some embodiments advantageously reduce conduction losses. In some embodiments, by keeping transistor 516 off during period t.sub.B, some embodiments advantageously reduce noise and EMI, allow for a less complex implementation of SR controller 518, and/or advantageously avoid hard switching of transistor 516 (e.g., when turning off transistor 516 at the end of period t.sub.B). In some embodiments, such as in some embodiments operating at frequencies higher than 200 kHz, avoiding hard switching of transistor 516 during period t.sub.B may advantageously result in lower power consumption versus turning on transistor 516 during period t.sub.B.

[0045] The inventor realized that negative edges of voltage V.sub.DS_516 corresponding to period t.sub.A start from a voltage higher than Vout while negative edges of voltage V.sub.DS_516 corresponding to period t.sub.B start from a voltage lower than or equal to V.sub.out. For example, FIGS. 6A and 6B show waveforms associated with SR transistor 516 of ACF converter 500, at full load and light load, respectively, according to an embodiment of the present invention. FIGS. 6A and 6B may be understood in view of FIG. 5.

[0046] It is understood that FIGS. 6A and 6B illustrate a particular example of an embodiment operating with an output voltage V.sub.out of 20 V. Other output voltages, such as lower than 20 V (e.g., 18 V, 13, V, 12 V, 10 V, 5 V, or lower) or higher than 20 V (e.g., 25 V or higher), may also be used.

[0047] As shown in FIGS. 6A and 6B, the negative edges of voltage V.sub.DS_516 corresponding to period t.sub.A (when transistor 516 is turned on) start from a voltage (V.sub.peak) that is higher than the output voltage V.sub.out. For example, in some embodiments, voltage V.sub.peak may be given by

[00001]$\begin{array}{cc}{V}_{\mathrm{peak}}=V_{\mathrm{out}}+\frac{V_{\mathrm{in}}}{n}& \left(1\right)\end{array}$

where n represents the turns ratio of transformer 512.

[0048] The negative edges of voltage V.sub.DS_516 corresponding to period t.sub.B (when secondary current I.sub.s increases but transistor 516 remains turned off) start from a voltage that is lower than or equal to the output voltage Vout.

[0049] The inventor also realized that the fall time of voltage V.sub.DS_516 (illustrated as period t.sub.f in FIG. 6B) corresponding to period t.sub.A (as transistor 502 turns off) is substantially smaller than the time elapsing from a peak of voltage V.sub.DS_516 to a crossing of voltage V.sub.out during period tc (illustrated as period t.sub.r in FIG. 6B). Period t.sub.r corresponds to ¼ of the ringing (resonant) period of voltage V.sub.DS_516.

[0050] In some embodiments, fall time t.sub.f at least one order of magnitude smaller than period t.sub.r. For example, in an embodiment, the ringing period of voltage V.sub.DS_516 is about 840 ns so that period t.sub.r is about 210 ns, while the fall time t.sub.f is about 20 ns.

[0051] In some embodiments, SR transistor 516 is only turned on when the negative edge of voltage V.sub.DS_516 starts from a voltage that is higher than (1+k).Math.V.sub.out and crosses output voltage V.sub.out faster than a predetermined threshold set between the expected t.sub.f and t.sub.r times. In some embodiments, a gating signal (ON_EN) is use to prevent the turn on of transistor 516 when asserted (e.g., low) and allow the turn on of transistor 516 when deasserted (e.g., high).

[0052] FIG. 7 shows a flow chart of embodiment method 700 for generating gating signal ON_EN for controlling SR transistor 516, according to an embodiment of the present invention. Gating signal ON_EN may be used for preventing the turn on of SR transistor 516 when gating signal ON_EN is asserted (e.g., low) and allowing the turn on of SR transistor 516 when gating signal ON_EN is deasserted (e.g., high). In some embodiments, a conventional SR controller may be modified to receive gating signal ON_EN so that the turn on of the SR transistor is prevented when gating signal ON_EN is asserted (e.g., low), while leaving the remainder of the on/off logic of the SR controller unchanged.

[0053] During step 702, a reference voltage V.sub.ref is generated/set to a value higher than output voltage V.sub.out. For example, in some embodiments, reference voltage V.sub.ref is given by

Vef=(1+k).Math.V.sub.out  (2)

where k is a number higher than 0. For example, in some embodiments, k may have a value between 0.2 and 0.5. In some embodiments, reference voltage V.sub.ref may be given by

[00002]$\begin{array}{cc}{V}_{\mathrm{ref}}=V_{\mathrm{out}}+\frac{V_{\mathrm{peak}}-V_{\mathrm{out}}}{2}& \left(3\right)\end{array}$

[0054] During step 704, the drain-to-source voltage of transistor 516 (V.sub.DS_516) is compared with the reference voltage V.sub.ref. When voltage V.sub.DS_516 is higher than reference voltage V.sub.ref, gating signal ON_EN is deasserted (e.g., high).

[0055] After gating signal ON_EN is deasserted (e.g., high), the drain-to-source voltage of transistor 516 (V.sub.DS_516) is compared with the reference voltage V.sub.ref during step 708. When voltage V.sub.DS_516 is lower than reference voltage V.sub.ref, gating signal ON_EN is asserted (e.g., high) during step 712 after a wait time td (during step 710), where the wait time to has a duration between the expected fall time duration t.sub.f and the duration of period t.sub.r.

[0056] In some embodiments, wait time td (also referred to as delay time t.sub.d) may be, e.g., 100 ns. Other values, such as 90 ns, 80 ns, or lower, or 110 ns, 150 ns, or higher, may also be used. In some embodiments, wait time td may be given by

[00003]$\begin{array}{cc}{t}_f<<t_d<<\left(\frac{1}{4}+\frac{k}{2\pi }\right).Math.t_{\mathrm{ring}}& \left(4\right)\end{array}$

where t.sub.ring represents the ringing (resonant) period of voltage V.sub.DS_516 during time tc.

[0057] In some embodiments, the turning on of SR transistor 516 is not gated during period t.sub.A, since gating signal ON_EN is deasserted (step 706) for a period to that is longer than fall time t.sub.f. In some embodiments, the turning on of SR transistor 516 is gated (prevented) during period t.sub.B when operating at full load (e.g., as shown in FIG. 6A) since voltage V.sub.DS_516 increases but remains well below output voltage V.sub.out (output “no” during step 704). In some embodiments, the turning on of SR transistor 516 is gated (prevented) during the first (or first few) valley of period t.sub.B when operating at light load (e.g., as shown in FIG. 6B) since gating signal ON_EN is asserted (step 712) after period to that is shorter than period t.sub.f. In some embodiments, the turning on of SR transistor 516 is gated (prevented) after the first (or first few) valley of period t.sub.B when operating at light load (e.g., as shown in FIG. 6B) since voltage V.sub.DS_516 remains below output voltage V.sub.out (output “no” during step 704).

[0058] FIG. 8 shows a schematic diagram of SR controller 800, according to an embodiment of the present invention. SR controller 800 includes comparators 802, and 804, AND gates 808 and 810, flip-flops 814 and blanking circuit 816, and gating circuit 822. SR controller 518 may be implemented as SR controller 800.

[0059] Comparator 802 is configured to detect when the body diode of transistor 516 is conducting (thereby detecting that secondary current I.sub.s is greater than zero). The output signal S.sub.turn_on of comparator 802 is asserted (high) when voltage V.sub.DS_516 drops below threshold voltage V.sub.th_on. In some embodiments, threshold voltage V.sub.th_on is, e.g., −0.3 V, for example. Other threshold voltages may also be used.

[0060] Comparator 804 is configured to detect when secondary current I.sub.s drops to zero. In some embodiments, such detection is implemented based on the rdson of transistor 516, which operates as a current sensor for sensing secondary current I.sub.s. For example, in some embodiments, signal S.sub.turn_off is asserted (high) when voltage V.sub.DS_516 exceeds threshold voltage V.sub.th_off. In some embodiments, threshold voltage V.sub.th_off is about 0 V, such as 0.5 mV, for example. Other threshold voltages may also be used.

[0061] Gating circuit 822 is configured to generate gating signal ON_EN based on output voltage V.sub.out and voltage V.sub.DS_516. For example, in some embodiments, gating circuit 822 generates gating signal ON_EN in accordance with method 700.

[0062] Blanking circuit 816 is configured to be triggered by a rising edge as well as by a falling edge of voltage V.sub.G_516 (i.e., each time there is a change of state in voltage V.sub.G_516). Blanking circuit 816 is configured to produce (each time blanking circuit 816 is triggered) a negative pulse with a duration t.sub.d1 (also referred to as blanking time, or t.sub.blank) to prevent AND gates 808 and 810 from asserting during period t.sub.d1. In some embodiments, period tai is, e.g., 300 ns. Other values for t.sub.d1 may also be used. In some embodiments, blanking circuit 816 may be implemented in any way known in the art.

[0063] As shown in FIG. 8, during normal operation, signal S.sub.turn_on is asserted (e.g., high) when the body diode of transistor 516 is conducting. However, flip-flop 814 is only set if signal S.sub.turn_on is asserted when gating signal ON_EN is deasserted (e.g., high) and blanking signal S.sub.blank is deasserted (e.g., high).

[0064] Signal S.sub.turn_off is asserted (e.g., high) when secondary current I.sub.s drops to zero. However, flip-flop 814 is only reset if signal S.sub.turn_off is asserted when blanking signal S.sub.blank is deasserted (e.g., high).

[0065] In some embodiments, comparators 802, and 804 may be implemented in any way known in the art. For example, in some embodiments, e.g., as illustrated in FIG. 8, comparators 802 and 804 may be implemented with hysteresis.

[0066] In some embodiments, flip flop 814 is configured to be set (high) based on the output of AND gate 808 and be reset (low) based on the output of AND gate 81o. Flip-flop 814 may be implemented in any way known in the art.

[0067] FIGS. 9A and 9B show a schematic diagram of gating circuit 900, and associated waveforms, respectively, according to an embodiment of the present invention. Gating circuit 900 includes comparator 906, OR gate 912, multiplier 918, and delay circuit 920. Gating circuit 822 may be implemented as gating circuit 900.

[0068] In some embodiments, multiplier 918 is configured to multiply output voltage Vout times (1+k) to generate (e.g., step 702) reference voltage V.sub.ref (e.g., according to Equation 2). Multiplier 918 may be implemented in any way known in the art, such as with an analog amplifier. In some embodiments, reference voltage V.sub.ref may be generated in other ways, such as in accordance with Equation 3.

[0069] In some embodiments, comparator 906 compares (e.g., step 704) voltage V.sub.ref and V.sub.D_516 and asserts signal S.sub.906 when voltage V.sub.DS_516 is higher than voltage V.sub.ref. Comparator 906 may be implemented in any way known in the art. For example, in some embodiments, e.g., as illustrated in FIG. 9A, comparator 906 may be implemented with hysteresis.

[0070] In some embodiments, delay circuit 920 is configured to delay signal S.sub.906 by a time t.sub.d, where t.sub.d is given, e.g., by Equation 4. Thus signal S.sub.920 asserts (high) to time after signal S.sub.906 asserts (high) and deasserts (low) to time after signal S.sub.916 deasserts (low). In some embodiments, delay circuit 920 may be implemented in any way known in the art.

[0071] As can be seen in FIG. 9A, delay circuit 920 and OR gate 912 perform steps 706, 708, 710, and 712. For example, gating signal ON_EN is deasserted (high) when signal S.sub.906 is asserted (high) and gating signal ON_EN is kept deasserted (high) for a duration to after signal S.sub.906 is deasserted (low), as shown in FIG. 9B.

[0072] FIGS. 10 and 11 show waveforms associated with SR controller 800 implementing gating circuit 822 as gating circuit 900 and operating at full load and light load, respectively, according to an embodiment of the present invention. In the embodiment shown in FIGS. 10 and 11, converter 500 is operated as a non-complementary ACF converter, output voltage V.sub.out is 20 V, blanking time t.sub.blank is 300 ns, and k is 0.4 so that V.sub.ref=1.4V. FIGS. 10 and 11 also illustrate the time window to that begins when voltage V.sub.DS_516 crosses output voltage V.sub.out from a voltage higher than V.sub.ref.

[0073] As shown in FIG. 10, at time t.sub.1 (at the beginning of period t.sub.A) gating signal ON_EN is high (since it is within delay time t.sub.d) and blanking signal S.sub.blank is high (since there has not been a state transition of voltage V.sub.G_516 during the 300 ns immediately prior to time t.sub.1). Since signals ON_EN and S.sub.blank are both high, signal S.sub.turn_on propagate via AND gate 808 to flip-flop 814 to cause voltage V.sub.G_516 to transition from low to high, thus turning on SR transistor 516. Thus SR transistor 516 is on during period t.sub.A.

[0074] As shown in FIG. 10, at time t.sub.2, gating signal ON_EN is low (since voltage V.sub.DS_516 has not increased above voltage V.sub.ref) and blanking time is low (since voltage V.sub.G_516 transitioned from high to low less than 300 ns prior to time t.sub.2). Since both blanking signal S.sub.blank and gating signal ON_EN are low, signal S.sub.turn_on is prevented from propagating to flip-flop 814, and thus SR transistor 516 to remain off during period t.sub.B.

[0075] As shown in FIG. 11, at time t.sub.3 (at the beginning of period t.sub.A) gating signal ON_EN is high (since it is within delay time t.sub.d) and blanking signal S.sub.blank is high (since there has not been a state transition of voltage V.sub.G_516 during the 300 ns immediately prior to time t.sub.1). Since signals ON_EN and S.sub.blank are both high, signal S.sub.turn_on propagate via AND gate 808 to flip-flop 814 to cause voltage V.sub.G_516 to transition from low to high, thus turning on SR transistor 516. Thus SR transistor 516 is on during period t.sub.A.

[0076] As shown in FIG. 11, at time t.sub.4, gating signal ON_EN is low (since, even though voltage V.sub.DS_516 increased above voltage V.sub.ref, time t.sub.4 occurs more than t.sub.d time after voltage V.sub.DS_516 crosses output voltage Vout) and blanking time is high (since there has not been a state transition of voltage V.sub.G_516 during the 300 ns immediately prior to time t.sub.1). Since gating signal ON_EN is low, signal S.sub.turn_on is prevented from propagating to flip-flop 814, and thus SR transistor 516 to remain off during period t.sub.B.

[0077] In some embodiments, SR controller 800 may be advantageously used (e.g., without change) in other types of flyback topologies. For example, FIGS. 12A and 12B show a schematic diagram of flyback converter 1200, and associated waveforms, respectively, according to an embodiment of the present invention. Flyback converter 1200 is an RCD clamp flyback converter that implements SR transistor 516 and controls the SR transistor 516 with SR controller 800 implementing gating circuit 822 as gating circuit 900.

[0078] The waveforms illustrated in FIGS. 12B, are associated with flyback converter 1200 being operated in DCM mode, with an output voltage V.sub.out of 20 V, a blanking time t.sub.blank of 300 ns, and k equal to 0.4 so that V.sub.ref=1.4V.sub.out. As shown in FIG. 12B, SR controller 800 causes transistor 516 to turn on and off at the expected times for proper DCM operation.

[0079] Example embodiments of the present invention are summarized here. Other embodiments can also be understood from the entirety of the specification and the claims filed herein.

[0080] Example 1. A method for controlling a synchronous rectifier (SR) transistor of a flyback converter, the method including: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.

[0081] Example 2. The method of example 1, where generating the gating signal includes: determining a reference voltage based on the output voltage; when the first voltage increases above the reference voltage, deasserting the gating signal; and while the gating signal is deasserted, comparing the first voltage with the reference voltage and asserting the gating signal a first delay time after the first voltage drops below the reference voltage.

[0082] Example 3. The method of one of examples 1 or 2, where turning on the SR transistor includes turning on the SR transistor when the turn-on signal is asserted while the gating signal is deasserted.

[0083] Example 4. The method of one of examples 1 to 3, where the first delay time is lower than one quarter of a ringing time of the first voltage.

[0084] Example 5. The method of one of examples 1 to 4, where the first delay time is between 20 ns and 210 ns.

[0085] Example 6. The method of one of examples 1 to 5, where the reference voltage is given by v.sub.ref=(1+k).Math.V.sub.out, where V.sub.ref represents the reference voltage, Vout represents the output voltage, and k is a number higher than 0.

[0086] Example 7. The method of one of examples 1 to 6, where k is between 0.2 and 0.5.

[0087] Example 8. The method of one of examples 1 to 7, where generating the gating signal includes using a gating circuit that includes: a first comparator having a first input for receiving the first voltage and a second input for receiving the reference voltage; a delay circuit having an input coupled to an output of the first comparator, the delay circuit having a delay time equal to the first delay time; and an OR gate having a first input coupled to the output of the first comparator, a second input coupled to an output of the delay circuit, and an output for providing the gating signal.

[0088] Example 9. The method of one of examples 1 to 8, further including generating a blanking signal based on the first voltage, where turning on the SR transistor is further based on the blanking signal, and where turning off the SR transistor is further based on the blanking signal.

[0089] Example 10. The method of one of examples 1 to 9, where asserting the turn-on signal includes asserting the turn-on signal when the first voltage drops below a second threshold, and where asserting the turn-off signal includes asserting the turn-off signal when the first voltage increases above a third threshold.

[0090] Example 11. The method of one of examples 1 to 10, further including operating the flyback converter as a non-complementary active clamp flyback (ACF) converter.

[0091] Example 12. The method of one of examples 1 to 11, further including operating the flyback converter as an RCD clamp flyback converter in discontinuous conduction mode (DCM).

[0092] Example 13. A synchronous rectifier (SR) controller including: an output terminal configured to be coupled to a control terminal of an SR transistor of a flyback converter; and an input terminal configured to receive an output voltage of the flyback converter, where the SR controller is configured to: determine a first voltage across conduction terminals of the SR transistor; assert a turn-on signal when a body diode of the SR transistor is conducting current; assert a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generate a gating signal based on the output voltage of the flyback converter and on the first voltage; turn on the SR transistor based on the turn-on signal and on the gating signal; and turn off the SR transistor based on the turn-off signal.

[0093] Example 14. The SR controller of example 13, where the SR controller is configured to generate the gating signal by: determining a reference voltage based on the output voltage; when the first voltage increases above the reference voltage, deasserting the gating signal; and while the gating signal is deasserted, comparing the first voltage with the reference voltage and asserting the gating signal a first delay time after the first voltage drops below the reference voltage.

[0094] Example 15. The SR controller of one of examples 13 or 14, where the SR controller is configured to turn on the SR transistor when the turn-on signal is asserted while the gating signal is deasserted.

[0095] Example 16. The SR controller of one of examples 13 to 15, further including a gating circuit configured to generate the gating signal, the gating circuit including: a first comparator having a first input configured to receive the first voltage and a second input configured to receive the reference voltage; a delay circuit having an input coupled to an output of the first comparator, the delay circuit having a delay time equal to the first delay time; and an OR gate having a first input coupled to the output of the first comparator, a second input coupled to an output of the delay circuit, and an output configured to provide the gating signal.

[0096] Example 17. The SR controller of one of examples 13 to 16, further including; a turn on circuit configured to generate the turn-on signal; a turn-off circuit configured to generate the turn-off signal; a first AND gate having a first input coupled to an output of the turn on circuit, and a second input coupled to an output of the OR gate; and a first flip-flop having a first input coupled to an output of the first AND gate, a second input coupled to an output of the turn-off circuit, and an output coupled to the output terminal.

[0097] Example 18. The SR controller of one of examples 13 to 17, further including: a blanking circuit having an input couple to the output of the first flip-flop; and a second AND gate having a first input coupled to an output of the blanking circuit, a second input coupled to the output of the turn-off circuit, and an output coupled to the second input of the first flip-flop, where the first AND gate includes a third input coupled to the output of the blanking circuit.

[0098] Example 19. The SR controller of one of examples 13 to 18, where the turn on circuit includes a second comparator having a first input configured to receive a second threshold, and a second input configured to receive the first voltage; and where the turn off circuit includes a third comparator having a first input configured to receive a third threshold, and a second input configured to receive the first voltage.

[0099] Example 20. A flyback converter including: a transformer having first and second windings; an output terminal coupled to the second winding; a first primary transistor coupled to the first winding; a primary controller having an output coupled to a control terminal of the first primary transistor; a synchronous rectifier (SR) transistor coupled to the second winding; and an SR controller configured to: determine a first voltage across conduction terminals of the SR transistor, assert a turn-on signal when a body diode of the SR transistor is conducting current, assert a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold, generate a gating signal based on an output voltage at the output terminal and on the first voltage; turn on the SR transistor based on the turn-on signal and on the gating signal; and turn off the SR transistor based on the turn-off signal.

[0100] Example 21. The flyback converter of example 20, further including a second primary transistor coupled to the second winding, where the primary controller is configured to control the first and second primary transistor to operate the flyback converter as a non-complementary active clamp flyback (ACF) converter.

[0101] Example 22. The flyback converter of one of examples 20 or 21, further including a resistor coupled to the first winding, a capacitor coupled in parallel with the resistor, and a diode coupled between the first primary transistor and the capacitor, where the primary controller is configured to control the first primary transistor to operate the flyback converter as an RCD clamp flyback converter in discontinuous conduction mode (DCM).

[0102] Example 23. The flyback converter of one of examples 20 to 22, where the SR transistor is a metal-oxide semiconductor field-effect transistor (MOSFET) or GaN transistor.

[0103] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.