Temperature sensor semiconductor device with pair of diodes and feedback loop

Abstract

In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

Claims

1. A temperature sensor semiconductor device comprising: a first diode and a second diode of specified sizing or biasing ratio; a negative voltage supply; a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor; an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array of dynamically matched current sources, and wherein the second diode is connected between the negative supply voltage and a second input of the array of dynamically matched current sources; and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array of dynamically matched current sources and a second node present between the second diode and the second input of the array of dynamically matched current sources, wherein the SAR feedback loop comprises a SAR controller, a SAR comparator, a generator for a complementary to absolute temperature (CTAT) voltage, and an adjustable second resistor, which implements a SAR digital-to-analog converter and is configured to convert the CTAT voltage into a proportional current, and wherein the generator for the CTAT voltage is connected to the array of dynamically matched current sources to define a nominal current thereby closing the SAR feedback loop.

2. The temperature sensor semiconductor device of claim 1, wherein the diodes are base-emitter junctions of bipolar transistors.

3. The temperature sensor semiconductor device of claim 1, further comprising a chopped or auto-zeroed integrating preamplifier in front of the SAR comparator configured to convert a step signal into a linear slope signal thereby averaging out DEM transients while amplifying the PTAT voltage.

4. The temperature sensor semiconductor device of claim 3, wherein the integrating preamplifier is configured to employ an open loop transconductance/capacitance stage.

5. The temperature sensor semiconductor device of claim 4, wherein the transconductance/capacitance stage comprises a cascode or a folded cascode.

6. The temperature sensor semiconductor device of claim 3, further comprising a chopping amplifier in the generator for the CTAT voltage.

7. The temperature sensor semiconductor device of claim 1, further comprising: a further first resistor, the further first resistor being connected between the second diode and the second input of the array of dynamically matched current sources, wherein the first diode and the second diode are equally sized and thus forming a symmetric arrangement, and wherein the array of dynamically matched current sources are configured to provide an asymmetrical biasing.

8. The temperature sensor semiconductor device of claim 7, wherein, during a first half of a DEM cycle, the first diode is biased with a current that is higher than a current of the second diode, the first resistor being shorted and the further first resistor being connected to the SAR feedback loop, and wherein, during a second half of the DEM cycle, the second diode is biased with a current that is higher than a current of the first diode, the first resistor being connected to the SAR feedback loop and the further first resistor being shorted.

9. The temperature sensor semiconductor device of claim 1, wherein the second resistor comprises a ladder of unit resistors with Kelvin connections and a plurality of unit resistors in parallel.

10. The temperature sensor semiconductor device of claim 1, further comprising a switch of the generator for the CTAT voltage, wherein the switch is configured to enable an application of a calibration voltage of a prescribed value instead of the generated CTAT voltage.

11. The temperature sensor semiconductor device of claim 10, wherein a SAR conversion with an application of the calibration voltage at a prescribed temperature is configured to yield a correction of a spread in a ratio R.sub.lsb/R.sub.1 of a resistance of the SAR digital-to-analog converter to the first resistor, and wherein a subsequent SAR conversion at the prescribed temperature without application of the calibration voltage is configured to yield a correction of a PTAT spread of the CTAT voltage.

12. A portable smart home device comprising: the temperature sensor semiconductor device of claim 1.

13. A connected smart home device comprising: the temperature sensor semiconductor device of claim 1.

14. A mobile device comprising: the temperature sensor semiconductor device of claim 1.

15. A medical device comprising: the temperature sensor semiconductor device of claim 1.

16. A temperature sensor semiconductor device comprising: a first diode and a second diode of specified sizing or biasing ratio; a negative supply voltage; a first resistor provided for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor; an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array of dynamically matched current sources, and wherein the second diode is connected between the negative supply voltage and a second input of the array of dynamically matched current sources; and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array of dynamically matched current sources and a second node present between the second diode and the second input of the array of dynamically matched current sources.

17. A temperature sensor semiconductor device comprising: a first diode and a second diode of specified sizing or biasing ratio; a negative supply voltage; a first resistor provided for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor; an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array of dynamically matched current sources, and wherein the second diode is connected between the negative supply voltage and a second input of the array of dynamically matched current sources; and a successive approximation register (SAR) feedback loop comprising a SAR controller, a SAR comparator, a generator for a complementary to absolute temperature (CTAT) voltage and an adjustable second resistor, which implements a SAR digital-to-analog converter and is configured to convert the CTAT voltage into a proportional current, wherein the generator for the CTAT voltage is connected to the array of dynamically matched current sources to define a nominal current thereby closing the SAR feedback loop.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The following is a detailed description of examples of the semiconductor device in conjunction with the appended figures.

(2) FIG. 1 is a circuit diagram of a direct SAR temperature sensor topology;

(3) FIG. 2 is a timing diagram for the circuit according to FIG. 1;

(4) FIG. 3 shows example waveforms during one DEM cycle;

(5) FIG. 4 is a circuit diagram of a g.sub.m/C filter with cascode;

(6) FIG. 5 is a circuit diagram of a g.sub.m/C filter with folded cascode;

(7) FIG. 6 is a circuit diagram of a direct SAR temperature sensor topology with extended DEM for bipolar chopping;

(8) FIG. 7 is a circuit diagram of a resistor DAC;

(9) FIG. 8 is a circuit diagram of a conventional CMOS temperature sensor topology; and

(10) FIG. 9 a circuit diagram of a current domain CMOS temperature sensor topology.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(11) In the temperature sensor semiconductor device the temperature sensing front end is embedded in a SAR feedback loop as illustrated in FIG. 1. A corresponding timing diagram for one SAR conversion step is shown in FIG. 2. Neither a PTAT generation amplifier nor a delta-sigma converter is applied. For ten bits (0.1K resolution) only ten SAR cycles are necessary, for example. Hence the conversion time is considerably shorter than the conversion time that can be achieved with a delta-sigma converter.

(12) Instead of driving the voltage V.sub.bip1−V.sub.bip2 to zero in a continuous time feedback loop, the voltage is zeroed in a SAR loop by adjusting a resistor R.sub.2 in a CTAT generator. The CTAT generator comprises a continuous time feedback loop, but the design requirements are relaxed, as V.sub.ctat (V.sub.be) is much larger than ΔV.sub.be, so that errors in clamping V.sub.ctat across the resistor R.sub.2 will be considerably less severe than in a PTAT generator according to FIG. 8. The adjusted CTAT current is mirrored into the pair of diodes, especially the pair of bipolar transistors bip.sub.1, bip.sub.2, and causes a voltage drop across R.sub.1 of V.sub.ctat.Math.R/R.sub.2. By direct comparison the voltage difference V.sub.bip1−V.sub.bip2 is driven to zero at the end of the SAR conversion, so that V.sub.ptat=V.sub.ctat.Math.R.sub.1/R.sub.2. This yields the ratio V.sub.ctat/V.sub.ptat=(R.sub.2+dQ)/R.sub.1=(D.sub.out.Math.R.sub.lsb+dQ)/R.sub.1, where dQ denotes the quantization error in R.sub.2.

(13) Using this ratio, the temperature T.sub.readout can be calculated as
T.sub.readout=A.Math.α.Math.V.sub.ptat/(α.Math.V.sub.ptat+V.sub.ctat)+B=A/[1+V.sub.ctat/(α.Math.V.sub.ptat)]+B or
T.sub.readout=A/[1+(D.sub.out.Math.R.sub.lsb)/(α.Math.R.sub.1)]+B.

(14) Mismatch in the PMOS current mirrors and offset in the CTAT amplifier will affect the final result. These errors could be eliminated by calibration, but the calibration would become invalid over time owing to drift in offset and mismatch. If stability of the sensor over time is a requirement, DEM is applied. As DEM converts DC mismatch and offset into AC ripple, it requires averaging typically provided by the first integrator of a delta-sigma converter. In this temperature sensor an open loop g.sub.m/C stage is employed in front of the comparator. In this way DEM ripple is filtered while v.sub.ptat is boosted before comparison. Amplification of v.sub.ptat is crucial because comparators cannot be practically designed for V accuracy.

(15) The g.sub.m/C stage converts the DEM step signals into linear slope signals. As long as a complete DEM cycle is run before comparison, all mismatch errors are integrated equally long with positive and negative slope. As a result, DEM transients are exactly cancelled while the signal V.sub.ptat is amplified. For instance, assuming an input referred offset V.sub.off at the g.sub.m/C amplifier, then integration for one DEM cycle T.sub.DEM yields
V.sub.out,gm/C=2.Math.g.sub.m/C.sub.int(∫.sub.0.sup.T.sup.DEMv.sub.PTATdt+∫.sub.0.sup.T.sup.DEM.sup./2v.sub.offdt−∫.sub.T.sub.DEM.sub./2.sup.T.sup.DEMv.sub.offdt) or
V.sub.out,gm/C=2.Math.g.sub.m.Math.T.sub.DEM.Math.V.sub.ptat/C.sub.int.

(16) The offset is cancelled because the input chopper chop.sub.1 reverses the offset sign after half a DEM cycle.

(17) In FIG. 3 example waveforms are depicted for one DEM cycle. While the g.sub.m/C output significantly deviates from the signal during the DEM cycle, at the end of the cycle it converges to the signal only.

(18) Compared to an integrator in a delta-sigma converter built from a feedback amplifier, the open loop g.sub.m/C filter has the advantage of eliminating the tradeoff between noise and settling. For an amplifier in feedback the output noise power is proportional to the closed loop bandwidth. This is in conflict with the settling error, which is inverse proportional to the closed loop bandwidth. Hence noise performance is typically determined by the settling requirements of the delta-sigma feedback DAC and input sampler. As the g.sub.m/C integrator is open loop and its output is processed by a comparator, there is no settling and linearity requirement. In consequence, low bandwidth can be implemented for superior noise filtering. The bandwidth for the g.sub.m/C integrator is given by 1/(2.Math.T.sub.DEM).

(19) The g.sub.m/C integrator can be implemented with a fully differential cascode amplifier and capacitive load C.sub.int as shown in FIG. 4. The integration capacitance C.sub.int must be reset between the different SAR cycles to eliminate the previous history. Due to the periodic reset, it also serves as switch capacitor common mode feedback. Although each reset gives rise to charge injection and kT/C noise, it is suppressed by the signal gain 2.Math.g.sub.m.Math.T.sub.DEM/C.sub.int.

(20) Despite the fact that the mismatch waveforms are cancelled towards the end of the DEM cycle, they can before cause large voltage swing at the output (FIG. 3). Depending on matching parameters and supply voltage, a folded cascode amplifier can be used to accommodate this swing, as shown in FIG. 5. If this is not sufficient, the integration capacitance is optionally increased. As the signal gain is thus reduced, an auto zero preamplifier may favourably be employed between the g.sub.m/C output and the comparator input in order to enable auto zeroing during the reset phases.

(21) The DEM switching is illustrated in Tables 1 and 2. The CTAT amplifier and g.sub.m/C stage are chopped. The current mirrors can either be chopped (Table 1) or rotated (Table 2).

(22) TABLE-US-00001 TABLE 1 DEM switching type 1, double chopping of current sources. DEM cycle n.sub.1 n.sub.2 n.sub.3 n.sub.4 chop.sub.1 chop.sub.2 1 M.sub.1 M.sub.2 M.sub.3 M.sub.4 0 0 2 M.sub.2 M.sub.1 M.sub.4 M.sub.3 0 0 3 M.sub.3 M.sub.4 M.sub.1 M.sub.2 1 1 4 M.sub.4 M.sub.3 M.sub.2 M.sub.1 1 1

(23) TABLE-US-00002 TABLE 2 DEM switching type 2 (rotation of current sources). DEM cycle n1 n2 n3 n4 chop1 chop2 1 M1 M2 M3 M4 0 0 2 M4 M1 M2 M3 0 0 3 M3 M4 M1 M2 1 1 4 M2 M3 M4 M1 1 1

(24) If the bipolar transistors are expected to experience significant flicker noise and drift, they also require DEM. Direct chopping of the bipolar transistors bip.sub.1, bip.sub.2 is avoided, because switches would be required that would introduce voltage drops much in excess of the required resolution of less than 15 PV.

(25) A circuit according to FIG. 6 can favourably be applied. In this circuit PTAT resistors R.sub.1a, R.sub.1b are implemented on both sides, and the arrangement is symmetric with bipolar transistors of equal size. Asymmetry is introduced by asymmetrical biasing, which is provided by the current mirror DEM controller (Table 3).

(26) TABLE-US-00003 TABLE 3 Extended DEM switching for N = 3. DEM cycle n.sub.1 n.sub.2 n.sub.3 n.sub.4 chop.sub.1 chop.sub.2 1 M.sub.1 M.sub.2 M.sub.3 M.sub.4, M.sub.5, M.sub.6 0 0 2 M.sub.6 M.sub.1 M.sub.2 M.sub.3, M.sub.4, M.sub.5 0 0 3 M.sub.5 M.sub.6 M.sub.1 M.sub.2, M.sub.3, M.sub.4 0 0 4 M.sub.5 M.sub.4 M.sub.1, M.sub.2, M.sub.3 M.sub.6 1 1 5 M.sub.4 M.sub.3 M.sub.6, M.sub.1, M.sub.2 M.sub.5 1 1 6 M.sub.3 M.sub.2 M.sub.5, M.sub.6, M.sub.1 M.sub.4 1 1

(27) During the first half of the DEM cycle, the left bipolar transistor is biased with higher current, and R.sub.1b is connected to the g.sub.m/C filter via Kelvin switches. R.sub.1a is shorted to keep the voltage swings at the drain of the PMOS current sources approximately equal. During the second half of the DEM cycle, the switching is reversed, and the right bipolar transistor is biased with higher current. Such an operation effectively chops the bipolar transistors along with the resistors R.sub.1a and R.sub.1b.

(28) The resistor DAC R.sub.2 is depicted in FIG. 7. Ten bits are needed for a resolution of 0.1K in a 100 K range. In order to implement these bits efficiently with precise matching, five MSBs and five LSBs are implemented separately. For the MSBs a ladder of unit resistors with Kelvin connections is employed. This allows to choose all resistor values corresponding to the five MSBs without introducing any voltage drops across switches. Implementing the ladder down to the LSBs would require very small unit resistors with poor matching. Hence the LSB values are implemented by switching MSB sized unit resistors in parallel. Switches are required to implement all LSB values in this way. The LSBs are connected at the bottom of R.sub.2, because low on-resistance can easily be achieved with switching at ground level.

(29) The readout temperature depends on the resistor ratio R.sub.1/R.sub.lsb and the absolute value of V.sub.ctat, according to the above equation for T.sub.readout. R.sub.lsb=R.sub.unit/32 with R.sub.unit denoting the unit resistor in the DAC shown in FIG. 7. It is the minimum resistor step switchable by the DAC, which is controlled by the DAC LSB input D(0). A variation of R.sub.1/R.sub.lsb can be taken account of by a correction factor c.sub.cal1. V.sub.ctat typically exhibits a PTAT spread, and the real value for V.sub.ctat can be assumed to be V.sub.ctat,nominal−c.Math.T. The value of V.sub.ctat/V.sub.ptat becomes (V.sub.ctat,nominal−cT)/V.sub.ptat=V.sub.ctat,nominal/V.sub.ptat−c.sub.off. The PTAT error in V.sub.ctat can be compensated with a calibration constant c.sub.cal2 to cancel c.sub.off. The corrected readout temperature thus obtained is T.sub.readout=A/[1+(D.sub.out.Math.R.sub.lsb)/(α.Math.R.sub.1.Math.(1+c.sub.cal1))+c.sub.cal2]+B.

(30) A two-step calibration on a temperature stabilized wafer chuck can be performed to extract both parameters. During the first step, a known external voltage V.sub.ext is applied instead of V.sub.ctat as illustrated in FIG. 1 for calibration equal to one. Alternatively, an internal voltage can be applied and measured. The value of the voltage is arbitrary as long as it is known. The nominal ratio V.sub.ctat/V.sub.ptat for the external voltage at the wafer chuck temperature can be determined from simulation or characterization. A SAR conversion with this calibration is performed, and V.sub.ctat/V.sub.ptat is compared to the nominal value from simulation or chip characterization: V.sub.ctat/V.sub.ptat=(D.sub.out.Math.R.sub.lsb)/[R.sub.1.Math.(1+c.sub.cal1)]=D.sub.out,nom.Math.R.sub.lsb/R.sub.1. Hence c.sub.cal1=D.sub.out/D.sub.out,nom. After extraction of c.sub.cal1, the PTAT error of V.sub.ctat can be extracted by performing a conversion in normal mode (internal V.sub.ctat, calibration equal to zero) at the wafer chuck temperature T.sub.chuck, which yields the value of c.sub.cal2 as c.sub.cal2=A/(T.sub.chuck−B)−1−(D.sub.out.Math.R.sub.lsb)/[α.Math.R.sub.1.Math.(1+c.sub.cal1)].

(31) The described topology places the analog front end into a SAR loop, so that front end and ADC are combined. This topology is compatible with an accurate bipolar front end and dynamic element matching. Voltage comparison is directly performed on V.sub.ptat. Dynamic element matching is enabled by employing a g.sub.m/C filter in front of the SAR comparator.

(32) An advantage of the described temperature sensor is faster conversion using a SAR feedback loop and elimination of active circuits such as PTAT generation amplifier and delta-sigma integrators. A further advantage is a tolerance to mismatch and drift.