CMOS optical sensor with a scalable repairing scheme for repair defective readout channels providing a further function of row noise suppression and corresponding row noise suppression method

Abstract

A CMOS optical sensor comprises spare readout channels to replace readout channels found defective at the end of the manufacturing process. These spare readout channels are dispatched over the width of the optical sensor (corresponding to the row direction) in the form of spare groups G.sub.m1, G.sub.m2, Gm.sub.3 of m spare readout channels each, m integer at least equal to 1. Each spare group is inserted between two successive default groups Gn.sub.1 and Gn.sub.2 of n default readout channels each and coupling means SW1 are configured to replace a defective default readout channel in a default group as well as any default readout channels of the group between the defective one and the spare group next to the default group of concern. Advantageously, for a row Row.sub.i being currently selected for CDS reading each pixel in the row, a row noise level V.sub.RN.sub.i is obtained from the A spare readout channels that are not used in the implemented repairing scheme, by sampling an analogic DC reference signal by each of the A spare readout channels and averaging the A values Sp.sub.k obtained. The row reference value V.sub.RN.sub.i is then subtracted from each of the pixel digital signal S.sub.i,j outputs for the current selected row, to finally obtain a signal value d.sub.i,j with row noise suppression.

Claims

1. A CMOS optical sensor comprising a pixel array (1) comprising P rows and N columns of pixels, P and N integers, wherein the pixels belonging to a same column are connected to a respective column conductor and a readout circuitry (2) coupled to the N column conductors of the pixel array to output a digital pixel value (S.sub.i,j) for each pixel in a selected row, characterized in that the readout circuitry comprises: a. N default readout channels (RoC.sub.1 to RoC.sub.N), one per respective column conductor (Col.sub.j) of the pixel array (1) and M spare readout channels (RoCsp.sub.1 to RoCsp.sub.3), with M<N, b. the N+M readout channels are arranged by groups in a repetitive pattern sequence in a row direction of one default group of n successive default readout channels then one spare group of m successive spare readout channels, n and m, integers, N/n integer greater than 1; and M/m integer greater than 1, and c. N switching circuits SW1, one per column conductor of the pixel array, each switching circuit configured to electrically connect a respective one of the N column conductors to one readout channel of the readout circuitry selected among: a default channel (RoC-D) for said column conductor, a first replacement readout channel on a left side of said default readout conductor (RoC-L), a second replacement readout channel on a right side of said default readout conductor (RoC-R), wherein said readout circuitry is configured to set the first switch circuits SW1 such that, when in a default group (Gn.sub.2) comprises a defective readout channel, one of a left shift coupling pattern or a right shift coupling pattern applies, wherein the left shift coupling pattern selects said first, left, replacement readout channel as a replacement to each of the readout channels of said default group starting from the defective readout channel (RoC.sub.11) down to the first readout channel (RoC.sub.9) of said default group, wherein the right shift coupling pattern selects said second, right, replacement readout channel as a replacement to each of the readout channels in said default group starting from the defective readout channel (RoC.sub.15) up to the nth readout channel (RoC.sub.16) in said default group.

2. The CMOS optical sensor of claim 1, in which m=1 and the first, left, replacement readout channel in each first switching circuit is the readout channel next on the left side to the default readout channel, and the second, right, replacement readout channel is the readout channel next on the right side to the default readout channel.

3. The CMOS optical sensor of claim 1, in which m>1, wherein the replacement pattern is on a m group basis and the first, left, replacement readout channel in each first switching circuit is a readout channel at m ranks further on the left side to said default readout channel, and the second, right, replacement readout channel is the readout channel at m ranks further on the right side to said default readout channel.

4. The CMOS optical sensor of claim 3, in which the m first switches SW1 associated with each subset (SS.sub.1, SS.sub.u) of m default readout channels in a default group (Gn.sub.1) are configured through a same logic command (C.sub.10.1).

5. The CMOS optical sensor of any of claim 1 wherein n is at least equal to 8.

6. The CMOS optical sensor of claim 3, wherein m is at least equal to 4.

7. The CMOS optical sensor of claim 1, further comprising: an analog DC voltage reference bus (B.sub.DC) which extends in the row direction over the width of the readout circuitry and second switching circuits (SW2), one per spare readout channel, each of said second switching circuit to selectively connect the respective spare readout channel when unselected by any first switching circuit (SW1), to said reference bus (B.sub.DC), wherein the N and M readout channels are all configured to implement a correlated double sampling (CDS), and the readout circuitry further implements a digital row noise suppression function and is configured for calculating an average row noise value (RN.sub.i) from digital signals (Sp.sub.1) obtained from the spare readout channel(s) operatively coupled to the DC reference bus through the second switch circuits (SW2) and not selected through any of the first switch (SW1) and for subtracting said average row noise value from each of the pixel values for the current selected row (Row.sub.i) provided by the readout channels operatively coupled to respective column conductors of the array through the first switch circuits (SW1).

8. The CMOS optical sensor of claim 7, comprising a third switching circuit (403) configured to timely apply an analog DC voltage reference to the DC reference bus (B.sub.DC) before a CDS reading phase in the readout channels for a current selected row (Row.sub.i).

9. The CMOS optical sensor of claim 8, further comprising buffers (404) distributed over the length of the reference bus (B.sub.DC) between an output line (405) of the third switching circuit (403) and the reference bus (B.sub.DC).

10. The CMOS optical sensor of claim 7, wherein the analog DC voltage reference is set to correspond to a mid-range value of an analog to digital conversion range implemented in the readout circuitry.

11. The CMOS optical sensor of claim 7, comprising a digital to analog conversion circuit (401) delivering the analog DC voltage reference.

12. The CMOS optical sensor of claim 1 in which each of the first and second switching circuits are configured through a respective programmable shift register.

13. The CMOS optical sensor of claim 1, in which the analog to digital conversion in each readout channel is operated by an analog to digital converter proper to the readout channel.

14. The CMOS optical sensor of claim 1, in which the analog to digital conversion in each readout channel is operated by an analog to digital converter shared by the readout channels.

15. The CMOS optical sensor of claim 4, wherein n is at least equal to 8.

16. The CMOS optical sensor of claim 4, wherein m is at least equal to 4.

17. The CMOS optical sensor of claim 9, wherein the analog DC voltage reference is set to correspond to a mid-range value of an analog to digital conversion range implemented in the readout circuitry.

18. The CMOS optical sensor of claim 10, comprising a digital to analog conversion circuit (401) delivering the analog DC voltage reference.

19. A reading method in the CMOS optical sensor according to claim 7 with temporal row noise, comprising, switching the analog DC reference voltage to the DC reference bus, and repeating, for each selected row (Row.sub.i) of the pixel array: a. reading a signal on each of the column conductors through a respective readout channel selected through the first switch (SW1) and outputting a sampled digital pixel value (S.sub.i,j); b. reading a signal on the DC reference bus through each of the spare readout channels selected by the second switches (SW2) and outputting a row noise value (Sp.sub.1); c. computing an average voltage reference value (RN.sub.i) for the current selected row (Row.sub.i) from the row noise values; d. subtracting the average voltage reference value (RN.sub.i) from each of the digital pixel value (S.sub.i,j); e. outputting the resulting digital pixel values (d.sub.i,j) with lower noise for the current selected row.

20. The reading method of claim 19, comprising setting the analog DC reference voltage to a mid-range value of an analog to digital conversion range.

Description

(1) Other characteristics and advantages of the invention will now be described, by way of non-limiting examples and embodiments, with reference to the accompanying drawings, in which:

(2) FIG. 1 illustrates a general block diagram of an optical sensor in an example embodiment comprising one analog to digital converter shared by the readout channels of the readout circuitry;

(3) FIG. 2 is a variant of FIG. 1 when each readout channel comprises its own analog to digital converter;

(4) FIG. 3 illustrates a schematic diagram of a readout circuitry including a repairing circuitry with spare readout channels dispersed among the default readout channels on the basis of one spare readout channel every n default readout channel according to a first example embodiment of the invention, for an optical sensor with analog to digital conversion means included in each readout channel as illustrated in FIG. 2, and a row noise reduction stage based on unused spare readout channels;

(5) FIG. 4 is a schematic diagram of a row noise reduction process according to the invention;

(6) FIG. 5 shows in the schematic diagram of FIG. 3, the related couplings and row noise reduction operation in case of two defective default readout channels being replaced according to the principles of the invention;

(7) FIG. 6 illustrates an example of a readout channel selection circuit and programming tools adapted to a repairing circuitry according to the first embodiment of the invention;

(8) FIG. 7 illustrates a schematic diagram of a repairing circuitry and row noise reduction stage according to a second example embodiment of the invention providing m>1 spare readout channels every n default readout channels;

(9) FIG. 8 illustrates an example implementation of a analog DC reference generation and distribution over a reference bus through distributed buffers in a row direction and an associated selection circuit to couple the reference bus only with unused spare readout channels according to the row noise reduction aspect of the invention;

(10) FIG. 9 illustrates a simplified chronogram of a CDS readout sequence in an optical sensor comprising spare readout channels and selection circuits to implement both a repairing function and a row noise reduction function according to the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

(11) FIGS. 1 and 2 both illustrate the main circuit elements of a CMOS optical sensor. The difference between the two figures stands only in the analog to digital conversion circuit being either shared by all the pixels (FIG. 1) or common to only the pixels in a same column (FIG. 2). Note that other configurations may exist, and for instance, a same ADC could be shared by pixels of a subset of columns. Also, especially when the optical sensor has a large array, which means thousands of rows and columns, it is common art to provide for two readout circuitries, one on foot of the columns and the other on top of the columns, to achieve speediness. Everything that is going to be said in relation with the invention applies to any of these different configurations, and in particular to that of FIG. 1 and FIG. 2 as well.

(12) A basic CMOS optical sensor is illustrated in FIGS. 1 and 2. Note that the term CMOS applies in fact to the electronic circuits around the pixel array, in particular the readout circuitry and the decoders. The pixels uses MOS elements, including photodiodes or photogates as photosensitive elements, and MOS transistors to assume at least a function of selection of the pixel in the array, to read it, and then we speak of passive pixels. But the pixels are preferably active pixels, and we speaks generally then of APS pixels and APS sensor. This means that the pixel structure includes more than one transistor, specifically X transistors where X is equal to or higher than 3. The structure is then 3T, 4T, 5T, or more. These XT structures enable to control different mode of operation of the pixels, in particular: the integration (linear, logarithmic) by the pixels can be in rolling or global shutter mode, with electron multiplying effect . . . etc; and the reading mode: CDS, binning, etc. The X transistors of a XT pixel structure can be all proper to the pixel or some can be shared with other pixels.

(13) The sensor comprises then pixels organized in an array 1, and which have a pixel structure comprised basically of a photosensitive element (photodiode, photogate) and transistors (MOS). The array 1 comprises P rows (Row.sub.1 to Row.sub.P) and N columns (Col.sub.1 to Col.sub.N) of pixels (P, N integers greater than 1). The pixels are noted PX.sub.i,j where i, an integer equal to 1 to P represents the rank of the row in a column direction; and j, an integer equal to 1 to N represents the rank of the column in a row direction. The pixels arranged in one and the same column are coupled to a respective column conductor among the N of the array. The pixels arranged in one and the same row are controlled by a respective row selection line among the P row selection lines of the array. Speaking of large arrays, N and P may equate several thousands, around 8000 for example.

(14) A readout circuitry 2 to read the pixels of the array comprises N readout channels RoC.sub.1 to RoC.sub.N, each readout channel RoC.sub.1 (j integer equal to 1 to N) coupled with the column conductor (Col) of same rank j in the array 1, to enable the production at the output of the readout channel of a signal representative of an illumination level received by a selected pixel in the corresponding column. The term “coupled” means connected, directly or through any coupling element.

(15) In FIG. 1, the output of the readout channels is an analogic signal: each output is sequentially sent for digital conversion to a fast ADC (analog to digital converter) 3, under control of a column decoder 5. In FIG. 2, the output of the readout channels is a digital signal, each readout channel comprising its own ADC.

(16) A readout channel classically comprises a sample and hold circuit, to obtain an analog sampled signal representative of an illumination level of a selected pixel, which is then digitized. Amplifiers are generally provided before the sample and hold circuit, for loading purpose, in view of the high capacitance of either the column conductors upstream. In case of an ADC shared by multiple readout channels (FIG. 1), output amplifiers may also be provided to load the output line conductor 7 between the readout channels and the ADC.

(17) The sequencing of the pixels and the readout circuitry is made through an addressing circuit comprising a row decoder 4, to sequentially select one row at a time, in the readout sequence of the array, and the column decoder 5, to sequentially forward the signal delivered by each readout channel, towards the ADC converter 3 (FIG. 1) or a data shift register 6 (FIG. 2). In final, digital data information DATA of the captured image are sent to a digital processor DSP for further processing including post processing for enhancing the image quality and processing(s) specific to the application. The DSP may be integrated in all or in part in the optical sensor integrated circuit. This means that some post processing operations may be done inside the optical sensor, which comprise for instance statistical computation on the data flow such as histograms, and others applicative operations are done in an applicative DSP outside the optical sensor.

(18) The decoding circuits 4 and 5 operate under proper clock signals generated by a sequencing circuit (not illustrated) which generates all the signals needed to control the integration sequence by the pixels and the reading sequence of the pixels for each capture frame, and in particular controls the row and column decoders. This is all well-known art.

(19) In practice, the readout channels generally implement CDS, which means that two samples are obtained from each pixel. The CDS subtraction between a reset signal and an information signal is obtained before (in analogic) or in the course of the analog to digital conversion. For instance, with an ADC based on a linear ramp, a counter is used which is configured in up-counting mode for one sample and in down-counting mode for the other sample. The resulting signal is in particular free of fixed pattern noise and kTC noise generated at the pixel.

(20) The invention will be now explained in details in the following description, with reference to FIGS. 3 to 9. It can be implemented in any CMOS optical sensor, having the general characteristics explained above in relation with FIGS. 1 and 2. Note that the invention is not limited to a particular ADC converter type but applies generally to any type of ADC (ramp with single or dual slope, SAR, sigma delta, etc.); and is not limited to the configurations illustrated on FIGS. 1 and 2, with one ADC shared by the N readout channels (FIG. 1), or one ADC per channel (FIG. 2).

(21) According to the invention, the CMOS optical sensor comprises spare readout channels like RoCsp.sub.1 in FIG. 3, to replace readout channels found defective at the end of the manufacturing process. These spare readout channels are dispatched over the width of the optical sensor (corresponding to the row direction) in the form of spare groups G.sub.m1, G.sub.m2, Gm.sub.3 of m spare readout channels each, m integer at least equal to 1, each spare group being inserted between two successive default groups of n default readout channels each. For instance in FIG. 3, the spare group Gm.sub.1 is inserted between the two default groups Gn.sub.1 and Gn.sub.2. On a practical level, this insertion of spare channels among default readout channels is possible because the width of a readout channel is less than the pixel pitch of the array, and the total number of spare readout channels is only a fraction of the total number of default readout channels. For instance: if we add 1 spare readout channel every 32, the readout channel pitch needs to be reduced by 3%. In a 8K pixel array, 8192 columns, it would mean we have 256 spare readout channels.

(22) At the end of the manufacturing process, if any default readout channel is found defective in a default group, coupling means are configured to replace the defective default readout channel as well as any default readout channels between the defective one and the spare group next to the default group of concern, preferably the nearest spare group with respect to the position or rank (in the default group) of the defective readout channel. To be complete, this supposes that the defective spare readout channel is not itself defective, but in practice, the probability in a large array that a spare readout channel is defective is very low (there are far less spare readout channels than defaults ones). Also, there is still the possibility then to use the next spare group, as will become apparent from the description below.

(23) According to whether the spare groups comprises just one spare readout channel or more than one readout channel, the replacement scheme is built on a one to one basis (first embodiment) or per groups of m default readout channels (second embodiment). This is to be explained in details below.

(24) According to another aspect of the invention, the spare readout channels that remain unused (after the repairing step of the defective readout channels), are used to sample an analogic DC reference signal from a reference bus and convert it in digital, at the same time that the pixels in a current selected row of the array are read. This makes it possible to obtain from each spare readout channel, a DC ref value (digital) from a respective readout channel and ADC exactly through the same readout electronic and driving mechanism as the one for any data signal S.sub.i,j from the pixels in the selected row Row.sub.i. In particular the CDS reading applies the same way, which enables in fact to obtain a value that represents a row noise level for the current selected row. We call this value a row reference value V.sub.RN.sub.i, which is an average of the DC Ref values obtained from each of the unused spare readout channels, which is expressed as follows: V.sub.RN.sub.i=ΣSp.sub.k/A, where A is the number of unused spare channels and k, an integer, equal to 1 to A, corresponding to a rank of the A unused spare channels with reference to a row direction, from instance from the left to the right in the plane of the drawing sheet of FIG. 3.

(25) This row reference value V.sub.RN.sub.i is then subtracted from each of the pixel digital signal S.sub.i,j outputs for the current selected row, Row.sub.i, to finally obtain a low-noise signal value d.sub.i,j, in which the row noise is suppressed or at last reduced.

(26) This row noise suppression process is summarized in the diagram of FIG. 4. It requires than at least one spare readout channel is unused, but this is what happens in practice. Then at each new selected row, a new DC reference is obtained which is subtracted from each pixel signal S.sub.i,j, to deliver a low noise signal d.sub.i,j. This row noise suppression process is performing because, in addition to taking into account the vertical variation of the row noise, by computing a new reference value at each new selected row, it takes in account the row noise variation over the length of the row (horizontal variation), which has been found to be not negligible in practice. The latter is thanks to the dispersion over the length of the row of the spare readout channels (or spare groups). Finally, as well known, the row noise in the pixel signals is reduced by the factor square root of A, where A is the number of spare readout channels used to generate the reference value.

(27) Note that the DC reference signal used for this row noise suppression is in practice a DC analogic voltage, which level is determined with respect to the ADC range, to be in the range of conversion of the ADC, preferably in the middle range, so that the row noise evaluation is coherent with the ADC converting range.

(28) This can be adapted easily in any sensor for any application through providing a programmable register associated with a DAC preferably inside the sensor itself, to generate a specified analogic voltage. This and other further details on how the DC reference signal is generated will be detailed later in the description.

(29) But before, the repairing process is now described in details, with reference to different embodiments of the invention.

First Embodiment

(30) A first embodiment of the present invention is illustrated on FIG. 3. Note that to improve the readability of the figure, the pixel array 1 is not represented in details, except the extremity of the columns conductors Col.sub.1 to Col.sub.N, which are each to be operatively coupled to a respective readout channel of the readout circuitry 2.

(31) We will first describe the repairing means, and then the row-noise-suppression means.

(32) Repairing Means

(33) According to a first embodiment of the invention, the readout circuitry 2 comprises spare readout channel and configurable coupling means to achieve the coupling of a column conductor with its default readout channel or with a different readout channel according to a repairing pattern defined according to the number and position of the defective channels found.

(34) Spare readout channels are inserted among the default readout channels, on the basis of one spare readout channel every n default readout channels. In other words, each spare group is composed of a single spare readout channel and the default readout channels are grouped by sequence of n successive readout channels, which gives the groups Gn.sub.1, Gn.sub.2 and Gn.sub.3 on FIG. 3, with n=8. Note that n=8 is only for the purpose of the illustration in the reduce space of a drawing sheet. In fact n will generally be greater, for instance equal to 32. This is to compare with the statistics on the number of defective readout channels for a given technology. The ratio of 1/128 is realistic for nowadays large array CMOS sensors.

(35) In the example, with a convention of a column rank increasing in a row direction from the left to the right as illustrated in the figures, the first default group Gn.sub.1 is the one for the n first column conductors Col.sub.1 to Col.sub.8; the second one Gn.sub.2, is for the n successive column conductors Col.sub.9 to Col.sub.16 . . . etc. A first spare group Gm.sub.1 comprising one spare readout channel RoCsp.sub.1 is then provided between Gn.sub.1 and Gn.sub.2; another spare group Gm.sub.2 comprising one spare readout channel RoCsp.sub.2 is provided between Gn.sub.2 and Gn.sub.3, and so on. Note that it is not necessary in practice to provide for a spare group on the left side of the first default readout column RoC.sub.1 of the first default group Gn.sub.1, and neither on the right side of the last default readout column RoC.sub.N (belonging to the last default group Gn.sub.N/n).

(36) N Switching circuits SW1 as multiplexing elements to couple each of the N column conductors of the array 1 to one readout channel selected among three readout channels of the readout circuitry 2, that are, for a given column conductor: a. a default readout channel RoC-D, which is that normally coupled with the given column conductor; b. a first replacement readout channel RoC-L next to the default readout channel on the left side (in the row direction) and this first replacement readout channel can be a “default” or a “spare” type readout channel, according to the rank of the default readout channel in its default group, c. a second replacement readout channel RoC-R next to the default readout channel on the right side (in the row direction) and this second replacement readout channel can be a “default” or a “spare” type readout channel, according to the rank of the default readout channel in its default group.

(37) Note that readout channel “next to” on the right side (or the left side) means the one immediately successive in the right row direction (or the left row direction).

(38) Let us take the column conductor Col.sub.j in the default group Gn.sub.2 as shown in FIG. 3. Its default readout channel RoC-D is RoC.sub.j. Its first replacement readout channel RoC-L is a “default” type one, RoC.sub.j−1, because RoC.sub.j in FIG. 3 is not the first channel (at the first rank in the left row direction) in the default group Gn.sub.2. The first rank channel of Gn.sub.2 is RoC9 and, the “left” readout channel RoC-L for RoC.sub.9 is the spare readout channel, RoCsp.sub.1 between Gn.sub.1 and Gn.sub.2. Similarly, its second replacement readout channel RoC-R is a “default” type one, RoC.sub.j+1, because RoC.sub.1 is not the last channel in Gn.sub.2 (at the n rank in the right row direction). The last rank channel of Gn.sub.2 is RoC.sub.16, and the “right” readout channel RoC-R for RoC.sub.16 is the spare readout channel RoCsp.sub.2 between Gn.sub.2 and Gn.sub.3.

(39) FIG. 5 illustrates a repairing pattern combining both channel shifting to the right and to the left inside a default group Gn2, then using the two spare readout channels framing Gn.sub.2 on its left and right case. In the example, two default readout channels RoC.sub.11 and RoC.sub.15 have been found defective in Gn.sub.2, which are the readout channels respectively at rank 3 and 7 in Gn.sub.2. These defective channels are represented with a wave pattern in the figure.

(40) Then the repairing schema in Gn.sub.2 according to the above principle applies as follows: RoC.sub.15 up to RoC.sub.16 are each replaced with their second replacement readout channel RoC-R, which are respectively RoC.sub.16 for RoC.sub.15, and RoCsp.sub.2 for RoC.sub.16; this corresponds to a right shift coupling pattern. RoC.sub.11 down to RoC.sub.9 are each replaced with their “left” readout channel RoC-L, which are respectively RoC.sub.10 for RoC.sub.11, RoC.sub.9 for RoC.sub.11 and RoCsp.sub.1 for RoC.sub.9; this corresponds to a left shift coupling pattern. RoC.sub.12 up RoC.sub.14 are not replaced, and are the operational readout channels for their respective column conductors. This corresponds to the default coupling pattern.

(41) In practice, the coupling of each column conductor to a respective readout channel among the three possibilities is implemented through configuration of the switch circuits SW1 (analog multiplexer): the input of each first switch SW1 is connected to an extremity of a respective column conductor, and the switch is configured to route the input to a single one of three outputs RoC-L, RoC-D and RoC-R. This means that the logic command on the three “elementary” switches in each switch SW1 can take only 3 combinations: “010”, which corresponds to the default output, RoC-D (see switches associated with RoC.sub.4 and RoC.sub.5 in Gn.sub.2); “100”, which corresponds to a left shift coupling pattern, enabling the RoC-L output (see switches associated with RoC.sub.9 to RoC.sub.11 in Gn.sub.2); or “001”, which corresponds to a right shift coupling pattern, enabling the RoC-R output (see switches associated with RoC.sub.15 and RoC.sub.16 in Gn.sub.2). Then a two bit logic signal is enough to program/configure one over the three combinations in each switching circuit SW1, as illustrated by the decoding table TAB1 in FIG. 6. In the example a shift register Set-SW1 is associated to a number of logical circuits each producing the set of switch signals to control one switch circuit SW1. 2 bits of the shift register generates one command set [Sel-L, Sel-R and Sel-R] applicable to a respective switch circuit SW1, for example that associated with RoC.sub.1. In practice, the shift register is a set of elementary shift registers in series to generate the N command sets [Sel-L, Sel-R and Sel-R] for the N switching circuits SW1.

(42) These first switches SW1 are on the input side of the readout circuitry 2. At the output side, the column decoder is able to implement a decoder process that takes in account the coupling pattern implemented by the switch circuits SW1. This means that the column decoder will successively select N readout channels per image frame, that are the N channels operatively used for reading the N pixels in each row. Or else, that the column decoder will sequentially select each of the readout channels implemented in the circuitry 2, either default and spare ones, and the correct data will be sorted out by the DSP according to the implemented coupling pattern.

(43) Although FIGS. 3 and 5 show a readout circuitry in which each readout channel has its own ADC, such that the outputs are digital outputs to be transmitted in series sequentially through a data shift register 6 towards a DSP (FIG. 2), the same would apply in case of analogic outputs to be sequentially applied for conversion to a fast ADC (FIG. 1).

(44) But, as illustrated in FIGS. 3 and 5, switch circuits SW1′ realizing the inverse routing function of input first switches SW1 may be implemented in real (instead of by software as proposed in the preceding paragraph), each to route the output delivered by a RoC-L or RoC-R replacement channel back to the corresponding default output signal line. The input command for the corresponding circuits SW1 and SW1′ is exactly the same, which limits the need in configurable/programmable means to configure the switching circuits. For instance, where the left output (RoC-L) was selected at the input by one SW1 circuit, the left input (Roc-L) is selected by the corresponding one SW1′ circuit at the output. This representation in hardware is convenient to make clear the whole repairing scheme. But it is also convenient for purpose of the description to yet explain another aspect of the present invention, when a row noise suppression function is advantageously implemented, based on unused spare readout channels, where unused means not selected for repairing purpose in the coupling pattern by the switches SW1. But as explained above, in practice, all these routing aspects at the output of the readout channels of the readout circuitry can be managed easily by the column decoder and/or the DSP processor and the present invention is not limited to an hardware implementation of the data routing at the output of the readout circuitry, but applies to a software implementation as well.

(45) Row Noise Suppression

(46) The general principle is illustrated on FIG. 3, while the row noise suppression process is detailed on the diagram of FIG. 4 and FIG. 5 illustrates a practical case where some spare readout channels are used for the repair and remaining spare readout channels can be used for the row noise suppression function according to the invention. According to the invention, when the sensor integrated circuit has been tested and defective readout columns identified, a coupling pattern is determined and implemented (SW1) which uses spare readout channels. Then a first determination is made (step 300, FIG. 4) of how many spare readout channel remain unused. This gives the number A of remaining spare readout channels, together with the position (address) of these A spare readout channels. Note that in practice A is never zero and the A remaining spare readout channels may be sparse over the length of the row. We can assign them a rank k, increasing in the row right direction (by convention) from 1 to A.

(47) These A spare readout channels are used to sample an analog DC reference voltage DC_ref applied to a reference bus B.sub.DC. This is obtained through a second switch circuit SW2 comprising one multiplexing element per spare readout channel to couple with the reference bus B.sub.DC that extends in the row direction over the length of the readout circuitry 2. For each spare readout channel, the respective SW2 multiplexing element is activated only when the spare readout channel is not used for repair (through SW1). At the output of the spare channels, we have represented a switch SW2′, which is to make the signal delivered by the spare channel be delivered as a spare signal to the row noise suppression stage, when the spare channel is not used in the repairing pattern. SW2′ is exactly in the same state than SW2 (which means a same logic command applying to set both). But as explained above. This hardware representation may not be necessary as the DSP is able to sort out the data signals based on the repairing pattern reflected by the configuration (settings) of SW1s.

(48) Because the spare readout channels implement exactly the same readout operation than the default one, the value representative of the analog DC reference voltage obtained at the output of the spare readout channel is a CDS value, which quantifies the row noise level for the current selected row. In other words, in the spare readout channels operated to sample the DC voltage reference, the SHr and SHs signals (FIG. 9) “sample” quite the same signal and the subtraction between the two samples corresponds to a row noise level. In other words: the subtraction between the two samples results in one actual sample of the row temporal noise.

(49) Then, the readout operation 100 (FIG. 4) performed in the readout circuitry for each new selected row Row.sub.i applies to read the pixel values in the selected row but also to read the signal value Sp.sub.k from each of the A spare readout channels operatively coupled to reference bus B.sub.DC. This comprises the sample and hold operation 100.1 with the successive sampling of a reference level and a signal level, and the analog to digital conversion 100.2 in each readout channel (FIG. 2) or by a fast ADC shared by the channels (FIG. 1). This readout operation 100 for the current selected row Row.sub.i outputs a flow of data comprising pixel data DATA_pix {S.sub.i,j}.sub.j=1, . . . N and spare data DATA_spare {Sp.sub.k}.sub.k=1, . . . A, which are all CDS values (meaning that the reference level and signal level were subtracted to one another).

(50) In step 200.1 (FIG. 4), an average of the Sp.sub.k digital values is computed, over the whole set of spare data DATA_spare {Sp.sub.k}.sub.k=1, . . . A, which gives a row noise value RN.sub.i for the current selected row Row.sub.i. This averaging enables to reduce the horizontal row noise variation (random) in a factor of square root of A.

(51) In step 200.2 this row noise value RN; is then subtracted from each of the pixel values S.sub.i,j of the pixel data flow DATA_pix {S.sub.i,j}.sub.j=1, . . . N for the current selected row Row.sub.i, which gives the low noise values d.sub.i,j as already explained supra.

(52) Then the process 100 and 200 repeat for each new row of the array, until all the P rows are read.

(53) In FIG. 3, the three illustrated spare readout channels are all available, which results in their spare signals Sp.sub.1, Sp.sub.2, Sp.sub.3 used to compute the averaged row-noise level, V.sub.RN.sub.i for the current selected row Row.sub.i. In FIG. 5, some spare readout channels are used for repair (selected in SW1s), so that their outputs are not used in the row suppression process: this is why the outputs from RoCsp.sub.1 and RoCsp2 are crossed out in the figure. Remains only in the illustration the spare signal Sp.sub.1 which is output by the spare channel RoCsp.sub.3. The indicia 1 is to mark that it is the first spare signal available for row noise suppression, with the conventions taken in this description.

(54) Note that in both FIGS. 3 and 5, all the process starting from the conversion in digital inside the readout channels is digital. In particular the processing steps 200.1 (evaluation of RN.sub.i) and 200.2 (row noise subtraction) can be done through integrated logic circuits or by a DSP (internal or external to the sensor). Also, when the ADC is a single one as in FIG. 1, the processing steps 200.1 and 200.2 takes place after the ADC, and then it can be done on-chip or off-chip by a DSP.

(55) Now regarding the DC analog reference voltage to be sampled by the A spare readout channels according to the invention, as already explained, the readout circuitry 2 comprises a bus line B.sub.DC, which extends in a row direction to cover the whole set of readout channels. This bus line B.sub.DC conveys an analogic DC reference voltage. In practice, the value of this analogic DC reference voltage is determined to correspond to a mid-range of the analog to digital converter(s) of the readout circuitry, which corresponds to the best conditions for efficient row noise suppression. In a practical example, this analogic DC reference can be set to the same voltage as the pixel common mode voltage, normally between 2.2V and 1.6V in 3.3V CIS technology. This analogic DC reference voltage needs not to be generated by a bandgap source, which is much expensive. Any voltage source preferably integrated into the optical sensor may be convenient.

(56) However, it is desirable to have the possibility to easily adapt the voltage level in each optical sensor. Also, it is desirable to obtain a quiet DC signal on the reference bus B.sub.DC before the sampling phase for each current selected row. Because otherwise the noise in the DC reference voltage can generate row temporal noise since it is sampled by the spare readout channel used for this purpose.

(57) FIG. 8 illustrates a preferred embodiment 400 to generate and apply a DC analogic reference voltage DC_ref to the reference bus which addresses these different aspects.

(58) It comprises a digital to analog converter, DAC, 401, which makes it easy to program a voltage reference value (digital code) V_ref.sub.DC in a parameter register of the optical sensor, and the desired analog DC reference voltage DC_ref is produced by the DAC. Then an operational amplifier 402 with high driving capability and operated as a follower (output looped back at its inverting input), is used to apply the DC reference DC_ref from the DAC (on its non-inverting input) to the capacitive bus reference line B.sub.DC.

(59) Preferably, a switch 403 is provided at the output of the follower amplifier 10 which is associated with buffers 404 distributed all along the length of the bus reference line B.sub.DC in order to uniformly load the bus reference line B.sub.DC. The buffers are then connected between a first bus line 405 which connects to the switch 403, and the reference bus B.sub.DC. By this implementation, the buffers 404 are analog to a big distributed buffer with very low noise.

(60) The operation of the switch 403 together with the buffers immunizes the reference bus B.sub.DC against the temporal noise coming from buffer 402 and DAC 401, since the analog signal is sampled and frozen at the input of the row distributed buffers. In practice, the buffers 404 can be a single transistor, or an operational amplifier, mounted as a follower. The output voltage is therefore equal to the input voltage.

(61) As illustrated on FIG. 9, the switch 403 is activated once during each row time by the pulse signal Set_DC, before the reading sequence 100 begins. With the pulse signal Set_DC, the reference bus B.sub.DC is set to the DC analog reference voltage DC_ref, and then the reference bus is isolated from the input stage (DAC, Amplifier and Switch): the analog DC voltage value is then frozen and quiet, for the whole following reading sequence for the current selected row, as illustrated on FIG. 9, with reference to a common true CDS readout sequence. Specifically, the switch 403 is activated with the pulse signal Set_DC, and the reference bus B.sub.DC is set to the DC analog reference voltage the time of the Set_DC pulse; then it is isolated from the input stage and the DC_ref is frozen. Only then the signal RS is activated in each pixel of the current selected row, to reset the sense node in these pixels, and a corresponding reference level of the sense node is sampled (SHr) in each readout channel; then the signal TX is activated in each pixel of the selected row, to transfer the charges integrated by the pixel to its sense node and a corresponding signal level is sampled (SHr) in the readout channel.

(62) In the spare readout channels operatively connected to the reference bus, the two pulse signals SHr and SHs apply as well, but each results in sampling the DC analog reference voltage on the reference bus B.sub.DC. This enables through CDS subtraction to obtain a signal (analog or digital) which corresponds to a row noise signal only, which is then subtracted from each of the pixel signals Si,j.

(63) FIG. 7 illustrates a second embodiment, in which the repairing pattern operates on a group basis, in a view to either simplify the command of the multiplexing elements through reducing the setting circuit (FIG. 6) and allows for several spare readout channels between each group of default readout channels, resulting in a better averaging process 200.2.

(64) In this embodiment, the spare groups Gm.sub.1, Gm.sub.2, Gm.sub.3 comprises m spare readout channels, where m is greater than 1. In the figure, m=4. It can be in principle any integer value greater than one, but as usual, it is preferably a power of 2 for decoding aspects. In practice, 4 is a possible value, but m could be also taken to be 8 or 16 for instance. The principle of the invention is not restricted to a specified value.

(65) Then the replacement principle to repair any defective readout channel, is now to shift in the left or the right direction on a group basis. That is, in each default group like Gm.sub.1, the default readout channels are further grouped in u subsets of m successive channels (u integer, equal to n/m). As illustrated, we have then in each default group, u subsets SS.sub.1 to SS.sub.u. The switching circuits SW1 are similarly grouped to form u groups 10.1, 10.2, . . . 10.u of m SW1 circuits in correspondence with the u subsets SS.sub.1, SS.sub.2, . . . , SS.sub.u.

(66) Then when a subset contains at least one defective channel, like SS.sub.u-1 in the Gn.sub.1, the m switching circuits SW1 of the corresponding group 10.u-1 are all set to apply a right shift replacement pattern to route the m corresponding column conductors (inputs), to the m readout channels of the next subset SS.sub.u (on a one to one basis). This scheme propagates in the shift direction up to the spare group Gm.sub.1 on the right side of Gn.sub.1. That is all the SW1 switches in the group 10.u are set to apply a right shift replacement pattern to route the m corresponding column conductors to the m readout channels of the spare group Gm.sub.1 next to the default group Gn.sub.1. In this embodiment, and as clear on FIG. 7, a default readout channel is then replaced with a next one m ranks further on its right side or its left side. As explained for the first embodiment the choice of the right shift replacement pattern or left shift replacement pattern in a default group is a matter of proximity of the defective channel with the spare groups framing the default group and also depends on whether the neighboring default groups on the left and the right have defective channels too.

(67) Then the configuration of the switching circuits SW1 is simplified, because the m switching circuits SW1 attached to a given subset are all configured identically, to select the default output (Sel-D), the right output (Sel-R) or the left output (Sel-L). With reference to FIG. 6, this means that a same command signal C.sub.10.1, is applied to the switch circuit 10.1 of m=4 multiplexing elements attached to the subset SS.sub.1 in Gn.sub.1. In the example the logic command C.sub.10.1 selects the default output RoC-D in the m multiplexing elements of circuit 10.1. The logic commands C1.sub.0.u-1 and C.sub.10.u instead each select the right output RoC-R in each of the m multiplexing elements.

(68) Then, the unused spare groups like Gm.sub.2 in FIG. 7 can be used for a row suppression noise operation according to the invention. For this row noise suppression, having m neighboring spare readout channels at disposal at each place of an unused spare group makes the averaging over the row length much more efficient.

(69) The readout circuitry implementing the repairing operation as described above is advantageously scalable and repeatable as clear on FIGS. 3, 5 and 7. This remains true when the row noise suppression operation according to the invention is also implemented. The scalability makes it easy to implement the readout circuit for any array size. The repeatability is compatible with stitching technologies which are commonly used to manufacture large surface of integrated circuits. This contributes further in reducing the manufacturing costs.

(70) Finally, the switch circuits SW1, SW2 (and eventually their complements SW1′, SW2′) are configured through shift register(s), in a setting process of the optical sensor, which defines a routing pattern that repairs the defects found at the manufacturing test process, and defines the spare channels for the row suppression operation. A parameter register of the optical sensor will also be set with the value A to initialize the average step 200.2. Finally, when the DC analog reference voltage is obtained through a DAC, the parameter register will also be set with a corresponding digital value V_ref.sub.DC to be applied in operation to the DAC (FIG. 8).

(71) The invention that has been described makes it possible to obtain an efficient optical sensor with enhanced image quality (good SNR, wide dynamic range) through scalable and programmable readout channels repairing process which enables to easily implement a row noise reduction function at low costs including low manufacturing cost, low surface area cost and low post-processing cost.