Driver circuit for switching edge modulation of a power switch

Abstract

A driver circuit for switching edge modulation of a power switch. The driver circuit includes a first driver circuit input including a downstream input node, and a power switch including an upstream first gate node. A charging path including a charging resistor is situated between the input node and the first gate node. A discharging path including a discharging resistor is situated between the input node and the first gate node. A gate path is situated between the input node and the first gate node. A power switch transistor, whose gate is connected to the first gate node, is provided. A gate path includes a gate resistor. The driver circuit is configured so that, during a switching process of the power switch, the gate path is temporarily short-circuited either via the charging path or the discharging path, to increase the slope of the switching behavior of the power switch.

Claims

1. A driver circuit for switching edge modulation of a power switch, comprising: a first driver circuit input including a downstream input node; a power switch including an upstream first gate node; a charging path situated between the input node and the first gate node, including a charging resistor; a discharging path situated between the input node and the first gate node, including a discharging resistor; a gate path situated between the input node and the first gate node, including a gate resistor; and a power switch transistor, a gate of the power switch transistor being connected to the first gate node; wherein the driver circuit being configured in such a way that, during a switching process of the power switch, the gate path is temporarily short-circuited either via the charging path or the discharging path, to increase a slope of a switching behavior of the power switch.

2. The driver circuit as recited in claim 1, wherein the driver circuit is configured in such a way that the charging path and the discharging path are blocked at a beginning and end of the switching process for overvoltage reduction.

3. The driver circuit as recited in claim 1, wherein the following components are situated in the discharging path between the input node and the first gate node, in the following order: a discharging path transistor, which is situated in parallel to a first discharging path diode situated in a conducting direction; the discharging resistor; and a second discharging path diode, which is situated in a non-conducting direction.

4. The driver circuit as recited in claim 1, wherein the following components are situated in the charging path between the input node and the first gate node, in the following order: a first charging path diode, which is situated in a conducting direction; the charging resistor; and a charging path transistor, which is situated in parallel to a second charging path diode situated in a non-conducting direction.

5. The driver circuit as recited in claim 1, further comprising: a second driver stage including a second driver circuit input, a second gate node to which the second driver stage is connected being situated between the first gate node and the gate of the power switch transistor.

6. The driver circuit as recited in claim 5, wherein the following components are situated in the second driver stage between the second driver circuit input and the second gate node, in the following order: a limiting resistor; and a limiting diode in a conducting direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments of the present invention are described in greater detail based on the figures and the following description.

(2) FIG. 1 shows a circuit diagram of a first specific embodiment of a driver circuit according to the present invention.

(3) FIG. 2 shows a circuit diagram of a second specific embodiment of a driver circuit according to the present invention.

(4) FIG. 3 shows a simplified chart of the drain current and the drain voltage of a power switch in the related art.

(5) FIG. 4 shows a simplified chart of the drain current and the drain voltage of a power switch including a driver circuit according to the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(6) FIG. 1 shows a circuit diagram of a first specific embodiment of a driver circuit 1 according to the present invention of a power switch 2. Driver circuit 1 includes a first driver circuit input 3 including a downstream input node 4. Driver circuit 1 furthermore includes a power switch transistor 5 including an upstream first gate node 6.

(7) A charging path 7, a discharging path 8, and a gate path 9 are situated between input node 4 and first gate node 6. A gate of power switch transistor 5 of power switch 2 is connected to first gate node 6. Driver circuit 1 is configured in such a way that, during a switching process of power switch 2, gate path 9 is temporarily short-circuited either via charging path 7 or discharging path 8, to increase the slope of the switching behavior of power switch 2. Charging path 7 and discharging path 8 are blocked at the beginning and end of a switching process for overvoltage reduction.

(8) Starting at input node 4, the following components are situated in charging path 7 in the direction toward first gate node 6: a first charging path diode 10, which is situated in the conducting direction; a charging resistor 11; and a charging path transistor 12, which is situated in parallel to a second charging path diode 13 situated in the non-conducting direction.

(9) Starting at input node 4, the following components are situated in discharging path 8 in the direction toward first gate node 6: a discharging path transistor 14, which is situated in parallel to a first discharging path diode 15 situated in the conducting direction; a discharging resistor 16; and a second discharging path diode 17, which is situated in the non-conducting direction.

(10) A gate resistor 18 is situated in gate path 8 between input node 4 and gate node 6.

(11) FIG. 2 shows a second specific embodiment of a driver circuit 20 according to the present invention. Corresponding features are denoted by the same reference numerals. In addition to the switching components shown in FIG. 1, driver circuit 20 includes a second driver stage 21.

(12) All components of driver circuit 20 between first driver circuit input 3 and first gate node 6 may be understood as the first driver stage. Reference is made in this regard to the description of FIG. 1.

(13) Second driver stage 21 includes a second driver circuit input 22, a second gate node 23 to which second driver stage 21 is connected being situated between first gate node 6 and the gate of power switch transistor 5. Starting from second driver circuit input 22 in the direction toward second gate node 23, the following components are situated in second driver stage 21, in this order: a limiting resistor 24; and a limiting diode 25 in the conducting direction.

(14) Driver circuits 1, 20 according to the present invention allow gate path 9, and, in particular, gate resistor 18, to be short-circuited at certain switching times. The slope of the switching edge of the power switch may thus be temporarily increased, and the losses may be decreased. By varying the effective gate series resistance with the aid of charging resistor 11 and discharging resistor 16, the peak current in power switch 2 may be limited by driver circuit 1, 20, despite the short circuit. For overvoltage reduction, charging path 7 and discharging path 8 may each be blocked in a timely manner during a switching process. In this way, it is possible to modulate the shape of the switching edges, and to avoid both overvoltages and limit losses.

(15) Driver circuit 20 shown in FIG. 2 allows an additional modulation of the upper switch-off edge transition as well as of the lower switch-on edge transition in that current may be impressed via second driver stage 21. Using this design, it is possible to achieve an additional modulation of the upper switch-off edge transition as well as of the lower switch-on edge transition in an uncomplicated manner.

(16) FIGS. 3 and 4 illustrate the main effect of the present invention. In a simplified chart, the drain current and the drain voltage of a power switch against time t are shown in each case over two switching processes.

(17) FIG. 3 shows drain current I.sub.DS and drain voltage V.sub.DS of a power switch in the related art. Switching edges 26 of drain voltage V.sub.DS are comparatively sharp and result in overvoltages when the duration of the switching process via the magnitude of the gate resistance is selected to be too short. In this way, the only choice that remains is, depending on the application, to select the gate resistance to be relatively large, and thereby tolerate larger switching losses.

(18) FIG. 4 shows drain current I.sub.DS and drain voltage V.sub.DS of a power switch including a driver circuit 1, 20 according to an example embodiment of the present invention. Here, switching edges 27 of drain voltage D.sub.VS are now flatter and no longer result in overvoltages, even when the duration of the switching process in the middle of the switching process via the magnitude of the effective gate series resistance of the gate of power switch 2 is selected to be relatively short. The effective gate series resistance is the variable effective resistance between first or second driver circuit input 3, 22 and the gate of power switch 2. The greater slope of the switching edge in the middle of the switching process and the shorter switching time result in lower switching losses at improved EMC emission. Despite an increased effective gate series resistance in the middle of the switching process, an enhanced performance may thus be achieved as a result of bridging at non-critical points in time.