LDO, MCU, fingerprint module and terminal device

Abstract

Provided are an LDO, an MCU, a fingerprint module and a terminal device. The LDO includes: a reference voltage generating circuit and a source follower connected to the reference voltage generating circuit. The reference voltage generating circuit is used to generate a reference voltage that changes with temperature to offset a voltage change caused by a voltage between a first terminal and a second terminal of the source follower changing with time, so that an output voltage of the second terminal of the source follower does not change with temperature. The LDO omits an operational amplifier EA and a resistor divider feedback network in the prior art, which not only has a simple circuit structure, but also can achieve ultra-low power consumption.

Claims

1. A low dropout regulator (LDO), comprising: a reference voltage generating circuit and a source follower, a first terminal of the reference voltage generating circuit being connected to a first terminal of the source follower, a second terminal of the reference voltage generating circuit being grounded, and a second terminal of the source follower being used to connect to a load circuit; wherein the reference voltage generating circuit is configured to generate a reference voltage that changes with temperature, to offset a voltage change caused by a voltage between the first terminal and the second terminal of the source follower changing with the temperature; the reference voltage generating circuit comprises: a first N-Metal-Oxide-Semiconductor (NMOS) transistor and an adjustable resistor, and a gate and a drain of the first NMOS transistor are connected to the first terminal of the source follower, and a source of the first NMOS transistor is grounded through the adjustable resistor; the source follower comprises: a second NMOS transistor, wherein a gate of the second NMOS transistor is connected to the drain of the first NMOS transistor, a source of the second NMOS transistor is used to connect to the load circuit, and a drain of the second NMOS transistor is connected to a power supply voltage, wherein the gate and the drain of the first NMOS transistor are further configured to receive a bias current Iptc having a-temperature coefficient, and the temperature coefficient is adjustable to offset the voltage change caused by the voltage between the first terminal and the second terminal of the source follower changing with the temperature; the first NMOS transistor and the second NMOS transistor are of a same type, and a channel length of the first NMOS transistor is the same as a channel length of the second NMOS transistor, and then a threshold voltage V.sub.thM1 of the first NMOS transistor is the same as a threshold voltage V.sub.thM2 of the second NMOS transistor.

2. The LDO according to claim 1, wherein the adjustable resistor is a low temperature drift resistor, and the gate and the drain of the first NMOS transistor are further configured to receive the bias current Iptc having the temperature coefficient, and the temperature coefficient is adjustable to compensate for a temperature coefficient of the adjustable resistor.

3. The LDO according to claim 2, wherein a temperature coefficient of the adjustable resistor is a zero temperature coefficient.

4. The LDO according to claim 1, wherein the source of the second NMOS transistor is grounded through a stabilizing capacitor, wherein the stabilizing capacitor is used to keep a voltage input to the load circuit unchanged.

5. A microcontroller unit (MCU), comprising: an LDO according to claim 1.

6. The MCU according to claim 5, wherein the reference voltage generating circuit comprises: a first N-metal-oxide-semiconductor (NMOS) transistor and an adjustable resistor, and a gate and a drain of the first NMOS transistor are connected to the first terminal of the source follower, and a source of the first NMOS transistor is grounded through the adjustable resistor.

7. The MCU according to claim 6, wherein the gate and the drain of the first NMOS transistor are further configured to receive a bias current Iptc having an adjustable temperature coefficient.

8. The MCU according to claim 6, wherein the source follower comprises: a second NMOS transistor, wherein a gate of the second NMOS transistor is connected to the drain of the first NMOS transistor, a source of the second NMOS transistor is used to connect to the load circuit, and a drain of the second NMOS transistor is connected to a power supply voltage.

9. The MCU according to claim 8, wherein the first NMOS transistor and the second NMOS transistor are of a same type, and a channel length of the first NMOS transistor is the same as a channel length of the second NMOS transistor.

10. A fingerprint module, comprising: an MCU according to claim 5.

11. A terminal device, comprising: a fingerprint module according to claim 10.

12. The LDO according to claim 1, wherein an output voltage V.sub.out of the source of the second NMOS transistor is determined by the following formula: $\begin{array}{c}{V}_{\mathrm{out}}=V_{\mathrm{ref}}-V_{\mathrm{gsM}2}\\ =I*R_0+V_{\mathrm{gsM}1}-V_{\mathrm{gsM}2}\\ =I*R_0+\left(V_{\mathrm{odM}1}+V_{\mathrm{thM}1}\right)-\left(V_{\mathrm{odM}2}+V_{\mathrm{thM}2}\right)\\ =I*R_0+V_{\mathrm{odM}1}+V_{\mathrm{odM}2}\\ =I*R_0+\Delta V_{\mathrm{od}}\end{array}$ wherein, V.sub.ref represents the reference voltage, V.sub.gsM1 represents a voltage between the gate and the source of the first NMOS transistor, V.sub.gsM2 represents a voltage between the gate and the source of the second NMOS transistor, I represents the bias current, R.sub.0 represents the adjustable resistor, V.sub.odM1 represents an overdrive voltage of the first NMOS transistor, V.sub.odM2 represents an overdrive voltage of the second NMOS transistor, and ΔV.sub.od represents an overdrive voltage difference between the first NMOS transistor and the second NMOS transistor.

13. The LDO according to claim 12, wherein the temperature coefficient of the bias current Iptc is adjustable to compensate for a temperature coefficient of the adjustable resistor and/or a temperature coefficient of ΔV.sub.od.

14. The LDO according to claim 12, wherein an adjustable range of the temperature coefficient of the bias current Iptc is −200 ppm/° C.˜+200 ppm/° C., and the adjustable range of the temperature coefficient of the bias current Iptc comprises an end point value.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) In order to more clearly illustrate technical solutions in embodiments of the present application or the prior art, drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced in the following. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative effort.

(2) FIG. 1 is a schematic structural diagram of an LDO commonly used in the prior art;

(3) FIG. 2 is a schematic structural diagram of an LDO provided by an embodiment of the present application;

(4) FIG. 3 is a schematic structural diagram of an LDO provided by another embodiment of the present application.

DESCRIPTION OF EMBODIMENTS

(5) In order to make the purpose, technical solutions, and advantages of embodiments of the present application more clearly, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort shall fall within the protection scope of the present application.

(6) The terms “first”, “second”, etc. (if any) in the description and claims and the above-mentioned drawings of the present application are used to distinguish similar objects, and need not be used to describe a specific order or sequence. It should be understood that the terms used in this way may be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented for example in a sequence other than those illustrated or described herein.

(7) In addition, the terms “include” and “have” and any variations of them are intended to cover a non-exclusive inclusion, for example, processes, methods, systems, products or devices that include a series of steps or units are not necessarily limited to those clearly listed steps or units, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

(8) First, an application background and some terms involved in embodiments of the present application are introduced.

(9) An LDO in the prior art includes an operational amplifier EA and a resistor divider feedback network, etc. The LDO in the prior art not only has a relatively complicated structure, but also has relatively large power consumption, and thus cannot be applied to application scenarios with a requirement of low power consumption.

(10) Aiming at the above problem, the embodiments of the present application provide an LDO, an MCU, a fingerprint module and a terminal device. The LDO includes: a reference voltage generating circuit and a source follower connected to the reference voltage generating circuit. The reference voltage generating circuit is configured to generate a reference voltage that changes with temperature to offset a voltage change caused by a voltage between a first terminal and a second terminal of the source follower changing with temperature, so that an output voltage of the second terminal of the source follower does not change with temperature. It can be seen that, compared with the LDO in the prior art, the LDO provided in the embodiments of the present application omits the operational amplifier EA and the resistor divider feedback network in the prior art, which not only has a simple circuit structure, but also can achieve ultra-low power consumption, and in the meantime, can realize the output voltage that does not change with temperature, and thus can be applied to application scenarios with a requirement of lower power consumption.

(11) The reference voltage generating circuit involved in the embodiments of the present application is configured to generate a reference voltage V.sub.ref that changes with temperature, which is used as an input voltage of a first terminal of the source follower.

(12) A second terminal of the source follower involved in the embodiments of the present application is used to connect to a load circuit, where a characteristic of the source follower includes: output voltage V.sub.out of the second terminal of the source follower=input voltage of the first terminal of the source follower (i.e. reference voltage V.sub.ref)—voltage between the first terminal and the second terminal of the source follower. In addition, a third terminal of the source follower can be connected to a power supply voltage.

(13) Optionally, the source follower in the embodiments of the present application may include but is not limited to: a second NMOS transistor, where a gate of the second NMOS transistor is used as the first terminal of the source follower to be connected to a first terminal of the reference voltage generating circuit, a source of the second NMOS transistor is used as a second terminal of the source follower to be connected to the load circuit, and a drain of the second NMOS transistor is used as the third terminal of the source follower to be connected to the power supply voltage.

(14) Correspondingly, a characteristic of the source follower includes: output voltage V.sub.out of the source of the second NMOS transistor=input voltage of the gate of the second NMOS transistor (i.e. reference voltage V.sub.ref)—voltage between the gate and the source of the second NMOS transistor.

(15) The reference voltage generating circuit involved in the embodiments of the present application may include but is not limited to: a first NMOS transistor and an adjustable resistor, where a gate and a drain of the first NMOS transistor are used as the first terminal of the reference voltage generating circuit to be connected to the first terminal of the source follower, a source of the first NMOS transistor is connected to a first terminal of the adjustable resistor, and a second terminal of the adjustable resistor is used as a second terminal of the reference voltage generating circuit to be grounded.

(16) Optionally, the gate and the drain of the first NMOS transistor may also be configured to receive a bias current having an adjustable temperature coefficient (Programmable Temperature Coefficient Current, Iptc).

(17) The bias current having an adjustable temperature coefficient Iptc (or bias current Iptc for short) involved in the embodiments of the present application means that a temperature coefficient of the bias current is adjustable. For example, an adjustable range of the temperature coefficient may be −200 ppm/° C.˜+200 ppm/° C., where the adjustable range of the temperature coefficient may include an end point value.

(18) Illustratively, the bias current Iptc may be generated by a bias circuit having an adjustable temperature coefficient; of course, it may also be generated by other circuits for generating a current having an adjustable temperature coefficient, which is not limited in the embodiments of the present application.

(19) The temperature coefficient involved in the embodiments of the present application refers to a rate at which a physical property of a material changes with temperature.

(20) Illustratively, the adjustable resistor in the embodiments of the present application may be a low temperature drift resistor (or called a low temperature coefficient resistor), which refers to a precision resistor whose resistance is less affected by temperature changes.

(21) Technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments may be combined with each other, and same or similar concepts or processes may not be repeated in some embodiments.

(22) FIG. 2 is a schematic structural diagram of an LDO provided by an embodiment of the present application. As shown in FIG. 2, the LDO provided by the embodiment of the present application may include: a reference voltage generating circuit 20 and a source follower 21; where a first terminal of the reference voltage generating circuit 20 is connected to a first terminal of the source follower 21, a second terminal of the reference voltage generating circuit 20 is grounded, and a second terminal (or called output terminal) of the source follower 21 is used to connect to a load circuit (not shown in the figure).

(23) A characteristic of the source follower includes: output voltage V.sub.out of the second terminal of the source follower 21=input voltage of the first terminal of the source follower (i.e. reference voltage V.sub.ref output by the first terminal of the reference voltage generating circuit 20)—voltage between the first terminal and the second terminal of the source follower.

(24) Considering that the voltage between the first terminal and the second terminal of the source follower 21 will change with temperature, the reference voltage generating circuit 20 in the embodiment of the present application is configured to generate the reference voltage V.sub.ref that also changes with temperature to offset a voltage change caused by the voltage between the first terminal and the second terminal of the source follower 21 changing with temperature, so that the output voltage of the second terminal of the source follower 21 does not change with temperature.

(25) For example, when the voltage between the first terminal and the second terminal of the source follower increases by ΔV with a change in temperature, the reference voltage V.sub.ref generated by the reference voltage generating circuit 20 also increases by ΔV, so that the output voltage V.sub.out of the second terminal of the source follower 21 does not change with temperature.

(26) For another example, when the voltage between the first terminal and the second terminal of the source follower decreases by ΔV with a change in temperature, the reference voltage V.sub.ref generated by the reference voltage generating circuit 20 also decreases by ΔV, so that the output voltage V.sub.out of the second terminal of the source follower 21 does not change with temperature.

(27) The LDO provided by the embodiments of the present application includes: the reference voltage generating circuit 20 and the source follower 21 connected to the reference voltage generating circuit 20, where the reference voltage generating circuit 20 is configured to generate the reference voltage V.sub.ref that changes with temperature to offset the voltage change caused by the voltage between the first terminal and the second terminal of the source follower changing with temperature, so that the output voltage of the second terminal of the source follower V.sub.out does not change with temperature. It can be seen that, compared with the LDO in the prior art, the LDO provided in the embodiments of the present application omits an operational amplifier EA and a resistance divider feedback network in the prior art, which not only has a simple circuit structure, but also can achieve ultra-low power consumption, and in the meantime, can realize the output voltage that does not change with temperature, and thus can be applied to application scenarios with a requirement of lower power consumption.

(28) FIG. 3 is a schematic structural diagram of an LDO provided by another embodiment of the present application. On the basis of foregoing embodiments, this embodiment of the present application describes implementation manners of the above-mentioned reference voltage generating circuit 20 and foregoing source follower 21.

(29) As shown in FIG. 3, the above-mentioned reference voltage generating circuit 20 may include: a first NMOS transistor M1 and an adjustable resistor R.sub.0.

(30) A gate g and a drain d of the first NMOS transistor M1 are used as a first terminal of the reference voltage generating circuit 20 to be connected to a first terminal of the source follower 21, and a source s of the first NMOS transistor M1 is connected to a first terminal of the adjustable resistor R.sub.0, and a second terminal of the adjustable resistor R.sub.0 is used as a second terminal of the reference voltage generating circuit 20 to be grounded. In addition, the gate g and the drain d of the first NMOS transistor M1 may also receive a supply current I.

(31) Illustratively, the adjustable resistor R.sub.0 in the embodiment of the present application may be a low temperature drift resistor (or called a low temperature coefficient resistor), which refers to a precision resistor whose resistance is less affected by temperature changes.

(32) Illustratively, the reference voltage V.sub.ref generated by the above-mentioned reference voltage generating circuit 20 may be determined by following formula (1):
V.sub.ref=I*R.sub.0+V.sub.gsM1  formula (1)
where V.sub.gsM1 represents a voltage between the gate g and the source s of the first NMOS transistor M1.

(33) It should be noted that the reference voltage V.sub.ref may also be determined by other equivalent or modified formulas of the above formula (1).

(34) The V.sub.gsM1 in the reference voltage generating circuit 20 provided by the embodiment of the present application changes with temperature, and can be used to offset a voltage change caused by the voltage between the first terminal and a second terminal of the source follower 21 changing with temperature, so that the output voltage V.sub.out of the second terminal of the source follower 21 does not change with temperature.

(35) It should be noted that in the embodiment of the present application, the reference voltage V.sub.ref output by the reference voltage generating circuit 20 may also be adjusted by adjusting resistance of the adjustable resistor R.sub.0 to meet requirements of different reference voltages V.sub.ref.

(36) Further, the above-mentioned supply current may be a bias current Iptc having an adjustable temperature coefficient, that is, the gate g and the drain d of the first NMOS transistor M1 may receive the bias current Iptc having an adjustable temperature coefficient, and correspondingly, it is also possible to adjust the temperature coefficient of the bias current Iptc to compensate for a temperature coefficient of the voltage between the first terminal and the second terminal of the source follower 21 (or in other words, to offset the voltage change caused by the voltage between the first terminal and the second terminal of the source follower 21 changing with temperature), so that the temperature coefficient of the output voltage V.sub.out of the second terminal of the source follower 21 is 0, that is, V.sub.out does not change with temperature. It should be understood that by adjusting the temperature coefficient of the bias current Iptc, the temperature coefficient of the adjustable resistor R.sub.0 and/or the temperature coefficient of V.sub.gsM1 can also be compensated for.

(37) As shown in FIG. 3, the source follower 21 may include: a second NMOS transistor M2, where a gate g of the second NMOS transistor M2 is used as the first terminal of the source follower 21 to be connected to the drain d of the first NMOS transistor M1 to obtain the reference voltage V.sub.ref generated by the reference voltage generating circuit 20, a source s of the second NMOS transistor M2 is used as the second terminal of the source follower 21 to be connected to a load circuit, and a drain d of the second NMOS transistor M2 is used as a third terminal of the source follower 21 to be connected to a power supply voltage VDD.

(38) Illustratively, a characteristic of the source follower 21 includes: output voltage V.sub.out of the source s of the second NMOS transistor M2=input voltage of the gate g of the second NMOS transistor M2 (i.e., reference voltage V.sub.ref)—voltage V.sub.gsM2 between the gate g and the source s of the second NMOS transistor M2.

(39) Combined with the above formula (1), the output voltage V.sub.out of the source s of the second NMOS transistor M2 may be determined by the following formula (2):
V.sub.out=V.sub.ref−V.sub.gsM2=I*R.sub.0+V.sub.gsM1−V.sub.gsM2  formula (2)

(40) It should be noted that the output voltage V.sub.out of the source s of the second NMOS transistor M2 may also be determined by other equivalent or modified formulas of the above formula (2).

(41) In the embodiment of the present application, V.sub.gsM1 and V.sub.gsM2 will change with temperature, and the change of V.sub.gsM1 with temperature can be used to offset the change of V.sub.gsM2 with temperature, so that the output voltage V.sub.out of the source s of the second NMOS transistor M2 does not change with temperature.

(42) It should be noted that if the supply current I in the above formula (2) is the bias current Iptc having an adjustable temperature coefficient, it is further possible to adjust the temperature coefficient of the bias current Iptc to compensate for the temperature coefficient of V.sub.gsM2 (or in other words, to offset the change of V.sub.gsM2 with temperature), so that the temperature coefficient of the output voltage V.sub.out of the source s of the second NMOS transistor M2 is 0, that is, V.sub.out does not change with temperature. It should be understood that by adjusting the temperature coefficient of the bias current Iptc, the temperature coefficient of the adjustable resistor R.sub.0 and/or the temperature coefficient of V.sub.gsM1 can also be compensated for.

(43) Optionally, in order that the change of V.sub.gsM1 with temperature can be used to completely offset the change of V.sub.gsM2 with temperature, the first NMOS transistor M1 and the second NMOS transistor M2 in the embodiment of the present application are a same type of NMOS transistor, and a channel length of the first NMOS transistor M1 is the same as that of the second NMOS transistor M2, and then a threshold voltage V.sub.thM1 of the first NMOS transistor M1 is the same as a threshold voltage V.sub.thM2 of the second NMOS transistor M2. Correspondingly, the above formula (2) may be transformed into the following formula (3):

(44) $\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{out}}=V_{\mathrm{ref}}-V_{\mathrm{gsM}2}=I*R_0+V_{\mathrm{gsM}1}-V_{\mathrm{gsM}2}\\ =I*R_0+\left(V_{\mathrm{odM}1}+V_{\mathrm{thM}1}\right)-\left(V_{\mathrm{odM}2}+V_{\mathrm{thM}2}\right)\\ =I*R_0+V_{\mathrm{odM}1}-V_{\mathrm{odM}2}=I*R_0+\Delta V_{\mathrm{od}}\end{array}& \mathrm{formula}\left(3\right)\end{array}$

(45) where, V.sub.odM1 represents an overdrive voltage of the first NMOS transistor M1, V.sub.odM2 represents an overdrive voltage of the second NMOS transistor M2, and ΔV.sub.od represents an overdrive voltage difference between the first NMOS transistor M1 and the second NMOS transistor M2.

(46) It should be noted that the output voltage V.sub.out of the source s of the second NMOS transistor M2 may also be determined by other equivalent or modified formulas of the above formula (3).

(47) In the embodiment of the present application, since the first NMOS transistor M1 and the second NMOS transistor M2 are the same type of NMOS transistor, and the channel length of the first NMOS transistor M1 is the same as the channel length of the second NMOS transistor M2, the threshold voltage V.sub.thM1 of the first NMOS transistor M1 is the same as the threshold voltage V.sub.thM2 of the second NMOS transistor M2, the change of V.sub.gsM1 with temperature can thus be used to completely offset the change of V.sub.gsM2 with temperature. In order to make the output voltage V.sub.out not change with temperature, the above-mentioned adjustable resistor R.sub.0 may be a low temperature drift resistor, and the above-mentioned supply current I may be a bias current Iptc that does not change with temperature.

(48) Illustratively, for application scenarios where an output current of the LDO does not change much (such as a sleep mode or a standby mode of an MCU), ΔV.sub.od is close to 0. It can be seen that the output voltage V.sub.out is only related to the bias current Iptc having an adjustable temperature coefficient, and the adjustable resistor R.sub.0, where the adjustable resistor R.sub.0 may be a low temperature drift resistor, or a zero temperature coefficient resistor composed of a combination of resistors with different temperature coefficients. The above-mentioned supply current may be a bias current Iptc that does not change with temperature, so that the output voltage V.sub.out does not change with temperature.

(49) As another example, for application scenarios where ΔV.sub.od is not close to 0, the temperature coefficient of the bias current Iptc may be adjusted to compensate for the temperature coefficient of the adjustable resistor R.sub.0 and/or the temperature coefficient of ΔV.sub.od (if the temperature coefficient of ΔV.sub.od is not zero), so that the output voltage V.sub.out does not change with temperature.

(50) In summary, the LDO provided by the embodiments of the present application includes: the reference voltage generating circuit 20 and the source follower 21 connected to the reference voltage generating circuit 20; the reference voltage generating circuit 20 includes the first NMOS transistor M1 and the adjustable resistor R.sub.0, and the source follower 21 includes the second NMOS transistor M1, where the reference voltage generating circuit 20 is configured to generate the reference voltage V.sub.ref that changes with temperature, to offset the voltage change caused by the voltage between the gate g and the source s of the second NMOS transistor M2 changing with temperature, so that the output voltage V.sub.out does not change with temperature. It can be seen that, compared with the LDO in the prior art, the LDO provided in the embodiments of the present application omits the operational amplifier EA and the resistor divider feedback network in the prior art, which not only has a simple circuit structure, but also can achieve ultra-low power consumption, and in the meantime, can realize the output voltage that does not change with temperature, and thus can be applied to application scenarios with a requirement of lower power consumption.

(51) Further, on the basis of the foregoing embodiment, as shown in FIG. 3, the source s of the second NMOS transistor M2 in the embodiment of the present application may also be grounded through a stabilizing capacitor 22, where the stabilizing capacitor 22 is used to keep the voltage input to the load circuit basically unchanged as much as possible, so as to ensure the normal operation of the load circuit as much as possible.

(52) It should be noted that the aforementioned stabilizing capacitor 22 may also be replaced by other devices or circuits with a voltage stabilizing function.

(53) An embodiment of the present application also provides an MCU, including: an LDO as provided in any of the foregoing embodiments of the present application, and the implementation principle and technical effect thereof are similar, and will not be repeated here.

(54) An embodiment of the present application also provides a fingerprint module, including: an MCU as provided in the foregoing embodiment of the application.

(55) An embodiment of the application also provides a terminal device, including: a fingerprint module as provided in the foregoing embodiment of the application.

(56) Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: it is still possible to modify the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the range of technical solutions of the embodiments of the present disclosure.