Multi-level converter with voltage divider for pre-charging flying capacitor

Abstract

A multi-level converter includes a flying capacitor and a resistive voltage divider. The multi-level converter is configured to convert an input voltage into an output voltage. The resistive voltage divider is configured to charge a flying capacitor in the multi-level converter during an initial charging mode of operation. In some implementations, the multi-level converter includes a plurality of flying capacitors and a plurality of resistive voltage dividers including a resistive voltage divider for each flying capacitor in the plurality of flying capacitors.

Claims

1. A multi-level converter configured to convert an input voltage into an output voltage, comprising: two upper level transistors connected in electrical series with a node therebetween; two lower level transistors, wherein the two upper level transistors and the two lower level transistors are connected together in electrical series between the input voltage and ground, a flying capacitor connected to the node between the two upper level transistors; and a resistive voltage divider configured to passively charge the flying capacitor, without opening or closing any switches, during an initial charging mode of operation, wherein the resistive voltage divider consists of a first resistor and a second resistor connected in electrical series between the input voltage and ground, with a node therebetween, the node between the first resistor and the second resistor being connected to the flying capacitor and to the node between the two upper level transistors, wherein the second resistor is a voltage-sensing resistor for providing voltage information to a controller.

2. The multi-level converter of claim 1, wherein the multi-level converter comprises a plurality of flying capacitors, and wherein the multi-level converter further comprises a resistive voltage divider connected to each flying capacitor.

3. The multi-level converter of claim 1, wherein a ratio of a resistance of the first resistor to a resistance of the second resistor is chosen based on a desired voltage on a positive terminal of the flying capacitor.

4. The multi-level converter of claim 1, wherein a resistance of the first resistor and a resistance of the second resistor are chosen to control a charging speed of the flying capacitor.

5. The multi-level converter of claim 1, wherein the multi-level converter comprises the second resistor to sense a voltage on a positive terminal of the flying capacitor for controlling the multi-level converter.

6. The multi-level converter of claim 1, further comprising a controller, wherein during the initial charging mode of operation, the controller is configured to enable a charging path from the resistive voltage divider through the flying capacitor to a ground node.

7. The multi-level converter of claim 6, wherein the controller is further configured to cause the multi-level converter to transition from the initial charging mode of operation to a normal mode of operation when the voltage across the flying capacitor satisfies a voltage criterion.

8. An N-level flying capacitor multi-level converter, comprising: N-1 upper transistors connected in series, with a node between each of the upper transistors; N-1 lower transistors connected in series, wherein the N-1 lower transistors are connected in series with the N-1 upper transistors between an input voltage and ground; N-2 flying capacitors, each flying capacitor connected to one of the nodes between each of the upper transistors; and N-2 resistive voltage dividers, each voltage divider being configured to passively charge one of the flying capacitors without opening or closing any switches, each resistive voltage divider consisting of a first resistor and a second resistor connected in electrical series between the input voltage and ground with a node therebetween, the node between the first resistor and the second resistor being connected to the one of the flying capacitors that the voltage divider is configured to charge and to the one node between the upper transistors connected to the one of the flying capacitors, wherein the second resistor is a voltage-sensing resistor for providing voltage information to a controller.

9. The flying capacitor multi-level converter of claim 8, wherein the resistive voltage dividers are configured to charge the flying capacitors during an initial charging phase of operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

(2) FIG. 1 illustrates a schematic of a three-level converter with a flying capacitor according to an exemplary embodiment of the present invention.

(3) FIG. 2 illustrates a schematic of a four-level converter with two flying capacitors according to an exemplary embodiment of the present invention.

(4) FIG. 3 illustrates a schematic of a hybrid converter with a flying capacitor according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings.

(6) FIG. 1 illustrates a schematic of a three-level converter 100 with a flying capacitor C.sub.FLY according to an exemplary embodiment of the present invention. The three-level converter 100 includes two upper transistors Q1, Q2 and two lower transistors Q3, Q4, capacitors C.sub.FLY, C.sub.BUS, and C.sub.OUT, resistors R.sub.C1 and R.sub.C2, and inductor L.sub.OUT. Transistors Q1-Q4 comprise n-type field effect transistors (FETs). In some implementations, transistors Q1-Q4 are gallium nitride (GaN) FETs, metal oxide semiconductor (MOS) FETs, bipolar junction transistors (BJTs), or any appropriate type or combination of transistors.

(7) The upper level transistors Q1, Q2 are connected in series with each other, and are connected in series with the lower level transistors, Q3, Q4, which are also connected in series with each other. The drain terminal of Q1 is connected to an input node 110 configured to receive V.sub.IN, and the source terminal of Q4 is connected to ground 105. Capacitor C.sub.BUS is connected to the input node 110 and to ground 105. Capacitor C.sub.FLY is connected between Q1 and Q2 at node 120 and between Q3 and Q4 at node 130.

(8) Resistor R.sub.C1 is connected to the input node 110 and to capacitor C.sub.FLY and between transistors Q1 and Q2 at node 120. Resistor R.sub.C2 is connected to capacitor C.sub.FLY and between transistors Q1 and Q2 at node 120 and to ground 105. Resistor R.sub.C1 works in tandem with resistor R.sub.C2 to act as a resistive voltage divider. The ratio of resistor R.sub.C1 to resistor R.sub.C2 is used to determine a voltage at the node 120 and the positive terminal of capacitor C.sub.FLY. Inductor L.sub.OUT is connected between transistors Q2 and Q3 at node 140 and to output node 150 configured to provide V.sub.OUT. Capacitor C.sub.OUT is connected to output node 150 and to ground 105.

(9) In response to being powered on, three-level converter 100 operates in an initial charging mode of operation in which the capacitor C.sub.FLY is charged. During the initial charging mode, transistor Q4 is turned on to provide a charging path for capacitor C.sub.FLY from the input node 110, through the resistive voltage divider of R.sub.C1 and R.sub.C2, to capacitor C.sub.FLY before reaching ground 105 through transistor Q4. A ratio of the resistance of R.sub.C1 to the resistance of R.sub.C2 is chosen based on the expected input voltage V.sub.IN such that the capacitor C.sub.FLY is charged until a voltage at the node 120 and the positive terminal of capacitor C.sub.FLY is approximately half the input voltage V.sub.IN or slightly greater than half the input voltage V.sub.IN to accommodate leakage from transistors Q1-Q4. The value of the resistances is also chosen to control a charging current to capacitor C.sub.FLY and the length of time needed to charge it. Once the capacitor C.sub.FLY is charged, three-level converter 100 transitions to a normal operating mode, and the voltage on the positive terminal of capacitor C.sub.FLY is maintained at approximately half the input voltage V.sub.IN.

(10) In contrast to conventional multi-level converters which use an independent power system to charge capacitor C.sub.FLY before steady state operation, the three-level converter 100 uses passive components in the resistive voltage divider which occupy a much smaller area than an independent charging system. In addition, resistors R.sub.C1 and R.sub.C2 do not add complexity to control of three-level converter 100. In some embodiments, the resistor R.sub.C2 is already included in a conventional three-level converter as a voltage-sensing resistor to provide voltage information to a controller, such that the only added component included to make a resistive voltage divider for charging the flying capacitor is the resistor R.sub.C1.

(11) The resistive voltage divider used to charge the flying capacitor can be extended from a three-level converter to other multi-level converters and to multi-level inverters. An N-level flying capacitor multi-level converter includes (N-1) upper transistors and (N-1) lower transistors, (N-2) flying capacitors, and (N-2) resistive voltage dividers. FIG. 2 illustrates a schematic of a four-level converter 200 with two flying capacitors C.sub.F1 and C.sub.F2 according to an exemplary embodiment of the present invention.

(12) The four-level converter 200 of FIG. 2 is similar to three-level converter 100 shown in FIG. 1, but includes additional transistors Q5 and Q6, an additional flying capacitor C.sub.F2, and an additional resistive voltage divider including resistors R.sub.C21 and R.sub.C22. Similar to three-level converter 100, four-level converter 200 uses passive components R.sub.C11 and R.sub.C12 in the first resistive voltage divider and R.sub.C21 and R.sub.C22 in the second resistive voltage divider to charge the flying capacitors C.sub.F1 and C.sub.F2 and reduce power consumption compared to an independent power system.

(13) Transistors Q1-Q6 comprise n-type FETs and are connected together in series. The drain terminal of Q1 is connected to an input node 210 configured to receive V.sub.IN, and the source terminal of Q6 is connected to ground 205. Capacitor C.sub.BUS is connected to the input node 210 and to ground 205. Capacitor C.sub.F1 is connected between Q1 and Q2 at node 220 and between Q5 and Q6 at node 230. Resistor R.sub.C11 is connected to the input node 210 and to capacitor C.sub.F1 and between transistors Q1 and Q2 at node 220. Resistor R.sub.C12 is connected to capacitor C.sub.F1 and between transistors Q1 and Q2 at node 220 and to ground 205. Resistor R.sub.C11 works in tandem with resistor R.sub.C12 as a resistive voltage divider to charge the first flying capacitor C.sub.F1.

(14) Capacitor C.sub.F2 is connected between Q2 and Q3 at node 240 and between Q4 and Q5 at node 250. Resistor R.sub.C21 is connected to node 220 and to capacitor C.sub.F2 at node 240. Resistor R.sub.C22 is connected to capacitor C.sub.F2 at node 240 and to ground 205. Resistor R.sub.C21 works in tandem with resistor R.sub.C22 as a resistive voltage divider to charge the second flying capacitor C.sub.F2. Inductor L.sub.OUT is connected between transistors Q3 and Q4 at node 260 and to output node 270 configured to provide V.sub.OUT. Capacitor C.sub.OUT is connected to output node 270 and to ground 205.

(15) In response to being powered on, four-level converter 200 operates in an initial charging mode of operation in which the flying capacitors C.sub.F1 and C.sub.F2 are charged. During the initial charging mode, transistor Q6 is turned on to provide a charging path for capacitor C.sub.F1 from the input node 210, through the resistive voltage divider of R.sub.C11 and R.sub.C12, to capacitor C.sub.F1 before reaching ground 205. Capacitor C.sub.F1 is charged until a voltage at the node 220 and the positive terminal of capacitor C.sub.F1 is approximately two-thirds of the input voltage V.sub.IN or slightly greater than two-thirds of the input voltage V.sub.IN to accommodate leakage from transistors Q1-Q6.

(16) Once the capacitor C.sub.F1 is charged or while the capacitor C.sub.F1 is charging, transistor Q5 is turned on to provide a charging path for capacitor C.sub.F2 from the input node 210, through the first resistive voltage divider of R.sub.C11 and R.sub.C12, through the second resistive voltage divider of R.sub.C21 and R.sub.C22, to capacitor C.sub.F2 before reaching ground 205 through transistors Q5 and Q6. Capacitor C.sub.F2 is charged until a voltage at the node 240 and the positive terminal of capacitor C.sub.F2 is approximately one third of the voltage at node 220 or slightly greater than one third of the voltage at node 220 to accommodate leakage from transistors Q1-Q6. Once the capacitor C.sub.F2 is charged, four-level converter 200 transitions to a normal operating mode, and the voltage on the positive terminal of capacitor C.sub.F1 and the voltage on the positive terminal of capacitor C.sub.F2 are maintained at their respective values.

(17) In addition to multilevel converters with three or more levels, the resistive voltage divider used to charge the flying capacitor can be extended to hybrid converters combining multilevel converters with other types of converters such as buck-boost converters, bootstrap converters, and the like. FIG. 3 illustrates a schematic of a hybrid converter 300 combining a converter and a synchronous buck according to an exemplary embodiment of the present invention. Hybrid converter 300 is similar to three-level converter 100 shown in FIG. 1, but also includes a capacitor C.sub.MID connected between transistors Q2 and Q3 at node 340. In addition, the inductor L.sub.OUT is connected between transistors Q3 and Q4 at node 330, rather than at node 340. Hybrid converter 300 includes the resistive voltage divider of resistors R.sub.C1 and R.sub.C2 which charges capacitor C.sub.FLY through transistor Q4 during an initial charging phase.

(18) The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.