PHASED ARRAY ANTENNA WITH HIGH IMPEDANCE SURFACE
20230155288 · 2023-05-18
Assignee
Inventors
Cpc classification
H01Q15/008
ELECTRICITY
H01Q9/0421
ELECTRICITY
H01Q1/52
ELECTRICITY
International classification
H01Q1/52
ELECTRICITY
Abstract
A phased array antenna with a high impedance surface according to an embodiment of the present disclosure is a phased array antenna with a high impedance surface including a plurality of unit elements, and each of the plurality of unit elements includes a substrate, a partial ground plane formed at least partially on the substrate, a planar inverted-L radiator disposed on the partial ground plane, and a via wall integrated in parallel on both edges of the partial ground plane, and a one-dimensional electromagnetic bandgap (EBG) structure is embedded in an edge of the planar radiator side of the partial ground plane.
Claims
1. A phased array antenna with a high impedance surface, the phased array antenna comprising: a plurality of unit elements, wherein each of the plurality of unit elements includes a substrate; a partial ground plane formed at least partially on the substrate; a planar inverted-L radiator disposed on the partial ground plane; and a via wall integrated in parallel on both edges of the partial ground plane, a one-dimensional electromagnetic bandgap (EBG) structure is embedded in an edge of the planar radiator side of the partial ground plane.
2. The phased array antenna according to claim 1, wherein the plurality of unit elements are linearly arrayed within 0.39λ.sub.0, λ.sub.0 being a wavelength in a free space.
3. The phased array antenna according to claim 1, wherein the one-dimensional EBG structure includes a plurality of periodic unit cells, and the plurality of periodic unit cells are arrayed in a line at the edge of the planar radiator side of the partial ground plane.
4. The phased array antenna according to claim 3, wherein the plurality of periodic unit cells configured in the one-dimensional EBG structure includes a meander strip line utilizing a single-layer FR-4 PCB process.
5. The phased array antenna according to claim 3, wherein the one-dimensional EBG structure is configured to operate as a high impedance surface having a slower wave behavior to be able to exhibit quadratic reflection phase than an antenna without a one-dimensional EBG structure.
6. The phased array antenna according to claim 3, wherein the phased array antenna is configured to operate as a high impedance surface having a slower wave behavior than an antenna without a one-dimensional EBG structure in a horizontal direction of an edge of the one-dimensional EBG structure so that surface wave control is able to be performed.
7. The phased array antenna according to claim 1, wherein the phased array antenna has a structure in which a one-dimensional EBG structure and an inverted-L antenna unit element are integrated, and a mutual coupling path between the antenna unit elements caused by a surface current flowing through a common ground plane is suppressed due to high impedance surface characteristics of the via wall, compared to a linearly arrayed phased array antenna without the via wall.
8. The phased array antenna according to claim 1, further comprising: a feeding network configured of a coplanar waveguide with ground (CPWG) transmission line including a plurality of island-shaped via walls serving as a high impedance surface for reducing leakage power.
9. The phased array antenna according to claim 1, further comprising: a power distribution circuit, the power distribution circuit including a tapered T-shaped power divider to facilitate impedance matching and low loss feeding despite a constraint of electrode manufacturing resolution of an FR-4 PCB process with a preset minimum line width.
10. The phased array antenna according to claim 1, comprising: a high impedance surface instead of a Balun, the Balun being an auxiliary circuit, such that wide-angle beam steering is allowed in a broadband and spherical coverage characteristics are provided despite utilization of a single-layer FR-4 PCB process.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DESCRIPTION OF EXEMPLARY EMBODIMENTS
[0038] Various changes may be made to the present disclosure, there are several embodiments of the present disclosure, and specific embodiments will be illustrated in the drawings and described in detail.
[0039] However, this is not intended to limit the present disclosure to the specific embodiments, and it should be understood that all changes, equivalents, or substitutions included in the spirit and scope of the present disclosure are included.
[0040] Although the terms first, second, etc. may be used to describe various components, these components should not be limited by these terms. The terms are only used to distinguish one component from other components. For example, a first component could be termed a second component and, similarly, a second component could be termed a first component without departing from the scope of the present disclosure.
[0041] It will be understood that when a component is referred to as being “connected” or “coupled” to another component, the component may be directly connected or coupled to the other component or intervening elements may be present. On the other hand, when a component is referred to as being “directly connected” or “directly coupled” to another component, there are no intervening elements present.
[0042] The terminology used herein is only used for the purpose of describing specific embodiments and is not intended to limit the present disclosure. Singular forms “a,” “an” and “the” include plural forms unless the context clearly indicates otherwise. It will be further understood that terms “include”, “have”, etc. used herein designate the presence of features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude a likelihood of the presence or addition of one or more other features, integers, steps, operations, components, parts, and/or combinations thereof.
[0043] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meaning in the context of the relevant art and will not be construed as having idealized or overly formal meanings unless expressly defined herein.
[0044] Hereinafter, preferred embodiments of the present disclosure will be described clearly and in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the present disclosure.
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[0047] Referring to
[0048] Referring to
[0049] With the phased array antenna with a high impedance surface according to the embodiment of the present disclosure, it is possible to suppress an coupling path caused by a surface current by integrating the via wall 200 in parallel on both the edges of the partial ground plane 20 of the antenna unit element, and to provide an effect of self-decoupling between the antenna elements. When a plurality of antenna unit elements are vertically connected, the via wall 200 may be integrated in parallel at upper and lower edges of the partial ground plane 20. Further, the one-dimensional EBG structure 100 may include a plurality of periodic unit cells 100-1 and 100-2, and the plurality of periodic unit cells 100-1 and 100-2 may be arrayed in a line at the edge of the partial ground plane 20 on the planar radiator 30 side. The unit cells 100-1 and 100-2 can be configured of a meander strip line according to an FR-4 (a dielectric constant of 4.4 and a loss factor of 0.032@28 GHz) PCB design rule (a minimum line width of 100 μm) that is a manufacturing resolution limit, and five the unit cells may be arrayed in a row in the partial ground plane 20.
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[0051] As illustrated in
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[0053] An electrical length of the unit element (ILA with an EBG and a via wall) of the phased array antenna with a high impedance surface according to the embodiment of the present disclosure is further compressed as compared to other antennas, as represented by a lowest input impedance matching frequency within the same distance between the elements. It is expected that an ILA topology with the one-dimensional EBG structure 100 and the via wall 200 will achieve a high gain in a longitudinal direction in a horizontal polarization without separate performance degradation despite a further electrically compressed configuration.
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[0055] Referring to
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[0057] The phased array antenna according to the embodiment of the present disclosure may further include a feeding network having a low leakage power loss and excellent impedance matching characteristics to individually supply in-phase power. As illustrated in
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[0059] With a phased array antenna in which an ILA and a high impedance structure (a one-dimensional EBG and a via wall) are integrated, a wide impedance bandwidth of 18 GHz was obtained between 22 GHz and 40 GHz. An average value of the mutual coupling of this antenna was suppressed to less than −12 dB. It was experimentally verified that, when in-phase feeding was made using a commercial RFIC beamforming chipset, a end-fire radiation gain of 6 dBi and a lower cross-polarization than a main polarization of 12 dB in an end-fire direction at 28 GHz were realized with the antenna. Further, with an antenna including an ILA topology with a high impedance surface structure (a one-dimensional EBG and a via wall), a 120° (±60°) beam coverage was secured within a 3 dB scan loss.
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[0061] It can be seen that a surface current of the line for each virtual position of the common ground plane illustrated in
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[0063] It is necessary to verify that an antenna manufactured on an FR-4 substrate with high dielectric loss characteristics can wirelessly transmit a signal without nonlinear distortion in a large signal, by comparing an error vector magnitude (EVM) performance with a millimeter wave 5G standard specification. A result of measuring an OTA system performance of a phased array antenna manufactured using a commercial beamforming RFIC chipset for various scan angles was analyzed. For measurement of
[0064] A large-capacity linear phased array antenna with 8 or more elements with an increased antenna directivity and a reduced side lobe level was further studied in order to satisfy a link budget in a millimeter wave 5G terminal. However, since there is no commercial RFIC chipset capable of simultaneously controlling an 8-element array antenna, a 1×8 T-shaped power divider including a predetermined phase delay line was designed. In this case, in the antenna element, an ILA topology including a high impedance surface (a one-dimensional EBG and a via wall) structure verified above was utilized.
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[0066] In order to realize a low loss feeding network within an inter-element spacing, ground planes including a via wall structure are partially overlapped between portions of the power divider, compression patterning was performed, and the structure was designed as illustrated in
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[0068] It was confirmed that a 1×8 power divider designed in a tapered T-shaped junction structure had good impedance matching of −10 dB or less in a Ka band. Further, it can be seen that a simulated internal insertion loss of the designed 1x8 T-shaped power divider was 3 dB to 4.5 dB at less than 36 GHz, and a main cause of this loss is a high dielectric loss of the FR-4 substrate rather than impedance mismatching.
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[0070] A manufactured sample having a symmetrical structure including a 1×8 T-shaped power divider as illustrated in
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[0073] Radiation patterns were measured and compared in a horizontal plane of an array antenna manufactured to investigate a beam scanning performance of a proposed phased array characterized by a directional fan beam. With the manufactured array antenna, a beam scan range of 110° (±55°) or more was obtained within a 3 dB scan loss in a frequency range of 26 GHz to 36 GHz. As illustrated in
[0074] In a beam steering scenario, a millimeter wave terminal antenna should exhibit a quasi-isotropic spherical coverage. In order to implement a stable spherical coverage, a maximum realized gain should be high and a slope of coverage efficiency should change relatively steeply. In order to obtain the coverage efficiency, a total scan pattern (hereinafter referred to as a TSP) was first simulated and analyzed. In particular, since the present disclosure focuses on a design and verification method for a single-layer FR-4 PCB packaging process-based millimeter wave antenna that can be applied to a terminal despite a manufacturing resolution of a 100 μm line width and a large dielectric loss material, the TSP and coverage efficiency analysis are important. In an antenna additionally designed for continuous beam scanning results, a feeding network including a predetermined phase delay line for ±15°, ±30°, and ±45° beam steering was utilized.
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[0076] As illustrated in
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[0078] As illustrated in
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[0080] A small array antenna manufactured using an ILA topology including a high impedance surface (a one-dimensional EBG and a via wall) structure in a single-layer FR-4 PCB-based antenna element exhibited a wide impedance bandwidth and a wide-angle scanning function. Further, a CPWG transmission line with a dense via wall structure in an island shape minimized power leakage to the outside of a feeding network despite a relative loss in a material of the FR-4 substrate and supplied optimal power to an array antenna. Realized gains of the manufactured 4- and 8-element phased array antennas were 6 dBi and 8.1 dBi, respectively, as an insertion loss of the feeding network was kept below 0.23 dB/mm. With a design method for the antenna according to the embodiment of the present disclosure, it is possible to provide a spherical coverage in a broadband at a much lower production cost compared to the state-of-the-art antenna presented in the table when the design method is applied to a terminal in future.
[0081] Although the present disclosure has been described above with reference to the drawings and embodiments, the scope of protection of the present disclosure is not intended to be limited by the drawings or embodiments, and it will be understood by those skilled in the art that various modifications and changes of the present disclosure can be made without departing from the spirit and scope of the present disclosure defined in the claims.