Auxiliary Power Supply Apparatus and Method for Isolated Power Converters

Abstract

An apparatus includes a controller configured to generate a PWM signal for controlling a power switch of a forward converter, a bias switch and a bias capacitor connected in series and coupled to a bias winding of the forward converter, and a comparator having a first input connected to the bias capacitor, a second input connected to a predetermined reference and an output configured to generate a signal for controlling the bias switch to allow a magnetizing current from the bias winding to charge the bias capacitor when a voltage across the bias capacitor is less than the predetermined reference.

Claims

1-20. (canceled)

21. An apparatus comprising: a controller configured to generate a PWM signal for controlling a power switch of a forward converter; a bias switch and a bias capacitor connected in series and coupled to a bias winding of the forward converter; and a comparator having a first input connected to the bias capacitor, a second input connected to a predetermined reference and an output configured to generate a signal for controlling the bias switch to allow a magnetizing current from the bias winding to charge the bias capacitor when a voltage across the bias capacitor is less than the predetermined reference.

22. The apparatus of claim 21, further comprising: a diode connected in series with the bias switch, wherein: an anode of the diode is connected to the bias winding; and a cathode of the diode is connected to the bias switch.

23. The apparatus of claim 22, wherein: the bias switch is an n-type transistor, and wherein: a source of the bias switch is connected to the diode; and a drain of the bias switch is connected to the bias capacitor.

24. The apparatus of claim 21, further comprising: a first logic gate and a first buffer, wherein: a first input of the first logic gate is connected to the output of the comparator; a second input of the first logic gate is configured to receive the PWM signal for controlling the power switch through a first inverter; an input of the first buffer is connected to an output of the first logic gate; and an output of the first buffer is connected to a gate of the bias switch.

25. The apparatus of claim 24, wherein: the first logic gate is an AND gate; and the first buffer is a level shifter.

26. The apparatus of claim 21, further comprising: a second logic gate and a second buffer, wherein: a first input of the second logic gate is configured to receive the PWM signal for controlling the power switch; a second input of the second logic gate is connected to the output of the comparator through a second inverter; an input of the second buffer is connected to an output of the second logic gate; and an output of the second buffer is connected to a gate of the power switch.

27. The apparatus of claim 26, wherein: the second logic gate is an AND gate; and the second buffer is a gate driver.

28. The apparatus of claim 21, wherein: the forward converter comprises a primary winding, the power switch and a sense resistor connected in series between an input power source and ground; and a reset circuit connected between the input power source and a common node of the primary winding and the power switch.

29. The apparatus of claim 28, wherein: the reset circuit is a RCD reset device comprising a reset diode, a reset capacitor and a reset resistor, and wherein: the reset capacitor and the reset resistor are connected in parallel between the input power source and the reset diode; an anode of the reset diode is connected to the common node of the primary winding and the power switch; and a cathode of the reset diode is connected to the reset capacitor and the reset resistor.

30. The apparatus of claim 28, further comprising: a secondary winding magnetically coupled to the primary winding; a synchronous rectifier coupled to the secondary winding; and an L-C filter coupled to the synchronous rectifier.

31. A method comprising: detecting a voltage across a bias capacitor of a forward converter; comparing, by a comparator, the voltage across the bias capacitor with a predetermined threshold; turning on a bias switch connected in series with the bias capacitor so as to make a magnetizing current charge the bias capacitor when the voltage across the bias capacitor is less than the predetermined threshold; and turning off the bias switch after the voltage across the bias capacitor is greater than another predetermined threshold.

32. The method of claim 31, further comprising: generating a PWM signal for controlling a power switch of the forward converter; and turning on the bias switch immediately after the power switch has been turned off.

33. The method of claim 32, further comprising: after turning off the bias switch, configuring a resetting circuit to reset the forward converter.

34. The method of claim 31, wherein: the forward converter comprises a transformer having a bias winding, a primary winding and a secondary winding and a power switch connected in series with the primary winding.

35. The method of claim 34, wherein: the bias switch and the bias capacitor are connected in series and coupled to the bias winding of the forward converter.

36. The method of claim 35, further comprising: a comparator having a first input connected to the bias capacitor, a second input connected to the predetermined reference and an output configured to generate a signal for controlling the bias switch to allow the magnetizing current to charge the bias capacitor when the voltage across the bias capacitor is less than the predetermined reference.

37. A system comprising: an inductor and a power switch connected in series; a first bias switch and a first bias capacitor connected in series and coupled to a common node of the inductor and the power switch; a first comparator having a first input connected to the first bias capacitor, a second input connected to a first predetermined reference and an output configured to generate a signal for controlling the first bias switch to allow a magnetizing current from the inductor to charge the first bias capacitor when a voltage across the first bias capacitor is less than the first predetermined reference; a second bias switch and a second bias capacitor connected in series and coupled to a common node of the inductor and the power switch; and a second comparator having a first input connected to the second bias capacitor, a second input connected to a second predetermined reference and an output configured to generate a signal for controlling the second bias switch to allow the magnetizing current from the inductor to charge the second bias capacitor when a voltage across the second bias capacitor is less than the second predetermined reference.

38. The system of claim 37, further comprising: a first level shifter connected between the output of the first comparator and a gate of the first bias switch; and a second level shifter connected between the output of the second comparator and a gate of the second bias switch.

39. The system of claim 37, further comprising: a first diode connected between the first bias switch, and the common node of the inductor and the power switch; and a second diode connected between the second bias switch, and the common node of the inductor and the power switch.

40. The system of claim 39, wherein: an anode of the firs diode and an anode of the second diode are connected to the common node of the inductor and the power switch; a cathode of the first diode is connected to the first bias switch; and a cathode of the second diode is connected to the second bias switch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0014] FIG. 1 illustrates a block diagram of a switching power converter in accordance with various embodiments of the present disclosure;

[0015] FIG. 2 illustrates a schematic diagram of a flyback converter in accordance with various embodiments of the present disclosure;

[0016] FIG. 3 illustrates a schematic diagram of a first implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure;

[0017] FIG. 4 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 3 in accordance with various embodiments of the present disclosure;

[0018] FIG. 5 illustrates a schematic diagram of a second implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure;

[0019] FIG. 6 illustrates a schematic diagram of a third implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure;

[0020] FIG. 7 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 5 in accordance with various embodiments of the present disclosure;

[0021] FIG. 8 illustrates a schematic diagram of a fourth implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure;

[0022] FIG. 9 illustrates a schematic diagram of a fifth implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure;

[0023] FIG. 10 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 9 in accordance with various embodiments of the present disclosure;

[0024] FIG. 11 illustrates a schematic diagram of a first implementation of a secondary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure;

[0025] FIG. 12 illustrates a schematic diagram of a second implementation of a secondary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure;

[0026] FIG. 13 illustrates a schematic diagram of an implementation of a primary side bias power supply of a forward converter in accordance with various embodiments of the present disclosure;

[0027] FIG. 14 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 13 in accordance with various embodiments of the present disclosure;

[0028] FIG. 15 illustrates a schematic diagram of a first implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure;

[0029] FIG. 16 illustrates a schematic diagram of a second implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure;

[0030] FIG. 17 illustrates a schematic diagram of a third implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure;

[0031] FIG. 18 illustrates a schematic diagram of a third implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure;

[0032] FIG. 19 illustrates a schematic diagram of an implementation of multiple bias power supplies of a switching converter in accordance with various embodiments of the present disclosure;

[0033] FIG. 20 illustrates a flow chart of controlling the bias power supply in FIG. 3 in accordance with various embodiments of the present disclosure;

[0034] FIG. 21 illustrates a flow chart of controlling the bias power supply in FIG. 7 in accordance with various embodiments of the present disclosure;

[0035] FIG. 22 illustrates a schematic diagram of a first implementation of the snubber in accordance with various embodiments of the present disclosure;

[0036] FIG. 23 illustrates a schematic diagram of a second implementation of the snubber in accordance with various embodiments of the present disclosure;

[0037] FIG. 24 illustrates a schematic diagram of a third implementation of the snubber in accordance with various embodiments of the present disclosure;

[0038] FIG. 25 illustrates another embodiment timing diagram of controlling the bias power supply shown in FIG. 3 in accordance with various embodiments of the present disclosure; and

[0039] FIG. 26 illustrates another embodiment timing diagram of controlling the bias power supply shown in FIG. 5 in accordance with various embodiments of the present disclosure.

[0040] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0041] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

[0042] The present disclosure will be described with respect to preferred embodiments in a specific context, namely an auxiliary power supply employed in a switching power converter. The disclosure may also be applied, however, to a variety of isolated power converters including half bridge converters, full bridge converters, flyback converters, forward converters, push-pull converters, inductor-inductor-capacitor (LLC) resonant converter and the like. Furthermore, the disclosure may also be applied to a variety of non-isolated power converters such as four switch buck boost converters and the like. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

[0043] FIG. 1 illustrates a block diagram of a switching power converter in accordance with various embodiments of the present disclosure. The switching power converter 100 comprises an input filter 101, a primary side network 102, a transformer 104, a rectifier 106 and an output filter 107. In addition, a primary side controller 112 is placed at the primary side of the switching power converter 100. A secondary side controller 114 is placed at the secondary side of the switching power converter 100.

[0044] It should be noted that as indicated by a dashed line A-A′, the left side of the dashed line including the input dc source VIN, the input filter 101 and the primary side network 102 is commonly referred to as the primary side of the switching power converter 100. On the other hand, the right side of the dashed line A-A′ including the rectifier 106 and the output filter 107 is commonly referred to as the secondary side of the switching power converter 100. Furthermore, as shown in FIG. 1, the transformer 104 is placed between the primary side and the secondary side. In fact, the transformer 104 provides electrical isolation between the primary side and the secondary side of the switching power converter 100.

[0045] The primary side network 102 is coupled to the input dc source VIN through the input filter 101. Depending on different power converter topologies, the primary side network 102 may comprise different combinations of switches as well as passive components. For example, the primary side network 102 may comprise four switching elements connected in a bridge configuration when the switching power converter 100 is a full bridge power converter. On the other hand, when the switching power converter 100 is an LLC resonant converter, the primary side network 102 may comprise a high side switching element and a low side switching element connected in series, and a resonant tank formed by an inductor and a capacitor connected in series.

[0046] Furthermore, when the switching power converter 100 is a forward converter (e.g., an active clamp forward converter), the primary side network 102 may comprise a primary switch and an active clamp reset device formed by an auxiliary switch and a clamp capacitor. Moreover, the switching power converter 100 may be a flyback converter. The primary side network 102 may comprise a primary switch and a reset device formed by a clamp capacitor, a resistor and a diode.

[0047] The switching elements of the primary side network 102 may be formed by any suitable devices such as metal oxide semiconductor field effect transistor (MOSFET) devices, bipolar junction transistor (BJT) devices, super junction transistor (SJT) devices, insulated gate bipolar transistor (IGBT) devices and the like.

[0048] It should be noted that one of ordinary of skill in the art would realize that the switching power converter 100 as well as its corresponding primary side network 102 may be implemented in many different ways. It should further be noted that the power converter topologies discussed herein are provided for illustrative purposes only, and are provided only as examples of various embodiments.

[0049] The input filter 101 may comprise an inductor coupled between the input dc source VIN and the primary side network 102. The input filter 101 may further comprise a plurality of input capacitors. The inductor provides high impedance when switching noise tries to flow out of the primary side network 102. At the same time, the input capacitors shunt the input of the switching power converter 100 and provide a low impedance channel for the switching noise generated from the primary side network 102. As a result, the switching noise of the switching power converter 100 may be prevented from passing through the input filter 101. The structure and operation of the input filter of an isolated dc/dc converter are well known in the art, and hence are not discussed in further detail.

[0050] The transformer 104 provides electrical isolation between the primary side and the secondary side of the switching power converter 100. In accordance with some embodiments, the transformer 104 may be formed of two transformer windings, namely a primary transformer winding and a secondary transformer winding. Alternatively, the transformer 104 may have a center tapped secondary so as to have three transformer windings including a primary transformer winding, a first secondary transformer winding and a second secondary transformer winding. Moreover, the transformer may comprise a plurality of bias windings.

[0051] It should be noted that the transformers illustrated herein and throughout the description are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the transformer 104 may further comprise a variety of gate drive auxiliary windings and the like.

[0052] The rectifier 106 converts an alternating polarity waveform received from the output of the transformer 104 to a single polarity waveform. The rectifier 106 may be formed of a pair of switching elements such as NMOS transistors. Alternatively, the rectifier 106 may be formed of a single switching element. Furthermore, the rectifier 106 may be formed by other types of controllable devices such as metal oxide semiconductor field effect transistor (MOSFET) devices, bipolar junction transistor (BJT) devices, super junction transistor (SJT) devices, insulated gate bipolar transistor (IGBT) devices and the like. The detailed operation and structure of the rectifier 106 are well known in the art, and hence are not discussed herein.

[0053] The output filter 107 is employed to attenuate the switching ripple of the switching power converter 100. According to the operation principles of switching power converters, the output filter 107 may be an L-C filter formed by an inductor and a plurality of capacitors. One person skilled in the art will recognize that some switching power converter topologies such as forward converters and full bridge converters may require an L-C filter. On the other hand, some switching power converter topologies such as flyback converters and LLC resonant converters may include an output filter formed by a capacitor or a plurality of capacitors connected in parallel. One person skilled in the art will further recognize that different output filter configurations apply to different power converter topologies as appropriate. The configuration variations of the output filter 107 are within various embodiments of the present disclosure.

[0054] FIG. 1 further comprises the primary side controller 112 and the secondary side controller 114. The primary side controller 112 may generate gate drive signals for the primary side network 102. The secondary side controller 114 may generate gate drive signals for the secondary side switching network 106. Both the primary side controller 112 and the secondary side controller 114 may comprise an auxiliary power supply. The auxiliary power supply is employed to provide bias power for the controllers. Throughout the description, the auxiliary power supply is alternatively referred to as a bias power supply.

[0055] In accordance with an embodiment, the primary side controller 112 may employ a peak current mode control mechanism to generate the gate drive signals based upon the comparison between a detected output voltage and a sensed current signal. Alternatively, the primary side controller 112 may employ a voltage mode control mechanism to generate the gate drive signals based upon the detected output voltage. However, as one having ordinary skill in the art will recognize, the control mechanisms described above are merely exemplary methods and are not meant to limit the current embodiments. Other control mechanisms, such as average current mode control scheme may alternatively be used. Any suitable control mechanisms may be used, and all such control mechanisms are fully intended to be included within the scope of the embodiments discussed herein.

[0056] FIG. 2 illustrates a schematic diagram of a flyback converter in accordance with various embodiments of the present disclosure. An input voltage source VIN is coupled to a primary switch SM through the primary winding of the transformer 104. For simplicity, throughout the description, the transformer 104 is alternatively referred to as transformer T1 and the primary switch S.sub.M is alternatively referred to as a main switch.

[0057] The primary switch S.sub.M is connected between the primary winding N.sub.P and a current sense resistor R.sub.CS. The current sense resistor R.sub.CS is further connected to ground as shown in FIG. 2. A reset device is connected in parallel with the primary winding N.sub.P of the transformer 104. The reset device is employed to reset the magnetizing current of the flyback converter 200.

[0058] As shown in FIG. 2, the reset device is formed by a diode D.sub.RCD, a resistor R.sub.RCD and a clamp capacitor C.sub.RCD. As shown in FIG. 2, the resistor RRCD and the clamp capacitor C.sub.RCD are connected in parallel. The diode D.sub.RCD is connected between a common node of the resistor R.sub.RCD and the clamp capacitor C.sub.RCD, and a common node of the primary switch S.sub.M and the primary winding N.sub.P. Throughout the description, the reset device shown in FIG. 2 is alternatively referred to as a RCD reset device.

[0059] In accordance with some embodiments, the primary switch S.sub.M is an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) device. The clamp capacitor C.sub.RCD is a 0.1 uF ceramic capacitor. The resistance value of the resistor R.sub.RCD is in a range from about 1 Kohms to about 10 Kohms.

[0060] The primary side controller 112 may receive a plurality of signals such as a feedback signal VFB through an isolation device (not shown) placed between the primary side and the secondary side, a current sense signal CS detected from the current sense resistor R.sub.CS, and an input voltage signal as shown in FIG. 2. Based upon the received signals, the primary side controller 112 generates a gate drive signal G.sub.PRI for driving the primary switch S.sub.M. According to the operating principles of flyback converters, the amount of time D.Math.T that the primary switch S.sub.M conducts current during a switching period T is determined by a duty cycle D. The duty cycle D may have a value from 0 to 1.

[0061] In accordance with some embodiments, the secondary rectifier 106 is formed by a synchronous switch S.sub.SR. The synchronous switch S.sub.SR may be an n-type MOSFET device. It should be noted that the synchronous rectifier may be formed by other switching elements such as BJT devices, SJT devices, IGBT devices and the like. It should further be noted that while FIG. 2 illustrates a single switching element for the synchronous switch S.sub.SR, one of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the synchronous switch S.sub.SR may comprise a plurality of MOSFET devices connected in parallel. Furthermore, the synchronous switch S.sub.SR may be replaced by a diode.

[0062] As shown in FIG. 2, the secondary side controller 114 may receive a plurality of signals such as the output voltage signal and the signal representing the voltage across the secondary winding N.sub.S. Based upon the received signals, the secondary side controller 114 generates a gate drive signal G.sub.SR for driving the synchronous switch S.sub.SR.

[0063] According to the operation principles of flyback converters, when the input voltage source VIN is applied to the primary side winding N.sub.p of the transformer T1 through the turn-on of the primary switch S.sub.M, the polarity of the secondary side winding N.sub.s of the transformer T1 is so configured that the synchronous switch SSR is turned off and the load (not shown) connected to the flyback converter is supplied by the energy stored in the output capacitor C.sub.0. On the other hand, when the primary side switch S.sub.M is turned off and the synchronous switch S.sub.SR is turned on, the energy stored in the transformer is transferred to the load through the turned-on synchronous switch S.sub.SR. The detailed operation of the secondary side of the flyback converter is well known in the art, and hence is not discussed in further detail herein.

[0064] FIG. 3 illustrates a schematic diagram of a first implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure. The flyback converter 300 shown in FIG. 3 is similar to the flyback converter 200 shown in FIG. 2. In FIG. 3, like reference numerals refer to like elements. As such, descriptions on the like elements are not repeated. Furthermore, the primary side controller 112 may comprise various function units. For simplicity, only relevant portions (e.g., the control circuit of the bias power supply) are illustrated in FIG. 3.

[0065] As shown in FIG. 3, the primary bias power supply comprises a bias power converter portion and a control circuit portion. The bias power converter portion includes a bias winding N.sub.b, a diode D.sub.VDDP, a switch S.sub.VDDP and a capacitor C.sub.VDDP. Throughout the description, the switch S.sub.VDDP is alternatively referred to as a bias switch and the capacitor C.sub.VDDP is alternatively referred to as a bias capacitor. The bias winding N.sub.b is magnetically coupled to the transformer T1. The structure and operating principle of the bias winding are well known, and hence are not discussed herein.

[0066] As shown in FIG. 3, the diode D.sub.VDDP and the switch S.sub.VDDP are connected in series between the bias winding N.sub.b and the capacitor C.sub.VDDP. The diode D.sub.VDDP functions as a blocking diode. Throughout the description, the diode D.sub.VDDP is alternatively referred to as a blocking diode. In some embodiments, when the voltage across the bias winding N.sub.b is lower than the voltage across the capacitor C.sub.VDDP, the diode D.sub.VDDP prevents the capacitor C.sub.VDDP from being discharged.

[0067] The switch S.sub.VDDP is employed to control the charge of the capacitor C.sub.VDDP. In particular, the capacitor C.sub.VDDP is charged only when it is necessary. For example, when the bias voltage VDDP is lower than a first predetermined threshold, the switch S.sub.VDDP is turned on and the capacitor C.sub.VDDP is charged by the bias winding N.sub.b through the diode D.sub.VDDP and the turned-on switch S.sub.VDDP. Once the bias voltage VDDP reaches a second predetermined threshold, the switch S.sub.VDDP is turned off accordingly. In some embodiments, the second predetermined threshold is greater than the first predetermined threshold.

[0068] The control circuit portion includes a comparator U1, a logic gate U2 and a level shifter U3. The non-inverting input of the comparator U1 is connected to a predetermined reference Vref. The inverting input of the comparator U1 is configured to receive the bias voltage VDDP.

[0069] The logic gate U2 is an AND gate. A first input of the logic gate U2 is connected to the output of the comparator U1. A second input of the logic gate U2 is configured to receive the primary switch's gate drive signal through an inverter. The circle placed at the second input of the logic gate U2 indicates the signal applied to the second input of the logic gate U2 is a signal inverted from G.sub.PRI. In other words, the signal applied to the second input of the logic gate U2 and the primary switch's gate drive signal G.sub.PRI are two complementary signals.

[0070] In operation, when the primary switch S.sub.M is turned on, the signal applied to the second input of the logic gate U2 is a logic low signal. Such a logic low signal overrides the signal from the comparator U1, leaving the output of the logic gate U2 at a logic level of 0. As a result, the bias switch S.sub.VDDP is turned off. According to the logic circuit configuration shown in FIG. 3, the switch S.sub.VDDP can be turned on after the primary switch S.sub.M is turned off and the bias voltage VDDP is lower than the predetermined reference Vref.

[0071] It should be noted that the comparator U1 is a hysteretic comparator. The predetermined reference Vref includes a low threshold and a high threshold. When the bias voltage drops below the low threshold, the bias switch S.sub.VDDP is turned on and the magnetizing current from the bias winding N.sub.b charges the bias capacitor C.sub.VDDP. The bias switch S.sub.VDDP remains on until the bias voltage VDDP reaches the high threshold. The detailed operation principle of the hysteretic comparator will be described below with respect to FIG. 4.

[0072] It should further be noted that while FIG. 3 illustrates the voltage of the bias power supply is regulated through a hysteresis control mechanism, other suitable control mechanisms may be employed to regulate the bias voltage. For example, a constant off time control mechanism, a constant on time control mechanism and/or a pulse-width modulation (PWM) control mechanism may be alternatively employed to regulate the bias voltage VDDP.

[0073] As shown in FIG. 3, the source of the bias switch S.sub.VDDP is not connected to ground. In fact, the source of the bias switch S.sub.VDDP is connected to the capacitor C.sub.VDDP. In order to drive the bias switch S.sub.VDDP, the gate drive signal has to be level-shifted from the level of ground to the level of VDDP. The level shifter U3 is employed to fulfill this function. The structure and operating principle of the level shifter are well known, and hence are not discussed herein.

[0074] One advantageous feature of having the bias power supply shown in FIG. 3 is the bias power supply can maintain the bias voltage through a hysteresis control method. As a result, the bias power supply does not require a linear regulator for regulating the bias voltage VDDP. The bias power supply without having a linear regulator can reduce unnecessary power losses, thereby achieving better efficiency.

[0075] FIG. 4 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 3 in accordance with various embodiments of the present disclosure. The horizontal axis of FIG. 4 represents intervals of time. There are four vertical axes. The first vertical axis Y1 represents the magnetizing current flowing through the primary side of the transformer T1. The second vertical axis Y2 represents the gate drive signal of the primary side switch. The third vertical axis Y3 represents the bias voltage VDDP. The fourth vertical axis Y4 represents the gate drive signal of the bias switch.

[0076] At time t1, the primary side switch S.sub.M is turned on. As a result of turning on the primary side switch S.sub.M, the magnetizing current ramps up from time t1 until time 2 when the primary side switch S.sub.M is turned off. From time t1 to time t2, the bias voltage VDDP drops as shown in FIG. 4. According to the control logic described above with respect to FIG. 3, the bias switch S.sub.VDDP of the bias power supply cannot be turned on until the primary side switch S.sub.M is off. As such, the gate drive signal G.sub.VDDP of the bias switch S.sub.VDDP is low from time t1 to time t2.

[0077] The comparator U1 shown in FIG. 3 has a hysteresis band. In other words, the reference of the comparator U1 includes an upper threshold VREFH and a lower threshold VREFL. In operation, when the bias voltage VDDP drops below the lower threshold VREFL, the output of the comparator U1 transitions from a logic low state to a logic high state. The output of the comparator U1 maintains the logic high state until the bias voltage VDDP reaches the upper threshold VREFH. After the bias voltage reaches the upper threshold VREFH, the output of the comparator U1 transitions from a logic high state to a logic low state.

[0078] At time t2, the bias voltage drops below the lower threshold VREFL and the primary side switch S.sub.M is turned off, the bias switch S.sub.VDDP is turned on as indicated by the gate drive signal G.sub.VDDP. In response to the turned-on bias switch S.sub.VDDP, the magnetizing current from the bias winding N.sub.b starts to charge the bias capacitor C.sub.VDDP and the bias voltage VDDP increases in a linear manner as shown in FIG. 4.

[0079] At time t3, the bias voltage reaches the upper threshold VREFH, the output of the comparator U1 transitions from a logic high state to a logic low state. In response to this logic state change, the bias switch S.sub.VDDP is turned off at time t3 as indicated by the gate drive signal G.sub.VDDP. During the time interval from t2 to t3, the magnetizing current is partially reset by the bias voltage VDDP. The magnetizing current is of a slope of −VDDP/L.sub.M, where L.sub.M is the magnetizing inductance of the transformer T1.

[0080] During the time interval from t3 to t4, the magnetizing current is reset by the RCD reset device. The magnetizing current i.sub.LM decreases in a linear manner as shown in FIG. 4. From t3 to t4, the magnetizing current is of a slope of −V.sub.C/L.sub.M, where V.sub.C is the voltage across the capacitor C.sub.RCD. At t4, the magnetizing current is reset to zero. At time t5, a new switching cycle starts and the magnetizing current i.sub.LM starts to increase after the primary switch S.sub.M has been turned on.

[0081] In order to have the magnetizing current timing sequence (from t2 to t4) shown in FIG. 4, the bias voltage VDDP should be less than or equal to the lower end of the output voltage of the flyback converter 300. In operation, when the primary switch S.sub.M is turned on, the magnetizing current ramps up and the energy is stored in the transformer T1 in the time interval from t1 to t2. After the primary switch S.sub.M has been turned off, the magnetizing current is diverted to the lower voltage potential first. Since the bias voltage VDDP is less than or equal to the lower end of the output voltage of the flyback converter 300, the magnetizing current charges the bias capacitor first in the time interval from t2 to t3, and then the magnetizing current charges the output capacitor of the flyback converter 300 during the time interval from t3 to t4.

[0082] FIG. 4 illustrates the magnetizing current i.sub.LM includes a ramp up phase (e.g., the time interval from t1 to t2) and a ramp down phase (e.g., the time interval from t2 to t4). The charge of the bias capacitor C.sub.VDDP occurs during the ramp down phase as shown in FIG. 4. It should be noted, in some embodiments, the charge of the bias capacitor C.sub.VDDP may occur during the ramp up phase of the magnetizing current i.sub.LM. An example of charging the bias capacitor C.sub.VDDP during the ramp up phase of the magnetizing current i.sub.LM will be described below with respect to FIG. 7.

[0083] FIG. 5 illustrates a schematic diagram of a second implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure. The flyback converter 400 shown in FIG. 4 is similar to the flyback converter 300 shown in FIG. 3. In FIG. 4, like reference numerals refer to like elements. As such, descriptions on the like elements are not repeated.

[0084] As shown in FIG. 5, the primary bias power supply comprises a bias power converter portion and a control circuit portion. The bias power converter portion includes a diode D.sub.VDDP, a switch S.sub.VDDP and a capacitor C.sub.VDDP. As shown in FIG. 5, the diode D.sub.VDDP and the switch S.sub.VDDP are connected in series between the primary winding NP and the capacitor C.sub.VDDP. The diode D.sub.VDDP functions as a blocking diode. For example, when the primary switch S.sub.M is turned on, the diode D.sub.VDDP helps to prevent the capacitor C.sub.VDDP from being discharged through the turned-on primary switch S.sub.M.

[0085] The switch S.sub.VDDP is employed to control the charge of the capacitor C.sub.VDDP. In particular, the capacitor C.sub.VDDP is charged only when it is necessary. For example, when the bias voltage VDDP is lower than a predetermined reference Vref, the switch S.sub.VDDP is turned on and the capacitor C.sub.VDDP is charged by the magnetizing current through the diode D.sub.VDDP and the turned-on switch S.sub.VDDP. Once the bias voltage VDDP is above the predetermined reference Vref, the switch S.sub.VDDP is turned off accordingly.

[0086] The control circuit portion includes a comparator U1, a first logic gate U2 and a level shifter U3 and a second logic gate U4. In some embodiments, the comparator U1 is a hysteretic comparator. Both the first logic gate U2 and the second logic gate U4 are AND gates. The non-inverting input of the comparator U1 is connected to the predetermined reference Vref. The inverting input of the comparator U1 is configured to receive the bias voltage VDDP.

[0087] A first input of the first logic gate U2 is connected to the output of the comparator U1. A second input of the first logic gate U2 is configured to receive a PWM signal generated by the primary side controller 112.

[0088] A first input of the second logic gate U4 is connected to the output of the comparator U1 through an inverter. The circle placed at the first input of the second logic gate U4 indicates the signal applied to the first input of the second logic gate U4 is a signal inverted from the signal generated by the comparator U1. A second input of the second logic gate U4 is configured to receive the PWM signal generated by the primary side controller 112.

[0089] In operation, the PWM signal generated by the primary side controller 112 is applied to both the primary switch S.sub.M and the bias switch S.sub.VDDP. If the bias voltage VDDP is lower than a predetermined reference Vref, the comparator U1 generates a logic high state. After passing through an inverter (the circle attached to the second logic gate U4), the signal applied to the first input of the second logic gate U4 is a logic low signal. Such a logic low signal overrides the PWM signal applied to the second logic gate U4, leaving the output of the second logic gate U4 at a logic low state. As a result, despite that the PWM signal is applied to both switches, the control circuit turns on the bias switch S.sub.VDDP before turning on the primary switch S.sub.M when charging the bias capacitor C.sub.VDDP is necessary. The primary switch S.sub.M remains off until the bias switch S.sub.VDDP has been turned off. The detailed timing diagram of controlling the bias power supply shown in FIG. 5 will be discussed below with respect to FIG. 7.

[0090] One advantageous feature of having the bias power supply shown in FIG. 5 is the bias power supply can be charged by the primary winding N.sub.p of the flyback converter 400. As a result, the bias power supply does not require a bias winding for charging the bias capacitor C.sub.VDDP. The bias power supply without having a dedicated bias winding can simplify the design of the transformer T1, thereby improving the reliability and cost of the flyback converter 400.

[0091] FIG. 6 illustrates a schematic diagram of a third implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure. The flyback converter 500 is similar to the flyback converter 400 shown in FIG. 5 except that a diode D.sub.S is connected between the common node of the drain of the bias switch S.sub.VDDP and the diode D.sub.VDDP, and the reset capacitor C.sub.RCD. The diode D.sub.VDDP functions as a snubber to reduce the voltage stress on the bias switch S.sub.VDDP.

[0092] The snubber shown in FIG. 6 can help to reduce the ringing across the bias switch S.sub.VDDP. It should be noted that the snubber shown in FIG. 6 is applicable to all other bias power supplies in the present disclosure.

[0093] FIG. 7 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 5 in accordance with various embodiments of the present disclosure. The horizontal axis of FIG. 7 represents intervals of time. There are four vertical axes. The first vertical axis Y1 represents the magnetizing current flowing through the primary side of the transformer T1. The second vertical axis Y2 represents the gate drive signal of the primary side switch S.sub.M. The third vertical axis Y3 represents the bias voltage VDDP. The fourth vertical axis Y4 represents the gate drive signal of the bias switch of the bias power supply.

[0094] At time t1, after the bias voltage reaches the lower threshold VREFL, the output of the comparator U1 transitions from a logic low state to a logic high state. At the same time, the PWM signal is applied to both the primary switch S.sub.M and the bias switch S.sub.VDDP. Both the PWM signal and the output of the comparator U1 have a logic high state. As a result, the first logic gate U2 generates a logic high signal, which is used to turn on the bias switch S.sub.VDDP through the level shifter U3. As shown in FIG. 7, from t1 to t2, the bias switch gate drive signal G.sub.VDDP is of a logic high state.

[0095] In response to the turned-on bias switch S.sub.VDDP, the magnetizing current of the transformer T1 charges the bias capacitor C.sub.VDDP in a linear manner from t1 to t2. During the time interval from t1 to t2, the magnetizing current is of a slope of (VIN−VDDP)/L.sub.M, where L.sub.M is the magnetizing inductance of the transformer T1. During the time interval from t1 to t2, the primary switch S.sub.M remains off as shown in FIG. 7.

[0096] At time t2, after the bias voltage VDDP reaches VREFH, the output of the comparator U1 transitions from a logic high state to a logic low state. In response to this logic state change, the bias switch S.sub.VDDP is turned off and the primary side switch S.sub.M is turned on. As a result of turning on the primary side switch S.sub.M, the magnetizing current ramps up from t2 to t3 until the primary side switch S.sub.M is turned off. During the time interval from t2 to t3, the magnetizing current is of a slope of VIN/L.sub.M. During the time interval from t3 to t5, the timing diagram of FIG. 7 is similar to that shown in FIG. 4, and hence is not discussed in detail to avoid unnecessary repetition.

[0097] It should be noted FIG. 7 shows a timing diagram of controlling the bias power supply of a power converter having a RCD reset device. In some applications, the power converter may have an active clamp reset device, and the magnetizing current may go negative. In these applications having an active clamp reset device, before turning on the bias switch S.sub.VDDP, the body diode of the main switch S.sub.M may conduct in response to the negative magnetizing current. In some embodiments, the main switch S.sub.M may be turned on to conduct the negative magnetizing current until the magnetizing current is reset to a value approximately equal to zero. After that, the bias switch S.sub.VDDP is turned on and the magnetizing current is diverted to charge the bias capacitor C.sub.VDDP. In order to control the turn-on time of the bias switch S.sub.VDDP, a zero current crossing detector may be used to detect the magnetizing current and determine the turn-on time of the bias switch S.sub.VDDP accordingly.

[0098] FIG. 8 illustrates a schematic diagram of a fourth implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure. The flyback converter 600 is similar to the flyback converter 400 shown in FIG. 5 except that a depletion mode junction gate field-effect transistor (JFET) has been used as a high voltage startup circuit.

[0099] In operation, when the bias voltage VDDP is greater than the predetermined reference Vrefs, the comparator U1 generates a logic low signal. Such a logic low signal pulls the gate of the JFET S.sub.JFET to ground through the buffer U2. As a result of pulling the gate to ground, the gate-source voltage of the JFET S.sub.JFET is a negative voltage, thereby turning off the JFET S.sub.JFET.

[0100] During a startup process of the flyback converter 600, the gate-source voltage of the JFET S.sub.JFET is approximately equal to zero. According to the operating principle of depletion mode JFET transistors, the JFET S.sub.JFET is on and the input voltage VIN is applied to the gate of the bias switch S.sub.VDDP through the resistor R.sub.VDDDP and the turned-on JFET S.sub.JFET. The gate voltage of the bias switch S.sub.VDDP is clamped by the Zener diode D.sub.Z. In some embodiments, the Zener diode D.sub.Z clamps the gate voltage of the bias switch S.sub.VDDP to a level approximately equal to two times the bias voltage VDDP.

[0101] One advantageous feature of having the bias power supply shown in FIG. 8 is that the bias switch S.sub.VDDP can be used to provide a conductive path for charging the bias capacitor before the main switch S.sub.M starts switching during a startup process of the flyback converter 600. As a result, the flyback converter 60 does not require a dedicated startup switch.

[0102] It should be noted the JFET S.sub.JFET and its control circuit (e.g., U1 and U2) can be removed so as to simplify the design of the bias power supply. For example, the resistor R.sub.VDDDP may be connected to the Zener diode D.sub.Z directly to establish a voltage for driving the bias switch S.sub.VDDP. This variation of the bias power supply is within the scope of the claims.

[0103] FIG. 9 illustrates a schematic diagram of a fifth implementation of a primary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure. The flyback converter 700 is similar to the flyback converter 600 shown in FIG. 8 except that the bias switch S.sub.VDDP is connected to a drain of a sense switch S.sub.SENSE. In order to reduce the voltage stress on the bias switch S.sub.VDDP, the bias switch S.sub.VDDP is connected to the source of the main switch S.sub.M as shown in FIG. 9. The sense switch S.sub.SENSE is employed to replace the sense resistor R.sub.CS shown in FIG. 8. As shown in FIG. 9, the sense switch S.sub.SENSE and the main switch S.sub.M are connected in series between the primary winding N.sub.p and ground. The bias switch S.sub.VDDP is a p-type MOSFET. The drain of the bias switch S.sub.VDDP is connected to the common node of the sense switch S.sub.SENSE and the main switch S.sub.M. The source of the bias switch S.sub.VDDP is connected to the bias capacitor C.sub.VDDP.

[0104] It should be noted that the system configuration shown in FIG. 9 does not require a blocking diode connected in series with the bias switch S.sub.VDDP. By saving the blocking diode, the flyback converter 700 can further reduce power losses.

[0105] It should further be noted the bias switch S.sub.VDDP is implemented as a p-type MOSFET. This implementation is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the bias switch S.sub.VDDP is implemented as an n-type MOSFET. In order to drive the n-type MOSFET, the driver (e.g., U8) of the n-type MOSFET is a buffer rather than an inverter. Furthermore, the driver may include a level shifter because the source of the n-type MOSFET is not connected to ground.

[0106] The control circuit of the main switch S.sub.M includes a first comparator U1, a first buffer U2, a level shifter U3, a depletion mode JFET S.sub.JFET, a Zener diode D.sub.Z and an OR gate U9. The control circuit portion of the bias power supply includes a second comparator U4, a first logic gate U5, a second logic gate U6, a second butter U7 and an inverter U8. As shown in FIG. 9, the first logic gate U5 is an AND gate. The second logic gate U6 is an AND gate.

[0107] During a startup process of the flyback converter 700, the depletion mode JFET S.sub.JFET is turned on because the initial voltage applied to the gate-source of the depletion mode JFET S.sub.JFET is approximately equal to zero. The input voltage VIN is applied to the gate of the main switch S.sub.M through the turned-on JFET S.sub.JFET and the resistor R.sub.VDDDP. The gate voltage of the main switch S.sub.M is clamped by the Zener diode D.sub.Z. In response to the voltage applied to the gate of the main switch S.sub.M, the main switch S.sub.M is turned on.

[0108] During the startup process, the bias voltage VDDP is below the predetermined reference Vref. The second comparator U4 generates a logic high signal. The logic high signal becomes a logic low signal after passing the second logic gate U6 and the inverter U8. The logic low signal pulls down the gate of the bias switch S.sub.VDDP, thereby turning on the bias switch S.sub.VDDP. The magnetizing current of the transformer T1 starts to charge the bias capacitor C.sub.VDDP until the bias voltage VDDP reaches the predetermined reference Vref.

[0109] It should be noted the comparator U4 is a hysteretic comparator. The predetermined reference Vref includes two different voltage thresholds.

[0110] After the startup process of the flyback converter 700 finishes and the bias voltage has been established, the bias voltage VDDP is greater than a predetermined reference Vrefs. The first comparator U1 generates a logic low signal, which is able to turn off the depletion mode JFET S.sub.JFET to avoid unnecessary power losses.

[0111] In operation, the turn-on time of the bias switch S.sub.VDDP is in synchronization with the PWM signal. In particular, when the PWM signal has a logic low state, the comparison result from the second comparator U4 is overridden by the PWM signal at the second logic gate U6. On the other hand, when the PWM signal has a logic high state, the comparison result from the second comparator U4 can be applied to the bias switch S.sub.VDDP through the inverter U8. When the bias voltage VDDP is below the predetermined reference Vref and charging the bias capacitor C.sub.VDDP is necessary, the bias switch S.sub.VDDP is turned on. The detailed timing diagram of controlling the bias power supply shown in FIG. 9 will be discussed below with respect to FIG. 10.

[0112] It should be noted the JFET S.sub.JFET and its control circuit (e.g., U1 and U2) shown in FIG. 9 can be saved so as to simplify the design of the bias power supply. For example, the resistor R.sub.VDDDP may be connected to the Zener diode D.sub.Z directly to establish a voltage for driving the main switch S.sub.M during a startup process. This variation of the bias power supply is within the scope of the claims.

[0113] FIG. 10 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 9 in accordance with various embodiments of the present disclosure. The horizontal axis of FIG. 10 represents intervals of time. There are five vertical axes. The first vertical axis Y1 represents the magnetizing current flowing through the primary side of the transformer T1. The second vertical axis Y2 represents the gate drive signal of the primary side switch S.sub.M. The third vertical axis Y3 represents the bias voltage VDDP. The fourth vertical axis Y4 represents the gate drive signal of the bias switch of the bias power supply. The fifth vertical axis Y5 represents the gate drive signal of the sense switch S.sub.SENSE of the bias power supply.

[0114] At time t1, after the bias voltage VDDP reaches the lower threshold VREFL, the output of the comparator U4 transitions from a logic low state to a logic high state. At the same time, the PWM signal is applied to the primary switch S.sub.M, the current sense switch S.sub.SENSE and the bias switch S.sub.VDDP. At time t, the primary switch S.sub.M is turned on. Since the output of the comparator U4 has a logic high state, the current sense switch S.sub.SENSE remains off from t1 to t2 because the signal applied to the current sense switch S.sub.SENSE is a logic low signal after the output signal of the comparator U4 passes through an inverter (the circle attached to the logic gate U5) as shown in FIG. 9.

[0115] Also at time t1, the output signal of the comparator U4 passes through the logic gate U6 and the inverter U8 and becomes a logic low signal. The bias switch S.sub.VDDP, as a p-type MOSFET, is turned on by this logic low signal. The bias switch S.sub.VDDP remains on until t2 when the bias voltage VDDP reaches the high reference VREFH. During the time interval from t1 to t2, the magnetizing current is of a slope of (VIN−VDDP)/L.sub.M, where L.sub.M is the magnetizing inductance of the transformer T1.

[0116] At time t2, the output of the comparator U4 transitions from a logic high state to a logic low state. In response to this logic change, the signal applied to the gate of the current sense switch S.sub.SENSE becomes a logic high signal, which turns on the current sense switch S.sub.SENSE. During the time interval from t2 to t3, both the primary switch S.sub.M and the sense switch current sense switch S.sub.SENSE are turned on. The magnetizing current is of a slope of VIN/L.sub.M. During the time interval from t3 to t5, the timing diagram in FIG. 10 is similar to that shown in FIG. 7, and hence is not discussed in detail to avoid unnecessary repetition.

[0117] FIG. 11 illustrates a schematic diagram of a first implementation of a secondary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure. The flyback converter 800 shown in FIG. 11 is similar to the flyback converter 200 shown in FIG. 2 except that the secondary switch is replaced by a diode D1. In FIG. 11, like reference numerals refer to like elements. As such, descriptions on the like elements are not repeated. Furthermore, the secondary side controller 114 may comprise various function units. For simplicity, only relevant portions (e.g., the control circuit of the secondary side bias power supply) are illustrated in FIG. 11.

[0118] As shown in FIG. 11, the second bias power supply comprises a bias power converter portion and a control circuit portion. The bias power converter portion includes a diode D2, a switch S.sub.VDDS and a capacitor C.sub.VDDS. As shown in FIG. 11, the switch S.sub.VDDS is implemented as an n-type MOSFET. As shown in FIG. 11, the diode D2 and the switch S.sub.VDDS are connected in series between the secondary winding N.sub.s and the capacitor C.sub.VDDS. The diode D2 functions as a blocking diode. When the voltage at the bias winding N.sub.s is lower than the voltage across the capacitor C.sub.VDDS, the diode D2 prevents the capacitor C.sub.VDDS from being discharged.

[0119] The switch S.sub.VDDS is employed to control the charge of the capacitor C.sub.VDDS. In particular, the capacitor C.sub.VDDS is charged only when it is necessary. For example, when the bias voltage VDDS is lower than a predetermined reference Vref, the switch S.sub.VDDS is turned on. The magnetizing current from the secondary winding N.sub.s is diverted to charge the capacitor C.sub.VDDS through a conductive path formed by the diode D2 and the turned-on switch S.sub.VDDS. Once the bias voltage VDDS is above the predetermined reference Vref, the switch S.sub.VDDS is turned off accordingly.

[0120] The control circuit portion includes a comparator U1 and a level shifter U2. The non-inverting input of the comparator U1 is connected to the predetermined reference Vref. The inverting input of the comparator U1 is configured to receive the bias voltage VDDS. It should be noted the comparator U1 is a hysteretic comparator. The predetermined reference Vref includes two different voltage thresholds.

[0121] As shown in FIG. 11, the source of the switch S.sub.VDDS is not connected to ground. In fact, the source of the switch S.sub.VDDS is connected to the capacitor C.sub.VDDS. In order to drive the switch S.sub.VDDS, the gate drive signal has to be level-shifted from the level of ground to the level of VDDS. The level shifter U2 is employed to fulfill this function. The structure and operating principle of the level shifter are well known, and hence are not discussed herein.

[0122] It should be noted the bias supply shown in FIG. 11 is applicable to the power converters having an output voltage VO greater than the bias voltage VDDS. In the event when the bias voltage VDDS is greater than the output voltage of a power converter, a separate charge pump may be necessary. The separate charge pump may be connected to the drain of the bias switch S.sub.VDDS through one additional diode.

[0123] FIG. 12 illustrates a schematic diagram of a second implementation of a secondary side bias power supply of a flyback converter in accordance with various embodiments of the present disclosure. The flyback converter 900 shown in FIG. 12 is similar to the flyback converter 800 shown in FIG. 11 except the secondary diode is replaced by a synchronous switch S.sub.SR and a bias winding N.sub.b is employed to charge the bias capacitor C.sub.VDDS. The bias capacitor C.sub.VDDS is charged only when the bias voltage VDDS is lower than the predetermined reference voltage Vref. The bias winding charges the bias capacitor C.sub.VDDS through a conductive path formed by the bias switch S.sub.VDDS and the diode D2 after the primary switch S.sub.M has been turned off. The detailed operation principle of the bias power supply shown in FIG. 12 is similar to that of the bias power supply shown in FIG. 11, and hence is not discussed in further detail herein.

[0124] It should be noted in FIGS. 11 and 12, the bias voltage VDDS should be less than or equal to the lower end of the output voltage of the flyback converter. As discussed above with respect to FIG. 4, the magnetizing current of the transformer T1 can charge the bias capacitor C.sub.VDDS first, and then charges the output capacitor of the flyback converter if bias voltage VDDS is less than or equal to the lower end of the output voltage of the flyback converter.

[0125] FIG. 13 illustrates a schematic diagram of an implementation of a primary side bias power supply of a forward converter in accordance with various embodiments of the present disclosure. The forward converter 1000 is a converter employing a RCD reset device formed by capacitor C.sub.RCD, resistor R.sub.RCD and diode D.sub.RCD as shown in FIG. 13. The operating principle and the structure of RCD forward converters are well known, and hence are not discussed herein to avoid repetition.

[0126] The secondary side of the forward converter 100 comprises a synchronous rectifier and an output filter. The synchronous rectifier comprises a first switch S.sub.SCR1 and a second switch S.sub.CR2. The output filter comprises an output inductor Lo and an output capacitor Co as shown in FIG. 13.

[0127] The switches of the synchronous rectifier may be formed by any suitable devices such as metal oxide semiconductor field effect transistor (MOSFET) devices, bipolar junction transistor (BJT) devices, super junction transistor (SJT) devices, insulated gate bipolar transistor (IGBT) devices and the like.

[0128] FIG. 13 illustrates a schematic diagram of a forward converter having a synchronous rectifier according to an embodiment of the present disclosure. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the synchronous rectifier may be replaced by a diode rectifier depending on different applications and design needs. Furthermore, in some high power applications, each switch shown in FIG. 13 may be replaced by a plurality of switches connected in parallel.

[0129] The bias power supply shown in FIG. 13 is similar to the bias power supply shown in FIG. 3, and hence is not discussed in further detail. The primary side gate drive signal G.sub.PRI is determined by the PWM signal and the comparison result of the comparator U1. When the bias switch S.sub.VDDP is turned on and the bias winding N.sub.b charges the bias capacitor C.sub.VDDP, the output signal of the comparator U1 overrides the PWM signal. As a result, the primary switch S.sub.M remains off until the charge of the bias capacitor C.sub.VDDP finishes. The detailed timing diagram of controlling the bias power supply shown in FIG. 13 will be discussed below with respect to FIG. 14.

[0130] It should be noted that the bias power supplies described above in FIGS. 3, 5-6 and 8-9 are also applicable to the forward converter shown in FIG. 11.

[0131] It should further be noted the power converters in FIGS. 3, 5-6, 8-9 and 11 can achieve better efficiency because the bias power supplies do not generate unnecessary power losses. First, the charge of the bias capacitor occurs only when it is necessary. Furthermore, the charge of the bias capacitor stops after the bias voltage reaches a predetermined threshold. Second, the current for charging the bias capacitor is diverted from a magnetizing current. These two conditions help the bias power supplies in FIGS. 3, 5-6, 8-9 and 11 achieve better efficiency.

[0132] FIG. 14 illustrates an embodiment timing diagram of controlling the bias power supply shown in FIG. 13 in accordance with various embodiments of the present disclosure. The timing diagram shown in FIG. 14 is similar to that shown in FIG. 4, and hence is not discussed again to avoid repetition.

[0133] FIG. 15 illustrates a schematic diagram of a first implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure. The switching converter 1100 may be any suitable power converters comprising a magnetic device (e.g., an inductor) and a switch connected in series with the magnetic device. For example, in some embodiments, the switching converter 1100 can be an isolated power converter such as a full bridge power converter. In alternative embodiments, the switching converter 1100 can be a non-isolated power converter such as a four-switch buck boost converter.

[0134] The switching converter 1100 comprises a magnetic device L1. As shown in FIG. 15, the magnetic device L1 and the main switch S.sub.M are connected in series as shown in FIG. 15. In some embodiments, the magnetic device L1 is an inductor. In alternative embodiments, the magnetic device L1 is a bias winding of a transformer. Furthermore, the magnetic device L1 can be a primary winding or a secondary winding of a transformer.

[0135] The bias power supply generates two bias voltages, namely a low bias voltage VDDL and a high bias voltage VDDH. In some embodiments, the values of the low bias voltage VDDL and the high bias voltage VDDH are determined by references VrefL and VrefH respectively. Both VrefL and VrefH are predetermined and may vary depending on different applications and design needs.

[0136] The switch S.sub.M, the diode D.sub.VDD and the bias switch S.sub.VDD are connected in a manner similar to that shown in FIG. 5. In order to establish two bias voltages, two switch-capacitor networks are connected to the bias switch S.sub.VDD. A first switch S.sub.L and a first capacitor C.sub.L are connected in series between the bias switch S.sub.VDD and ground. The low bias voltage VDDL is established at the common node of the first switch S.sub.L and the first capacitor C.sub.L. The gate of the first switch S.sub.L is controlled by a first control circuit formed by a first comparator U9, a first logic gate U1 and a first inverter U7. In some embodiments, the first logic gate U1 is implemented as an AND gate.

[0137] A second switch S.sub.H and a second capacitor C.sub.H are connected in series between the bias switch S.sub.VDD and ground. The high bias voltage VDDH is established at the common node of the second switch S.sub.H and the second capacitor C.sub.H. The gate of the second switch S.sub.H is controlled by a second control circuit formed by a second comparator U10, a second logic gate U2 and a second inverter U8. In some embodiments, the second logic gate U2 is an AND gate.

[0138] The operating principle of the first control circuit is similar to that of the second control circuit except that the output of the first comparator U9 can override the output of the second comparator U10. In other words, when both the voltages of the bias capacitors C.sub.L and C.sub.H are lower than their respective references VrefL and VrefH, the charges of the bias capacitors C.sub.L and C.sub.H are applied sequentially. According to the logic circuit shown in FIG. 15, the bias capacitor C.sub.L is charged first. The logic circuit shown in FIG. 15 indicates the output signal of the first comparator U9 overrides the charge command generated by the second comparator U10. The bias capacitor C.sub.H cannot be charged until the bias capacitor C.sub.L is charged to a level over its reference voltage.

[0139] It should be noted that the charge sequence used in FIG. 15 is selected purely for demonstration purposes and are not intended to limit the various embodiments of the present disclosure to any particular charge sequence. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the bias capacitor C.sub.H can be charged first by simply swapping the first control circuit and the second control circuit.

[0140] As shown in FIG. 15, an inductor current i.sub.L flows through the inductor. The inductor current may charge capacitors C.sub.L and/or C.sub.H if necessary. As indicated by the control circuits (logic gate U4) of the main switch S.sub.M and the bias switch S.sub.VDD, the turn-on signal of the bias switch S.sub.VDD can override the PWM signal applied to the switch S.sub.M. As a result, the charge of the capacitors C.sub.L and/or C.sub.H occurs before turning on the switch S.sub.M. This timing sequence is similar to that shown in FIG. 7, and hence is not discussed again.

[0141] It should be noted FIG. 15 shows the first switch S.sub.L and the second switch S.sub.H are implemented as p-type transistors. This implementation is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the first switch S.sub.L and the second switch S.sub.H can be implemented as n-type transistors. In order to drive the n-type transistors, the drivers (e.g., U7 and U8) may be modified accordingly. Each driver is replaced by a buffer. In addition, the driver may include a level shifter because the sources of the n-type transistors are not connected to ground.

[0142] FIG. 16 illustrates a schematic diagram of a second implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure. The bias power supply of the switching converter 1200 shown in FIG. 16 is similar to that shown in FIG. 15 except that two switch-capacitor networks are connected to a common node of a main switch S.sub.M and a sense switch S.sub.SENSE. The operating principle of the bias supply shown in FIG. 16 is similar to that described above with respect to FIG. 15, and hence is not discussed again.

[0143] It should be noted FIG. 16 shows the first switch S.sub.L and the second switch S.sub.H are implemented as p-type transistors. This implementation is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the first switch S.sub.L and the second switch S.sub.H can be implemented as n-type transistors. In order to drive the n-type transistors, the drivers (e.g., U7 and U8) may be modified accordingly. Each driver is replaced by a buffer. In addition, the driver may include a level shifter because the sources of the n-type transistors are not connected to ground.

[0144] It should further be noted a blocking diode D.sub.VDD1 is connected between the switch S.sub.L, and the common node of the main switch S.sub.M and the sense switch S.sub.SENSE. The blocking diode D.sub.VDD1 is employed to prevent the capacitor C.sub.L from being discharged when the voltage at the common node of the main switch S.sub.M and the sense switch S.sub.SENSE is lower than the voltage of the capacitor C.sub.L.

[0145] One advantageous feature of having the configuration shown in FIG. 16 is only one high voltage switch (e.g., S.sub.M) is necessary in some high voltage applications. For example, in some high voltage applications, switches S.sub.SENSE, S.sub.L and S.sub.H can be implemented as low voltage transistors.

[0146] FIG. 17 illustrates a schematic diagram of a third implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure. The bias power supply of the switching converter 1300 shown in FIG. 17 is similar to that shown in FIG. 16 except that a second blocking diode D.sub.VDD2 is connected in series with the switch S.sub.H.

[0147] One advantageous feature of having the second blocking diode D.sub.VDD2 is the capacitors C.sub.L and C.sub.H can be independently charged through the extra diode. In other words, it not necessary to consider the charge sequence between the capacitors C.sub.L and C.sub.H.

[0148] It should be noted FIG. 17 shows the first switch S.sub.L and the second switch S.sub.H are implemented as p-type transistors. This implementation is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the first switch S.sub.L and the second switch S.sub.H can be implemented as n-type transistors. In order to drive the n-type transistors, the drivers (e.g., U7 and U8) may be modified accordingly. Each driver is replaced by a buffer. In addition, the driver may include a level shifter because the sources of the n-type transistors are not connected to ground.

[0149] FIG. 18 illustrates a schematic diagram of a third implementation of a bias power supply of a switching converter in accordance with various embodiments of the present disclosure. The switching converter 1400 includes an inductor connected to the positive output of the switching converter 1400 through a main switch S.sub.M.

[0150] The bias power supply includes two bias voltages, namely a first bias voltage VDD1 and a second bias voltage VDD2. The values of the first bias voltage VDD1 and the second bias voltage VDDH are determined by references Vref1 and Vref2 respectively. Both Vref1 and Vref2 are predetermined and may vary depending on different applications and design needs.

[0151] In order to establish two bias voltages, two diode-switch-capacitor networks are connected to the common node of the inductor and the switch S.sub.M. A first diode D1, a first switch S1 and a first capacitor C1 are connected in series between the common node of the inductor and the switch S.sub.M, and ground. The first bias voltage VDD1 is established at the common node of the first switch S1 and the first capacitor C1. The gate of the first switch S1 is controlled by a first control circuit formed by a first comparator U11 and a first level shifter U12.

[0152] A second diode D2, a second switch S2 and a second capacitor C2 are connected in series between the common node of the inductor and the switch S.sub.M, and ground. The second bias voltage VDD2 is established at the common node of the second switch S2 and the second capacitor C2. The gate of the second switch S2 is controlled by a second control circuit formed by a second comparator U21 and a second level shifter U22.

[0153] The operating principle of the first control circuit and the second control circuit shown in FIG. 18 is similar to that of the second control circuit shown in FIG. 11, and hence is not discussed again herein.

[0154] It should be noted both the first diode D1 and the second diode D2 function as blocking diodes. One advantageous feature of having two blocking diode is the capacitors C1 and C2 can be independently charged through these two blocking diodes. In other words, it not necessary to consider the charge sequence between the capacitors C1 and C2.

[0155] It should further be noted the two bias voltages shown in FIGS. 15-18 are merely an example. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, depending on different applications and design needs, any number of bias voltages can be established based upon the circuit and control scheme described above with respect to FIGS. 15-18.

[0156] FIG. 19 illustrates a schematic diagram of an implementation of multiple bias power supplies of a switching converter in accordance with various embodiments of the present disclosure. FIG. 19 only shows a primary side of an isolated power converter 1500. Depending on different system configurations, the bias supplies shown in FIG. 19 can be applicable to different isolated power converters such as flyback converters, forward converters, half-bridge converters, full-bridge converters, push-pull converters, LLC resonant converters, any combinations thereof and the like.

[0157] The primary side bias power supply includes two bias voltages, namely a first bias voltage VDD1 and a second bias voltage VDD2. The second bias power supply includes one bias voltage, namely a secondary bias voltage VDDS. The operating principle of the primary side bias power supply is similar to that described above with respect to FIG. 3, and hence is not discussed herein. The operating principle of the secondary side bias power supply is similar to that described above with respect to FIG. 12, and hence is not discussed herein.

[0158] It should be noted that the bias power supply configuration shown in FIG. 15 is merely an example. A personal skilled in the art would understand any combinations of the primary bias power supplies and the secondary bias power supplies shown in this disclosure can be used to provide bias power for the isolated power converter 1500.

[0159] One advantageous feature of having the bias power supplies shown in FIGS. 15-19 is multiple bias power supplies can be efficiently generated through using the magnetizing current of a power converter. The power converter can be a non-isolated power converter. Alternatively, the power converter can be an isolated power converter.

[0160] For an isolated power converter, the multiple bias power supplies can be placed at a primary side of the power converter (e.g., the bias power supplies shown in FIGS. 15-17). Alternatively, the multiple bias power supplies can be placed at a secondary side of the power converter (e.g., the bias power supplies shown in FIG. 18). Moreover, the multiple bias power supplies can be placed at both the primary side and the secondary side of the power converter (e.g., the bias power supplies shown in FIG. 19).

[0161] FIG. 20 illustrates a flow chart of controlling the bias power supply in FIG. 3 in accordance with various embodiments of the present disclosure. This flowchart shown in FIG. 20 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated in FIG. 20 may be added, removed, replaced, rearranged and repeated.

[0162] Referring back to FIGS. 3-4, the bias power supply of the flyback converter 300 comprises a bias switch and a diode connected in series between a bias winding and a bias capacitor. A comparator U1 is used to monitor the voltage across the bias capacitor. When the voltage across the bias capacitor is lower than a predetermined value, the bias switch is turned on and the bias capacitor is charged by a magnetizing current of the bias winding.

[0163] At step 2002, the comparator U1 is used to detect a voltage across the bias capacitor. As shown in FIG. 3, the inverting input of the comparator U1 is connected to a positive terminal of the bias capacitor.

[0164] At step 2004, the detected bias capacitor voltage is compared with a first predetermined threshold. At step 2006, if the detected bias voltage is less than the first predetermined threshold, the bias switch is turned on immediately after a main switch has been turned off and a magnetizing current charges the bias capacitor.

[0165] At step 2008, the magnetizing current keeps charging the bias capacitor until the bias voltage is over a second predetermined threshold. In some embodiments, the second predetermined threshold is greater than the first predetermined threshold.

[0166] FIG. 21 illustrates a flow chart of controlling the bias power supply in FIG. 7 in accordance with various embodiments of the present disclosure. This flowchart shown in FIG. 21 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated in FIG. 21 may be added, removed, replaced, rearranged and repeated.

[0167] Referring back to FIGS. 6-7, the bias power supply of the flyback converter 500 comprises a bias switch and a diode connected in series between a primary winding and a bias capacitor. A comparator U1 is used to monitor the voltage across the bias capacitor. When the voltage across the bias capacitor is lower than a predetermined value, the bias switch is turned on and the bias capacitor is charged by a magnetizing current of the primary winding.

[0168] At step 2102, the comparator is used to detect a voltage across the bias capacitor. As shown in FIG. 6, the inverting input of the comparator U1 is connected to a positive terminal of the bias capacitor.

[0169] At step 2104, the detected bias capacitor voltage is compared with a first predetermined threshold. At step 2106, if the detected bias voltage is less than the first predetermined threshold, the bias switch is turned on and a magnetizing current charges the bias capacitor. During the time interval of turning on the bias switch, the main switch remains off.

[0170] At step 2108, the magnetizing current keeps charging the bias capacitor until the bias voltage is over a second predetermined threshold. In some embodiments, the second predetermined threshold is greater than the first predetermined threshold. The main switch is turned on immediately after the bias switch has been turned off.

[0171] FIGS. 22-24 illustrate various implementations of a snubber used in a bias power supply. The snubbers shown in FIGS. 22-24 are applicable to any of the bias switches illustrated in FIGS. 3, 5-6, 8-9, 11-13 and 15-19.

[0172] FIG. 22 illustrates a schematic diagram of a first implementation of the snubber in accordance with various embodiments of the present disclosure. The snubber 2200 includes a capacitor C.sub.RC and a resistor R.sub.RC connected in series. The snubber 2200 is connected in parallel with the bias switch S.sub.VDD. As shown in FIG. 22, the bias switch S.sub.VDD and the blocking diode D.sub.VDD are connected in series. More particularly, a cathode of the blocking diode D.sub.VDD is directly connected to a cathode of a body diode of the bias switch S.sub.VDD.

[0173] The snubber 2200 is employed to reduce the turn-off ringing overshoot across the bias switch S.sub.VDD. Depending on different applications and design needs, the values of the capacitor C.sub.RC and the resistor R.sub.RC are selected accordingly.

[0174] It should be noted that the n-type bias switch shown in FIG. 22 is merely an example. Depending on different applications and design needs, the bias switch S.sub.VDD may be implemented as a p-type transistor.

[0175] FIG. 23 illustrates a schematic diagram of a second implementation of the snubber in accordance with various embodiments of the present disclosure. The snubber 2300 includes a capacitor C.sub.RC, a resistor R.sub.RC and a diode D.sub.RCD. The capacitor C.sub.RC and the resistor R.sub.RC are connected in parallel to form a resistor-capacitor network. The resistor-capacitor network is further connected in series with the diode D.sub.RCD. The snubber 2300 is connected in parallel with the bias switch S.sub.VDD.

[0176] The snubber 2300 is employed to reduce the turn-off ringing overshoot across the bias switch S.sub.VDD. Depending on different applications and design needs, the values of the capacitor C.sub.RC and the resistor R.sub.RC are selected accordingly.

[0177] FIG. 24 illustrates a schematic diagram of a third implementation of the snubber in accordance with various embodiments of the present disclosure. The snubber 2400 includes a capacitor C.sub.C. The capacitor C.sub.C is connected to a common node of the bias switch S.sub.VDD and the blocking diode D.sub.VDD as shown in FIG. 24.

[0178] The snubber 2400 is employed to slow down the turn-off ringing overshoot across the bias switch S.sub.VDD. Depending on different applications and design needs, the value of the capacitor C.sub.C is selected accordingly.

[0179] FIG. 25 illustrates another embodiment timing diagram of controlling the bias power supply shown in FIG. 3 in accordance with various embodiments of the present disclosure. The horizontal axis of FIG. 25 represents intervals of time. There are four vertical axes. The first vertical axis Y1 represents the magnetizing current flowing through the primary side of the transformer T1 shown in FIG. 3. The second vertical axis Y2 represents the gate drive signal of the primary side switch S.sub.M. The third vertical axis Y3 represents the bias voltage VDDP shown in FIG. 3. The fourth vertical axis Y4 represents the gate drive signal of the bias switch S.sub.VDDP.

[0180] At time t1, the primary side switch S.sub.M is turned on. As a result of turning on the primary side switch S.sub.M, the magnetizing current ramps up from time t1 until time 2 when the primary side switch S.sub.M is turned off. From time t1 to time t2, the bias voltage VDDP drops as shown in FIG. 25.

[0181] At time t2, the primary side switch S.sub.M is turned off. From t2 to t3, the magnetizing current is reset by the RCD reset device shown in FIG. 3. The magnetizing current i.sub.LM decreases in a linear manner as shown in FIG. 25. From t2 to t3, the magnetizing current is of a slope of −V.sub.C/L.sub.M, where V.sub.C is the voltage across the capacitor C.sub.RCD.

[0182] At time t3, the bias voltage drops below the lower threshold VREFL, the bias switch S.sub.VDDP is turned on as indicated by the gate drive signal G.sub.VDDP. In response to the turned-on bias switch S.sub.VDDP, the magnetizing current from the bias winding N.sub.b starts to charge the bias capacitor C.sub.VDDP and the bias voltage VDDP increases in a linear manner as shown in FIG. 25.

[0183] At time t4, the bias voltage reaches the upper threshold VREFH, the output of the comparator U1 transitions from a logic high state to a logic low state. In response to this logic state change, the bias switch S.sub.VDDP is turned off at time t4 as indicated by the gate drive signal G.sub.VDDP. During the time interval from t3 to t4, the magnetizing current is partially reset by the bias voltage VDDP. The magnetizing current is of a slope of −VDDP/L.sub.M, where L.sub.M is the magnetizing inductance of the transformer T1.

[0184] During the time interval from t4 to t5, the magnetizing current is reset by the RCD reset device. The magnetizing current i.sub.LM decreases in a linear manner as shown in FIG. 25. From t4 to t5, the magnetizing current is of a slope of −V.sub.C/L.sub.M, where V.sub.C is the voltage across the capacitor C.sub.RCD. At t5, the magnetizing current is reset to zero. At time t6, a new switching cycle starts and the magnetizing current i.sub.LM starts to increase after the primary switch S.sub.M has been turned on.

[0185] As described above with respect to FIGS. 3-4, the bias voltage VDDP is less than or equal to the lower end of the output voltage of the flyback converter 300. Since the bias voltage VDDP is less than or equal to the lower end of the output voltage of the flyback converter 300, the magnetizing current can charge the bias capacitor in any time interval from t2 to t5.

[0186] It should be noted the bias capacitor charge time (from t3 to t4) shown in FIG. 25 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the bias capacitor charge may occur immediately after the main switch has been turned off. Alternatively, the bias capacitor charge may occur in the middle of the magnetizing current resetting period (e.g., from t2 to t5). Furthermore, the bias capacitor charge may occur at the end of the magnetizing current resetting period (e.g., from t2 to t5).

[0187] FIG. 26 illustrates another embodiment timing diagram of controlling the bias power supply shown in FIG. 5 in accordance with various embodiments of the present disclosure. The horizontal axis of FIG. 26 represents intervals of time. There are four vertical axes. The first vertical axis Y1 represents the magnetizing current flowing through the primary side of the transformer T1 shown in FIG. 5. The second vertical axis Y2 represents the gate drive signal of the primary side switch S.sub.M. The third vertical axis Y3 represents the bias voltage VDDP. The fourth vertical axis Y4 represents the gate drive signal of the bias switch of the bias power supply.

[0188] At t1, the primary side switch S.sub.M is turned on. As a result of turning on the primary side switch S.sub.M, the magnetizing current ramps up from time t1 to time t2 until the bias switch is turned on. During the time interval from t1 to t2, the magnetizing current is of a slope of VIN/L.sub.M.

[0189] At time t2, after the bias voltage reaches the lower threshold VREFL, the output of the comparator U1 transitions from a logic low state to a logic high state. The PWM signal is applied to both the primary switch S.sub.M and the bias switch S.sub.VDDP. Both the PWM signal and the output of the comparator U1 have a logic high state. As a result, the first logic gate U2 generates a logic high signal, which is used to turn on the bias switch S.sub.VDDP through the level shifter U3. Also at time t2, the logic high state from the comparator U1, after passing an inverter, turns off the main switch SM. As shown in FIG. 26, from t2 to t3, the bias switch gate drive signal G.sub.VDDP is of a logic high state.

[0190] In response to the turned-on bias switch S.sub.VDDP, the magnetizing current of the transformer T1 charges the bias capacitor C.sub.VDDP in a linear manner from t2 to t3. During the time interval from t2 to t3, the magnetizing current is of a slope of (VIN−VDDP)/L.sub.M, where L.sub.M is the magnetizing inductance of the transformer T1. During the time interval from t2 to t3, the primary switch S.sub.M is off as shown in FIG. 26.

[0191] At time t3, after the bias voltage VDDP reaches VREFH, the output of the comparator U1 transitions from a logic high state to a logic low state. In response to this logic state change, the bias switch S.sub.VDDP is turned off and the primary side switch S.sub.M is turned on. As a result of turning on the primary side switch S.sub.M, the magnetizing current ramps up from time t3 to time t4 until the primary side switch S.sub.M is turned off. During the time interval from t3 to t4, the magnetizing current is of a slope of VIN/L.sub.M.

[0192] It should be noted the bias capacitor charge time (from t2 to t3) shown in FIG. 26 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the bias capacitor charge may occur immediately after the PWM signal has been applied to the bias switch and the main switch. Alternatively, the bias capacitor charge may occur in the middle of the PWM turn-on period (e.g., from t1 to t4). Furthermore, the bias capacitor charge may occur at the end of the PWM turn-on period (e.g., from t1 to t4).

[0193] Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0194] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.