FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF, AND SEMICONDUCTOR STRUCTURE

Abstract

A field effect transistor and a preparation method thereof, and a semiconductor structure are provided. An example field effect transistor includes: a substrate structure, a source, a drain, and a gate. The source and the drain are arranged on the substrate structure in a first direction, and a channel region is formed between the source and the drain. A channel layer is formed in the channel region, and N carbon nanotubes extending in the first direction are embedded in the channel layer, where N is an integer greater than or equal to 1. Two ends of each of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path. The gate is formed on the channel layer. In the channel region between the source and the drain, electron conduction is implemented by using the carbon nanotube disposed in the channel layer.

Claims

1. A field effect transistor, comprising: a substrate structure, a source, a drain, and a gate, wherein: the source and the drain are arranged on the substrate structure in a first direction, and a channel region is formed between the source and the drain; a channel layer is formed in the channel region, N carbon nanotubes extending in the first direction are embedded in the channel layer, wherein N is an integer greater than or equal to 1, and two ends of each of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path; and the gate is formed on the channel layer.

2. The field effect transistor according to claim 1, wherein N is greater than or equal to 3, and the N carbon nanotubes are distributed in an array.

3. The field effect transistor according to claim 1, wherein the channel layer comprises at least one channel interlayer, each channel interlayer comprises a first oxide layer and a second oxide layer that are stacked in a direction from the substrate structure to the channel layer, and at least one carbon nanotube is embedded between the first oxide layer and the second oxide layer.

4. The field effect transistor according to claim 3, wherein a metal silicate compound is formed on a surface that is of the first oxide layer and that is in contact with the at least one carbon nanotube.

5. The field effect transistor according to claim 3, wherein a metal oxide is formed on a surface that is of the first oxide layer and that is in contact with the at least one carbon nanotube.

6. The field effect transistor according to claim 1, wherein a first contact layer is disposed on a side that is of the source and that faces the channel layer, a second contact layer is disposed on a side that is of the drain and that faces the channel layer, one end of at least one of the N carbon nanotubes is connected to the source by using the first contact layer, and the other end of the at least one of the N carbon nanotubes is connected to the drain by using the second contact layer; and wherein conductivity of the first contact layer is higher than conductivity of the source, and conductivity of the second contact layer is higher than conductivity of the drain.

7. The field effect transistor according to claim 6, wherein a material of the first contact layer is gold or a gold alloy, and a material of the second contact layer is gold or a gold alloy.

8. The field effect transistor according to claim 1, wherein a capacitive layer and a gate dielectric layer are further stacked between the gate and the channel layer in a direction from the gate to the channel layer.

9. The field effect transistor according to claim 1, wherein the substrate structure comprises a silicon substrate and a well region formed on the silicon substrate.

10. The field effect transistor according to claim 9, wherein the substrate structure further comprises an insulation layer disposed on a side that is of the well region and that is away from the silicon substrate, and the source and the drain are located on the insulation layer.

11. A semiconductor structure, comprising two field effect transistors wherein the two field effect transistors are isolated from each other by using an isolator, and wherein each of the two field effect transistors comprises: a substrate structure, a source, a drain, and a gate, wherein: the source and the drain are arranged on the substrate structure in a first direction, and a channel region is formed between the source and the drain; a channel layer is formed in the channel region, N carbon nanotubes extending in the first direction are embedded in the channel layer, wherein N is an integer greater than or equal to 1, and two ends of each of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path; and the gate is formed on the channel layer.

12. A preparation method for a field effect transistor, comprising: preparing a substrate structure; preparing a channel layer on the substrate structure, wherein N carbon nanotubes extending in a first direction are embedded in the channel layer, two ends of each of the N carbon nanotubes are exposed from the channel layer, and N is an integer greater than or equal to 1; forming a gate on the channel layer; and forming a source and a drain respectively on two sides of the channel layer, wherein the source and the drain are respectively connected to the two ends of the each of the N carbon nanotubes to form a conductive path.

13. The preparation method according to claim 12, wherein the preparing a channel layer on the substrate structure comprises performing the following steps at least once: forming a first oxide layer on a base material, wherein the base material is a structure that is of the substrate structure and that is used to form a side of the channel layer; forming at least one carbon nanotube on the first oxide layer; and forming a second oxide layer on a surface of the carbon nanotube to cover the carbon nanotube.

14. The preparation method according to claim 13, wherein after the forming a first oxide layer on a base material and before the forming at least one carbon nanotube on the first oxide layer, the method further comprises: preparing a metal oxide on the first oxide layer, wherein the metal oxide reacts with the first oxide layer to form a metal silicate compound.

15. The preparation method according to claim 14, wherein the forming at least one carbon nanotube on the first oxide layer comprises: synthesizing the carbon nanotube on the metal silicate compound by using a vapor deposition method under an action of a catalyst.

16. The preparation method according to claim 13, wherein after the forming a first oxide layer on a base material and before the forming at least one carbon nanotube on the first oxide layer, the method further comprises: adding metal to the first oxide layer to form a metal oxide.

17. The preparation method according to claim 12, wherein a first contact layer is disposed on a side that is of the source and that faces the channel layer, a second contact layer is disposed on a side that is of the drain and that faces the channel layer, one end of at least one of the N carbon nanotubes is connected to the source by using the first contact layer, and the other end of the at least one of the N carbon nanotubes is connected to the drain by using the second contact layer, wherein conductivity of the first contact layer is higher than conductivity of the source, and conductivity of the second contact layer is higher than conductivity of the drain; and before the preparing a channel layer in which at least one carbon nanotube is embedded on the substrate structure, and forming a gate on the channel layer, the method further comprises: depositing high-conductivity metal on the two sides of the channel layer to form the first contact layer and the second contact layer on the two sides of the channel layer, wherein the two ends of the carbon nanotube are respectively connected to the first contact layer and the second contact layer.

18. The preparation method according to claim 12, wherein in a direction from the gate to the channel layer, a capacitive layer and a gate dielectric layer are further stacked between the gate and the channel layer, and the forming a gate on the channel layer comprises: preparing the gate dielectric layer on the channel layer; preparing the capacitive layer on the gate dielectric layer; and preparing the gate on the capacitive layer.

19. The preparation method according to claim 12, wherein the substrate structure comprises a silicon substrate and a well region formed on the silicon substrate, and the preparing a substrate structure comprises: doping an impurity on the silicon substrate to form the well region.

20. The preparation method according to claim 19, wherein the substrate structure further comprises an insulation layer formed on a side that is of the well region and that is away from the silicon substrate, and after the doping an impurity on the silicon substrate to form the well region, the method further comprises: forming the insulation layer on a side that is of the well region and that is away from the silicon substrate.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1 is a schematic diagram of a structure of a field effect transistor in the conventional technology;

[0043] FIG. 2a to FIG. 2f are schematic diagrams of a structure of a field effect transistor according to an embodiment of this application;

[0044] FIG. 3a to FIG. 3d are schematic diagrams of a distribution manner of carbon nanotubes in a channel layer in a field effect transistor according to an embodiment of this application;

[0045] FIG. 4 is a schematic diagram of a structure of a channel layer in a field effect transistor according to an embodiment of this application;

[0046] FIG. 5 is a schematic diagram of a structure of a channel interlayer in a field effect transistor according to an embodiment of this application;

[0047] FIG. 6a and FIG. 6b are schematic diagrams of a structure of a first interlayer in a field effect transistor according to an embodiment of this application;

[0048] FIG. 7 is a schematic diagram of a structure of a semiconductor structure according to an embodiment of this application;

[0049] FIG. 8 is a schematic flowchart of a preparation method for a field effect transistor according to an embodiment of this application;

[0050] FIG. 9 is a schematic flowchart of a preparation method for a substrate structure in a field effect transistor according to an embodiment of this application;

[0051] FIG. 10 is a schematic flowchart of a preparation method for a channel interlayer in a field effect transistor according to an embodiment of this application;

[0052] FIG. 11 is a schematic flowchart of a preparation method for a field effect transistor according to an embodiment of this application;

[0053] FIG. 12 is a schematic flowchart of a preparation method for a field effect transistor according to an embodiment of this application;

[0054] FIG. 13 is a schematic flowchart of a preparation method for a field effect transistor according to an embodiment of this application; and

[0055] FIG. 14 is a schematic flowchart of a preparation method for a gate in a field effect transistor according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

[0056] An application scenario of this application is first described. Currently, a size of a conventional transistor cannot adapt to a development trend of miniaturization, lightness, and thinning of an electronic device due to a process limitation. Therefore, embodiments of this application provide a field effect transistor and a preparation method thereof, and a semiconductor structure. Such a field effect transistor has stronger performance and a larger drive current, and can meet a development requirement of miniaturization of the electronic device.

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following further describes this application in detail with reference to the accompanying drawings.

[0058] Terms used in the following embodiments are merely for the purpose of describing specific embodiments, but are not intended to limit this application. The terms “one”, “a”, “the”, “the foregoing”, “this”, and “the one” of singular forms used in the specification and the appended claims of this application are also intended to include expressions such as “one or more”, unless otherwise specified in the context clearly.

[0059] Referring to “an embodiment” or “some embodiments” or the like in the specification means that one or more embodiments of this application include a specific feature, structure, or characteristic described with reference to the embodiment. Therefore, statements such as “in an embodiment”, “in some embodiments”, “in some other embodiments”, and “in other embodiments” that appear at different places in this specification do not necessarily mean referring to a same embodiment. Instead, the statements mean “one or more but not all of the embodiments”, unless otherwise specifically emphasized in another manner. The terms “include”, “contain”, “have”, and their variants all mean “include but are not limited to”, unless otherwise specifically emphasized in another manner.

[0060] FIG. 2a is a schematic diagram of a structure of a field effect transistor according to an embodiment of this application. The field effect transistor includes a substrate structure 1, a source 2, a drain 3, and a gate 4. In a Y direction shown in FIG. 2a, the substrate structure 1 is located at a bottom of the entire transistor structure, a top of the substrate structure 1 is divided into a first area A1 and a second area A2, and there is a spacing between the first area A1 and the second area A2. The source 2 is correspondingly disposed in the first area A1, the drain 3 is correspondingly disposed in the second area A2, space is formed between the source 2 and the drain 3, the space is set as a channel region B, and the gate 4 is correspondingly located above the channel region B. A channel layer 5 is formed in the channel region B, and a plurality of carbon nanotubes 6 are embedded in the channel layer 5. Herein, structures of the channel layer 5 and the carbon nanotubes 6 are shown in a local section. The plurality of carbon nanotubes 6 herein are distributed in parallel. As shown in FIG. 2a, each carbon nanotube 6 extends in a first direction (that is, an X direction in FIG. 2a, where the X direction is perpendicular to the Y direction), an axis of any carbon nanotube 6 is parallel to the X direction, and two ends of each carbon nanotube 6 are respectively connected to the source 2 and the drain 3, so as to implement current conduction between the source 2 and the drain 3. It should be understood that a quantity of carbon nanotubes 6 herein is N, where N is an integer greater than or equal to 1. A plurality of carbon nanotubes are shown in FIG. 2a. When there is only one carbon nanotube 6, an effect of conducting the source 2 and the drain 3 may also be implemented, and when there are a plurality of carbon nanotubes 6, electron circulation efficiency between the source 2 and the drain 3 may be enhanced. The carbon nanotube 6 is connected to the source 2 and the drain 3 in a direct contact connection manner to implement circuit conduction. Certainly, a contact medium may be further added to implement circuit conduction in an indirect connection manner.

[0061] In a possible implementation, in a structure of a field effect transistor shown in FIG. 2b, disposing a first contact layer 21 on a side that is of the source 2 and that faces the channel region B is equivalent to disposing the first contact layer 21 between the source 2 and the channel layer 5, so that the source 2 and the channel layer 5 are connected by using the first contact layer 21. An end that is of the carbon nanotube 6 embedded in the channel layer 5 and that faces the source 2 may be in contact with the first contact layer 21 or extend into the first contact layer 21. Correspondingly, disposing a second contact layer 31 on a side that is of the drain 3 and that faces the channel region B is equivalent to implementing a connection between the drain 3 and the channel layer 5 by using the second contact layer 31, and an end that is of the carbon nanotube 6 embedded in the channel layer 5 and that faces the drain 3 may be in contact with the second contact layer 31 or extend into the second contact layer 31.

[0062] The first contact layer 21 and the second contact layer 31 herein are equivalent to a contact medium between the source 2, the drain 3, and the carbon nanotube 6. Conductivity of the first contact layer 21 is higher than conductivity of the source 2, and conductivity of the second contact layer 31 is higher than conductivity of the drain 3. Therefore, the first contact layer 21 and the second contact layer 31 can improve conductivity between the source 2 and the carbon nanotube 6, and conductivity between the drain 3 and the carbon nanotube 6.

[0063] Specifically, a material of the first contact layer 21 may be gold or a gold alloy, and the gold alloy may be an alloy doped with copper or cobalt. Such a material is selected because the gold or the gold alloy has high conductivity in terms of electrical contact. In addition, the gold or gold alloy has good ductility in terms of preparation, facilitates process preparation, and has good contact. Similarly, a material of the second contact layer 31 may be also gold or a gold alloy.

[0064] A structure of the field effect transistor shown in FIG. 2b is used as an example. The substrate structure 1 may be specifically shown in FIG. 2c. The substrate structure 1 includes a silicon substrate 11 and a well region 12 formed on the silicon substrate 11. The silicon substrate 11 is located at a bottommost layer of the entire field effect transistor structure, to provide bearing and support for the entire field effect transistor, and also protect the structure of the field effect transistor. The well region 12 may be a P well or an N well. It should be understood that, when the well region 12 is the P well, the source 2 and the drain 3 should be N-type doped structures; or when the well region 12 is the N well, the source 2 and the drain 3 should be P-type doped structures. FIG. 2b illustrates a structure in which the well region 12 is the P well, and the source 2 and the drain 3 are the N-type doped structures.

[0065] Based on the structure of the field effect transistor shown in FIG. 2c, FIG. 2d shows a structure of another field effect transistor. A difference from the structure of the field effect transistor shown in FIG. 2c lies in that an SOI (silicon-on-insulator, silicon technology) is used to form an insulation layer 13 on a surface that is of the well region 12 and that is away from the silicon substrate 11, and the insulation layer 13 may be SiO.sub.2. Both the source 2 and the drain 3 are disposed on the insulation layer 13. The insulation layer 13 can reduce a parasitic capacitance between the source 2, the drain 3 and the well region 12, thereby achieving an anti-leakage effect.

[0066] In the field effect transistor shown in FIG. 2e, in a direction from the gate 4 to the channel layer 5, a capacitive layer 41 and a gate dielectric layer 42 are stacked between the gate 4 and the channel layer 5, the capacitive layer 41 is in contact with the gate 4, and the gate dielectric layer 42 is in contact with the channel layer 5.

[0067] Based on the structure of the field effect transistor shown in FIG. 2e, an embodiment of this application further provides a field effect transistor. As shown in FIG. 2f, a surface of a structure including the gate 4, the capacitive layer 41, and the gate dielectric layer 42 is covered with a first protective layer 43, and the first protective layer 43 may be nitride.

[0068] It should be noted that, in the field effect transistor shown in FIG. 2a to FIG. 2f, the silicon substrate 11, the well region 12, and the insulation layer 13 are referred to as the substrate structure 1 as an entire structure, and are divided only by using positions of the structures in the field effect transistor structure. The concept of the substrate structure 1 is merely used to describe positions for disposing the silicon substrate 11, the well region 12, and the insulation layer 13. It is not used to limit a specific function of the three-layer structure. It should be understood that, based on understanding of the substrate structure 1, the substrate structure 1 may further include another structure in which the field effect transistor is located in a part of the substrate structure 1 and that is not shown in this embodiment of this application.

[0069] A distribution manner shown in FIG. 3a is used as an example of the plurality of carbon nanotubes 6. In FIG. 3a, there are six carbon nanotubes 6, and the carbon nanotubes 6 are divided into an upper layer and a lower layer in a Y direction. A distance between the two layers of carbon nanotubes 6 is C1 (using an axis of the carbon nanotube 6 as a reference). In a Z direction, three carbon nanotubes 6 on the upper layer are disposed side by side, a distance between any two adjacent carbon nanotubes 6 is C2 (using the axis of the carbon nanotube 6 as the reference), three carbon nanotubes 6 on the lower layer are disposed side by side, and a distance between any two adjacent carbon nanotubes 6 is also C2 (using the axis of the carbon nanotube 6 as the reference). C1 may be equal to C2, or C1 may be unequal to C2. In this distribution, it is set that the direction Y is a column direction, and the direction Z is a row direction. In FIG. 3a, the carbon nanotubes 6 are aligned left and right in the row direction, and are aligned up and down in the column direction. In addition, in the row direction, a distance between any two carbon nanotubes 6 is equal.

[0070] FIG. 3b shows another possible distribution manner of carbon nanotubes 6. There are five carbon nanotubes 6, which are divided into an upper layer and a lower layer in a Y direction. A distance between the two layers of carbon nanotubes 6 is D1 (using an axis of the carbon nanotube 6 as a reference). In a Z direction, three carbon nanotubes 6 on the upper layer are disposed side by side, a distance between any two adjacent carbon nanotubes 6 is D2 (using the axis of the carbon nanotube 6 as the reference), two carbon nanotubes 6 on the lower layer are disposed side by side, and a distance between any two adjacent carbon nanotubes 6 is also D2 (using the axis of the carbon nanotube 6 as the reference). D1 may be equal to D2, or D1 may be unequal to D2. In this distribution, it is set that the direction Y is a column direction, and the direction Z is a row direction. In FIG. 3b, the carbon nanotubes 6 are aligned left and right in the row direction, and are mutually misaligned in the column direction. In addition, in the row direction, a distance between any two carbon nanotubes 6 is equal.

[0071] FIG. 3c shows still another possible distribution manner of carbon nanotubes 6. There are five carbon nanotubes 6, which are divided into an upper layer and a lower layer in a Y direction. A distance between the two layers of carbon nanotubes 6 is E1 (using an axis of the carbon nanotube 6 as a reference). In a Z direction, three carbon nanotubes 6 on the upper layer are disposed side by side, a distance between a first carbon nanotube 6 and a second carbon nanotube 6 from the left is E2 (using the axis of the carbon nanotube 6 as the reference), and a distance between the second carbon nanotube 6 and a third carbon nanotube 6 from the left is E3 (using the axis of the carbon nanotube 6 as a reference). Two carbon nanotubes 6 at the lower layer are disposed side by side, and a distance between the two carbon nanotubes 6 is E4 (using the axis of the carbon nanotube 6 as the reference). In this distribution, it is set that the direction Y is a column direction, and the direction Z is a row direction. In FIG. 3c, the carbon nanotubes 6 are aligned left and right in the row direction, and are mutually misaligned in the column direction. In addition, in the row direction, a distance between any two carbon nanotubes 6 is unequal.

[0072] FIG. 3d shows yet another possible distribution manner of carbon nanotubes 6. There are five carbon nanotubes 6, and in a Y direction or a Z direction, the carbon nanotubes 6 have no specific arrangement rule using an axis of the carbon nanotube 6 as a reference. In this distribution, the direction Y is set as a column direction, Z is set as a row direction, and the carbon nanotubes 6 in FIG. 3d are mutually misaligned.

[0073] It should be understood that FIG. 3a to FIG. 3d show several possible distribution manners of carbon nanotubes 6 in the channel layer 5. A same point lies in that in each manner, a plurality of carbon nanotubes 6 are parallel to each other, that is, axis directions of all carbon nanotubes 6 are parallel to the X direction (a direction from the source 2 to the drain 3 or a direction from the drain 3 to the source 2). However, it should be noted that the carbon nanotubes 6 shown in FIG. 3a and FIG. 3b are distributed in an array, and in preparation of the carbon nanotubes 6, the carbon nanotubes 6 may be prepared in batch, thereby reducing complexity of a preparation process. However, the distribution manners of the carbon nanotubes 6 shown in FIG. 3c and FIG. 3d are irregular, and a relatively complex preparation process may be needed in preparation of the carbon nanotubes 6.

[0074] In the foregoing field effect transistor structure, electron conduction is implemented between the source 2 and the drain 3 by using the carbon nanotube 6, so that the field effect transistor has a wider channel. In other words, the field effect transistor has stronger performance and a larger drive current. Herein, the carbon nanotube 6 is in a shape of a tiny cylinder formed by arranging carbon atoms, which facilitates component miniaturization.

[0075] The distribution status of the carbon nanotubes 6 shown in FIG. 3a in the channel layer 5 is used as an example. A structure of the channel layer 5 may be specifically shown in FIG. 4. The channel layer 5 includes at least one channel interlayer 51. For carbon nanotubes 6 distributed in an array in FIG. 3a, in the X direction, one channel interlayer 51 corresponds to one layer of carbon nanotubes 6, that is, in one channel interlayer 51, a layer of carbon nanotubes 6 distributed side by side is formed.

[0076] For a structure of each channel interlayer 51, refer to FIG. 5. In a direction from the substrate structure 1 to the channel layer 5, the channel interlayer 51 includes a first oxide layer 511 and a second oxide layer 512 that are disposed opposite to each other. Herein, the first oxide layer 511 is closer to the substrate structure 1, and the second oxide layer 512 is closer to the gate 4. At least one first recess al may be formed on a surface that is of the first oxide layer 511 and that faces the second oxide layer 512. Correspondingly, second recesses a2 that are in a one-to-one correspondence to the first recesses al are formed on a surface that is of the second oxide layer 512 and that faces the first oxide layer 511. Each group of first recesses al and second recesses a2 that correspond to each other are matched to clamp one carbon nanotube 6. In FIG. 5, a row of parallel carbon nanotubes 6 is embedded in the channel interlayer 51. Therefore, a quantity of first recesses al and a quantity of second recesses a2 match a quantity of carbon nanotubes 6.

[0077] It should be understood that a structural state shown by the first oxide layer 511 and the second oxide layer 512 shown in FIG. 5 is a state finally presented by the field effect transistor, and is not used to limit a structural state of the channel layer 5 in a production and preparation process. In other words, the first recess al and the second recess a2 may not exist in the preparation process, and are presented only after the first oxide layer 511 and the second oxide layer 512 clamp the carbon nanotube 6.

[0078] In a possible implementation, a material of the first oxide layer 511 and the second oxide layer 512 herein may be SiO.sub.2. In actual production and preparation, the carbon nanotube 6 may be formed at the first recess al on the first oxide layer 511, and then the second oxide layer 512 is disposed on a side that is of the carbon nanotube 6 and that is away from the first oxide layer 511, so that the second oxide layer 512 covers the carbon nanotube 6. The first oxide layer 511 and the second oxide layer 512 surround the carbon nanotube 6 to obtain a structure as shown in FIG. 5.

[0079] It should be further noted that, in FIG. 5, the first oxide layer 511 and the second oxide layer 512 are shown in a relatively regular structure (similar to a cube). In actual production and preparation, the first oxide layer 511 and the second oxide layer 512 may be in an irregular state, and structures of the first oxide layer 511 and the second oxide layer 512 are related to one layer of carbon nanotubes 6 whose axes are on a same plane. Therefore, the structure of the finally obtained channel layer 5 only needs to match the structure of the channel region B between the source 2 and the drain 3.

[0080] In a specific structure, as shown in FIG. 6a, a metal silicate compound 71 is formed on a surface that is of the first recess al on the first oxide layer 511 and that faces the carbon nanotube 6. The metal silicate compound 71 herein may be distributed on the surface of the first recess al in a form of a film layer, that is, the carbon nanotube 6 is formed on the metal silicate compound 71, and in other words, the carbon nanotube 6 is surrounded by the metal silicate compound 71 and the second oxide layer 512. In another specific structure, as shown in FIG. 6b, a metal oxide 72 is formed on a surface that is of the first recess al on the first oxide layer 511 and that faces the carbon nanotube 6. The metal oxide 72 herein may be distributed on the surface of the first recess al in a form of a film layer, that is, the carbon nanotube 6 is formed on the metal oxide 72, and in other words, the carbon nanotube 6 is surrounded by the metal oxide 72 and the second oxide layer 512. Both the metal silicate compound 71 and the metal oxide 72 herein facilitate formation of the carbon nanotube 6.

[0081] It may be understood that, when the metal silicate compound 71 or the metal oxide 72 covers the surface that is of the first recess al and that faces the carbon nanotube 6 as shown in FIG. 6a or FIG. 6b, formation of the carbon nanotube 6 is facilitated.

[0082] Based on the structure of the field effect transistor shown in FIG. 2d, this application further provides a semiconductor structure. As shown in FIG. 7, the semiconductor structure includes two field effect transistors (which are respectively shown by using a field effect transistor M1 and a field effect transistor M2). The two field effect transistors share one silicon substrate 11, and other structures of the two field effect transistors are separately disposed. Specifically, as shown in FIG. 7, the field effect transistor M1 includes a P well 12a formed on the silicon substrate 11. An insulation layer 13a is formed on a side that is of the P well 12a and that is away from the silicon substrate 11. An N-type source 2a and an N-type drain 3a of the field effect transistor M1 are disposed on the insulation layer 13a. A channel layer 5a is disposed between the source 2a and the drain 3a. N carbon nanotubes 6a (N is an integer greater than or equal to 1, and N is greater than 1 in FIG. 7) distributed in parallel are embedded in the channel layer 5a. A first contact layer 21a is disposed between the channel layer 5a and the source 2a, and a second contact layer 31a is disposed between the channel layer 5a and the drain 3a. Two ends of the carbon nanotube 6a are respectively connected to the first contact layer 21a and the second contact layer 31a, to implement electron conduction between the source 2a and the drain 3a. Correspondingly, the field effect transistor M2 includes an N well 12b formed on the silicon substrate 11. An insulation layer 13b is formed on a side that is of the N well 12b and that is away from the silicon substrate 11. A P-type source 2b and a P-type drain 3b of the field effect transistor M2 are disposed on the insulation layer 13b. A trench layer 5b is disposed between the source 2b and the drain 3b. N carbon nanotubes 6b (N is an integer greater than or equal to 1, and N is greater than 1 in FIG. 7) distributed in parallel are embedded in the channel layer 5b. A first contact layer 21b is disposed between the channel layer 5b and the source 2b, and a second contact layer 31b is disposed between the channel layer 5b and the drain 3b. Two ends of the carbon nanotube 6b are respectively connected to the first contact layer 21b and the second contact layer 31b, to implement electron conduction between the source 2b and the drain 3b.

[0083] Still refer to FIG. 7. The two field effect transistors are isolated by using shallow trench isolation (STI, shallow trench isolation), that is, a spaced trench is formed between the two field effect transistors, the trench is filled with an isolator through deposition to form an isolation part 8, and a second protective layer 9 is further formed on the isolation part 8.

[0084] The structure of the field effect transistor shown in FIG. 2a is used as an example. An embodiment of this application further provides a preparation method for a field effect transistor. For a specific preparation procedure of the field effect transistor, refer to FIG. 8. The method includes the following steps.

[0085] S1: Prepare a substrate structure 1, where it should be understood that the substrate structure 1 herein is merely used as an example of a bottom structure of the field effect transistor.

[0086] S2: Prepare a channel layer 5 on the substrate structure 1, where N carbon nanotubes 6 extending in a first direction are embedded in the channel layer 5, and N is an integer greater than or equal to 1; and expose two ends of the carbon nanotube 6 from the channel layer 5, where it should be understood that, that two ends of the carbon nanotube 6 are exposed from the channel layer 5 herein means that the ends of the carbon nanotube 6 are not covered by the channel layer 5 at least, and the ends of the carbon nanotube 6 may be flush with a surface of the channel layer 5, or the carbon nanotube 6 protrudes from the surface of the channel layer 5.

[0087] S3: Form a gate 4 on the channel layer 5.

[0088] S4: Form a source 2 and a drain 3 respectively on two sides of the channel layer 5 in the first direction, where the source 2 and the drain 3 are respectively connected to the two ends of the carbon nanotube 6 to form a conductive path, so as to implement current conduction between the source 2 and the drain 3.

[0089] When the substrate structure 1 herein includes a silicon substrate 11 and a well region 12, and the well region 12 is formed by doping an impurity on the silicon substrate 11, step S1 is specifically shown in FIG. 9, and includes the following step.

[0090] S11: Dope an impurity on the silicon substrate 11 to form a well region 12. When the well region 12 herein is a P well, a trivalent element (for example, boron) is doped on the silicon substrate 11 to form a P well; and when the well region 12 herein is an N well, a pentavalent element (for example, phosphorus) is doped on the silicon substrate 11 to form the N well.

[0091] When the substrate structure 1 further includes an insulation layer 13 formed on the side that is of the well region 12 and that is away from the silicon substrate 11, after the foregoing step S11, the following step is further included.

[0092] S12: Form the insulation layer 13 on a side that is of the well region 12 and that is away from the silicon substrate 11.

[0093] According to the distribution manners of the carbon nanotubes 6 in the channel layer 5 shown in FIG. 3a to FIG. 3d, structures of the channel layer 5 and the carbon nanotubes 6 may be divided for layer-by-layer structure preparation by using one channel interlayer 51 as a unit. For each channel interlayer 51, at least one carbon nanotube 6 is embedded in the channel interlayer 51. When a quantity of carbon nanotubes 6 is greater than or equal to two, all the carbon nanotubes 6 are parallel, and axes of the carbon nanotubes 6 are located on a same plane.

[0094] Based on this, the structure shown in FIG. 4 is used as an example. Refer to FIG. 10. The preparing a channel layer 5 on the substrate structure 1 in step S2 includes the following steps performed at least once.

[0095] S21: Form a first oxide layer 511 on a base material, where the base material herein is a structure used by the substrate structure 1 to form a side of the channel layer 5, when the channel interlayer 51 is a first channel interlayer 51 in contact with the substrate structure 1, the base material herein refers to the substrate structure 1, and when the channel interlayer 51 refers to a channel interlayer 51 above another channel interlayer 51, the base material herein refers to the previously formed channel interlayer 51.

[0096] S22: Form at least one carbon nanotube 6 on the first oxide layer 511, where when a quantity of carbon nanotubes 6 is greater than or equal to 2, the carbon nanotubes 6 are parallel to each other. It should be understood that the first recess al shown in FIG. 5 is formed on the first oxide layer 511, and the carbon nanotube 6 is formed at the first recess a1.

[0097] S23: Form a second oxide layer 512 on a surface of the carbon nanotube 6 to cover the carbon nanotube 6, so as to finally obtain the channel interlayer 51, shown in FIG. 5, in which one layer of carbon nanotubes 6 on the same plane is embedded.

[0098] It may be understood that the first oxide layer 511 and the second oxide layer 512 herein have at least the following several possible implementations.

[0099] Implementation 1: The first oxide layer 511 may be SiO.sub.2 and the second oxide layer 512 may also be SiO.sub.2, and the carbon nanotube 6 may be directly formed on the first oxide layer 511.

[0100] Implementation 2: The first oxide layer 511 may be SiO.sub.2, a metal silicate compound 71 is formed at a location at which the first oxide layer 511 is used to form the carbon nanotube 6, and the carbon nanotube 6 is formed on the metal silicate compound 71. Based on this, as shown in FIG. 11, after step S21 and before step S23, the method may further include the following step.

[0101] S211: Prepare a metal oxide on the first oxide layer 511, so that the metal oxide reacts with the first oxide layer 511 to form the metal silicate compound 71. When the first oxide layer 511 is SiO.sub.2, the metal oxide may be Al.sub.2O.sub.3. Herein, Al.sub.2O.sub.3 may be specifically injected into SiO.sub.2 by sputtering. Al.sub.2O.sub.3 reacts with SiO.sub.2 to form a metal silicate compound Al.sub.2SiO.sub.5 or Al.sub.2O.sub.3. SiO.sub.2 with a thickness level of nm.

[0102] Based on this, as shown in FIG. 11, the forming at least one carbon nanotube 6 on the first oxide layer 511 in step S22 may be specifically implemented in the following step.

[0103] S221: Under the action of a catalyst, synthesize the carbon nanotube 6 on the metal silicate compound 71 by using a vapor deposition method, where the catalyst herein may be tungsten-based alloy nanocrystalline, and the specific process is as follows: By using a cluster molecule of a carbon-philic metal (for example, a metal containing tungsten) and another transition metal element as a start material on the metal silicate compound 71, prepare a tungsten-based alloy nanocrystalline catalyst under a relatively mild condition, and then synthesize the carbon nanotube 6 by alcohol chemical vapor deposition.

[0104] Implementation 3: The first oxide layer 511 may be SiO.sub.2, a metal oxide 72 is formed at a location at which the first oxide layer 511 is used to form the carbon nanotube 6, and the carbon nanotube 6 is formed on the metal oxide 72. Based on this, as shown in FIG. 12, after step S21 and before step S23, the method may further include the following step.

[0105] S212: Add metal to the first oxide layer 511 to form the metal oxide 72. Herein, a metal adding process may use evaporation and photoetching. When the metal is Al, Al is added to the first oxide layer 511 by evaporation and photoetching, and Al may be naturally oxidized in air to form the metal oxide 72 (Al.sub.2O.sub.3) with a thickness level of nm.

[0106] Based on this, as shown in FIG. 12, the forming at least one carbon nanotube 6 on the first oxide layer 511 in step S22 may be specifically implemented in step S222.

[0107] S222: Prepare the carbon nanotube 6 by using laser ablation.

[0108] Based on the structure of the field effect transistor shown in FIG. 2b, after step S2 and before step S3, as shown in FIG. 13, the method further includes the following step.

[0109] S2′: Deposit high-conductivity metal on the two sides of the channel layer 5 to form a first contact layer 21 and a second contact layer 31 on the two sides of the channel layer 5, where one end of the carbon nanotube 6 is electrically connected to the source 2 through the first contact layer 21, and the other end of the carbon nanotube 6 is electrically connected to the drain 3 through the second contact layer 31. Herein, a process of depositing high-conductivity metal on two sides (refer to two sides in a first direction) of the channel layer 5 may use electron beam lithography. It should be understood that the first contact layer 21 and the second contact layer 31 may be prepared separately or simultaneously according to a specific process during production.

[0110] Based on step S2′, during specific implementation of step S4 in FIG. 13, the source 2 is connected to one end of the carbon nanotube 6 through the first contact layer 21, and the drain 3 is connected to the other end of the carbon nanotube 6 through the second contact layer 31, so as to implement a circuit connection between the source 2, the carbon nanotube 6, and the drain 3 to form a conductive path.

[0111] When the capacitive layer 41 and the gate dielectric layer 42 are further stacked between the gate 4 and the channel layer 5 of the field effect transistor, as shown in FIG. 14, the foregoing step S3 includes the following steps.

[0112] S31: Prepare the gate dielectric layer 42 on the channel layer.

[0113] S32: Prepare the capacitive layer 41 on the gate dielectric layer 42.

[0114] S31: Prepare the gate 4 on the capacitive layer 41.

[0115] It should be understood that a first protective layer 43 may be further covered on a surface of a structure including the gate 4, the capacitive layer 41, and the gate dielectric layer 42, to protect the structure.

[0116] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.