Methods of Fabricating Integrated Circuit Devices With Components on Both Sides of a Semiconductor Layer and the Devices Formed Thereby

Abstract

A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

Claims

1. A method of making an integrated circuit, the method comprising: providing a first substrate comprising a carrier substrate, a buried insulating layer, and semiconductor layer above a buried insulating layer, the buried insulating layer being above a carrier substrate, the first substrate having a first side and an opposite second side, the semiconductor layer having a first semiconductor layer side and a second semiconductor layer side; from the first semiconductor layer side, forming a first waveguide in the semiconductor layer; forming a first insulating layer over the first side of the substrate; forming a metallization level comprising a metal line within the first insulating layer; attaching a second substrate over the first insulating layer; flipping the first substrate after the attaching; from the second side of the first substrate, removing the carrier substrate and the buried insulating layer; forming a laser source over the second semiconductor layer side of the semiconductor layer, the laser source being formed directly over the first waveguide; and encapsulating the laser source in a second insulating layer, wherein the integrated circuit comprising the first waveguide and the laser source forms part of a photonic integrated circuit.

2. The method of claim 1, wherein forming the laser source comprises: depositing a n-type semiconductor layer stack over the second insulating layer; depositing a quantum well layer stack over the n-type semiconductor layer stack; depositing a p-type semiconductor layer stack over the quantum well layer stack; and patterning the p-type semiconductor layer stack, the quantum well layer stack, and the n-type semiconductor layer stack.

3. The method of claim 2, wherein forming the laser source comprises: forming a first eutectic deposit on the patterned p-type semiconductor layer stack; and forming a second eutectic deposit on the patterned n-type semiconductor layer stack.

4. The method of claim 3, further comprising: forming contacts to the first eutectic deposit and the second eutectic deposit, the contacts being formed in the second insulating layer.

5. The method of claim 1, further comprising: depositing a third insulating layer before forming the second insulating layer, the third insulating layer contacting the exposed major surface of the semiconductor layer; depositing an amorphous silicon layer over the third insulating layer; and patterning the amorphous silicon layer to form a second waveguide directly above the first waveguide.

6. The method of claim 1, further comprising: forming a grating coupler in the semiconductor layer, the grating coupler being proximate to the first waveguide.

7. The method of claim 6, further comprising forming a mirror in the first insulating layer, the mirror being directly formed over the grating coupler.

8. The method according to claim 7, aligning the grating coupler with the mirror so that light via the semiconductor layer is divided in the grating coupler into a first beam that crosses the second insulating layer toward an optical fiber interface at an exposed surface of the second insulating layer and into a second beam toward the mirror and reflected toward the optical fiber interface.

9. The method according to claim 6, further comprising forming a modulator in the semiconductor layer, the modulator being proximate the grating coupler.

10. A method of making an integrated circuit, comprising: providing a substrate comprising a carrier substrate, a buried insulating layer, and a semiconductor layer above a buried insulating layer, the buried insulating layer being above a carrier substrate, the semiconductor layer having a first side and an opposite second side contacting the buried insulating layer; forming a grating coupler in the semiconductor layer; forming a first insulating layer over the first side of the semiconductor layer; forming a mirror in the first insulating layer, the mirror overlapping with the grating coupler; after forming the mirror, removing the carrier substrate and the buried insulating layer to expose the second side of the semiconductor layer; and after removing the carrier substrate and the buried insulating layer, forming a second insulating layer to cover the exposed second side of the semiconductor layer, wherein the integrated circuit comprising the grating coupler and the mirror forms part of a photonic integrated circuit.

11. The method according to claim 10, wherein the semiconductor layer comprises a silicon layer.

12. The method according to claim 10, further comprising forming a laser source in the second insulating layer.

13. The method according to claim 12, wherein forming the laser source comprises: forming a patterned semiconductor heterostructure over the second insulating layer; and depositing an encapsulant material surrounding the patterned semiconductor heterostructure.

14. The method according to claim 13, further comprising forming a first waveguide, directly under the laser source, in the semiconductor layer, the grating coupler being disposed proximate to the first waveguide.

15. The method according to claim 14, wherein forming the laser source further comprises, prior to forming of the patterned semiconductor heterostructure, forming a second waveguide in the second insulating layer, the second waveguide being formed directly over the first waveguide.

16. The method according to claim 15, wherein forming the second waveguide comprises: depositing a third insulating layer contacting the first side of the semiconductor layer; depositing an amorphous semiconductor layer over the third insulating layer; etching the amorphous semiconductor layer to form a patterned amorphous semiconductor layer; and depositing the second insulating layer above the third insulating layer.

17. The method according to claim 10, wherein the mirror is formed while forming metal lines in the first insulating layer.

18. The method according to claim 10, aligning the grating coupler with the mirror so that light via the semiconductor layer is divided in the grating coupler into a first beam that crosses the second insulating layer toward an optical fiber interface at an exposed surface of the second insulating layer and into a second beam toward the mirror and reflected toward the optical fiber interface.

19. The method according to claim 10, further comprising forming a modulator in the semiconductor layer, the modulator being proximate the grating coupler.

20. A method of operating an integrated circuit, the method comprising: generating light from a laser source disposed within an encapsulating material, the encapsulating material having an first major surface and a second major surface; directing the light towards a first waveguide disposed directly under the laser source, the first waveguide disposed in a semiconductor layer having a first side and an opposite second side, the first major surface facing towards the semiconductor layer and the second major surface facing away from the semiconductor layer; and using a grating coupler in the semiconductor layer, splitting the light into a first beam directed towards an optical fiber interface at the second major surface of the encapsulating material and into a second beam towards a mirror disposed in an insulating layer comprising metallization, wherein the mirror is configured to reflect the second beam towards the optical fiber interface.

21. An integrated circuit comprising: a semiconductor layer comprising a first side and a second side; a first waveguide disposed in the semiconductor layer; an encapsulating material disposed over the first side of the semiconductor layer; a laser source disposed in the encapsulating material; and an insulating layer disposed under the second side of the semiconductor layer, wherein the semiconductor layer is disposed between the encapsulating material and the insulating layer, wherein the integrated circuit comprises no other semiconductor substrate between the encapsulating material and the insulating layer, wherein the integrated circuit comprising the first waveguide and the laser source forms part of a photonic integrated circuit.

22. An integrated circuit comprising: a semiconductor layer comprising a first side and a second side; a grating coupler disposed in the semiconductor layer; an encapsulating material disposed over the first side of the semiconductor layer; an insulating layer disposed under the second side of the semiconductor layer, wherein the semiconductor layer is disposed between the encapsulating material and the insulating layer, wherein the integrated circuit comprises no other semiconductor substrate between the encapsulating material and the insulating layer; and a mirror disposed in the insulating layer, the mirror overlapping with the grating coupler, wherein the integrated circuit comprising the grating coupler and the mirror forms part of a photonic integrated circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 is a schematic cross-sectional view of a photonic integrated structure preparatory to obtaining of a photonic integrated circuit in accordance with an embodiment of the present invention.

[0022] FIG. 2 is a schematic cross-sectional view of the photonic integrated structure of FIG. 1 after bonding of a handle substrate.

[0023] FIG. 3 is a schematic cross-sectional view of the photonic integrated structure of FIG. 2 after removal of the carrier substrate of said structure.

[0024] FIG. 4 is a schematic cross-sectional view of the photonic integrated structure of FIG. 3 after etching of the insulating layer.

[0025] FIG. 5 is a schematic cross-sectional view of the photonic integrated structure of FIG. 4 including an additional waveguide above the waveguide.

[0026] FIG. 6 is a schematic cross-sectional view of the photonic integrated structure of FIG. 5 after III-V wafer bonding.

[0027] FIG. 7 is a schematic cross-sectional view of the photonic integrated structure of FIG. 6 after selective chemical etching of the substrate of the wafer and III-V laser patterning and etching.

[0028] FIG. 8 is a schematic cross-sectional view of a photonic integrated circuit in accordance with an embodiment of the present invention.

[0029] FIG. 9 is a schematic cross-sectional view of a photonic integrated circuit in accordance with another embodiment of the present invention.

[0030] FIG. 10 is a schematic cross-sectional view of an integrated circuit in accordance with the prior art.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0031] In FIG. 1, the reference SB denotes a Silicon-On-Insulator (SOI) wafer. The SOI substrate includes a semiconductor layer or film, and more particularly, a silicon layer or film 1 having, in this embodiment, a thickness of about 300 nanometers, arranged above a buried insulating layer 2, commonly denoted BOX (Buried Oxide) by those skilled in the art. This buried insulating layer 2 is itself arranged above a carrier substrate 3.

[0032] Various photonic components are produced in this silicon layer 1, for example, a waveguide GO arranged in a part 10 of this layer, a grating coupler 11, another waveguide 12, a modulator 13 and a photodetector 14.

[0033] Although any kind of optical modulator may be used, the modulator 13 may be an electro-optical modulator, for example a Mach-Zehnder modulator having an architecture well known by the man skilled in the art and including a phase shifter (also called phase modulator) in each of the two branches of the Mach-Zehnder modulator, both phase shifters being controlled in phase opposition. For simplicity reasons only one of those phase shifters of the modulator 13 is illustrated in the figures.

[0034] Of course, FIG. 1 shows a variety of photonic components that can be produced in the silicon layer without this list being exhaustive. Of course, it may be possible for only some of these components to be produced, depending on the desired applications. These various photonic components are mutually separated by an insulating region 100, silicon dioxide for example.

[0035] It should be noted that if the laser source to be produced is a DBR laser, the part 10 of the silicon layer also incorporates Bragg mirrors optically coupled to the waveguide GO and which are to be situated on the periphery of the III-V gain medium of the laser source.

[0036] This silicon layer 1 has a first side F1, or front side, and a second side F2 or back side, that is arranged above the buried insulating layer 2. In a conventional way known per se, the process for producing each photonic integrated circuit of the wafer includes producing several metallization levels, here four levels M1, M2, M3, M4 embedded in a first insulating region 4. The insulating material forming this first insulating region is commonly denoted as the intermetal dielectric (IMD) by those skilled in the art. This production may be conventionally based on deposition and chemical-mechanical polishing (CMP) of dielectrics (oxide) and metals (copper).

[0037] The tracks produced in these metallization layers can, at least in some cases, be connected by vias V. These metallization levels are typically used to interconnect components and to connect them to external contact pads. The height of the interconnect region RITX is typically about 3 microns.

[0038] Simultaneously with the production of the tracks of the first metallization level M1, a metal mirror 5 may be advantageously produced opposite the relief surface of the grating coupler 11. Next, a substrate 6 acting as a handle is bonded (FIG. 2) to the upper side of the insulating region 4.

[0039] After the structure has been flipped, the carrier substrate 3 is removed, as illustrated in FIG. 3, typically by grinding. As illustrated in FIG. 4, the insulating (BOX) layer 2 is etched to uncover the second side F2 of the silicon layer, i.e. the back side. It is from this back side that the processing for producing the laser source will be carried out.

[0040] This being so, generally, no processing is carried out on bare silicon. This is the reason why, before carrying out further processing, the silicon layer is covered with an additional insulating layer 70, commonly denoted the PADOX by those skilled in the art.

[0041] As a variant, when the buried insulating layer 2 includes a stack that includes a PADOX layer topped by a silicon layer nitride topped by a layer of TEOS oxide, the etching of the layer 2 is carried out as far as the PADOX layer 70, which may make it possible to avoid consuming the silicon dioxide of the regions 100. In this case, the side F2 of the silicon layer is approached and thus it may not be desirable to reform the PADOX layer 70. The thickness of this PADOX layer is typically about 100 nanometers.

[0042] Next, as illustrated in FIG. 5, an additional waveguide 71 is produced above the waveguide GO of the interconnect part 10. This waveguide 71 may be for the future laser source that is here assumed to be a DFB laser.

[0043] In this respect, wafer-scale deposition of an amorphous silicon layer is carried out on the additional insulating layer 70, which layer is etched so as to form the additional waveguide 71. In the event of the future laser source being a DFB laser, the additional means 71 or additional waveguide also incorporate Bragg mirrors optically coupled to the additional waveguide to contribute to the formation of the cavity resonator. In this respect, a double etching of the amorphous silicon layer is carried out to form the additional waveguide, then the Bragg mirrors.

[0044] Next, an additional insulating layer 72, for example made of silicon dioxide, is deposited on the additional means 71 and on the additional insulating layer 70 (PADOX), and a chemical-mechanical polishing is then carried out on the additional insulating layer 72. The thickness of the additional means 71 is typically about 200 nanometers, whereas the thickness of the additional insulating layer 72 is less than or equal to 100 nanometers.

[0045] The stack 7 thus produced and having been polished, is thus ready to receive the active gain medium that amplifies the laser source. Thus, as illustrated in FIG. 6, a heterostructure 8 made of III-V semiconductor material is formed. This formation is carried out by direct bonding of a wafer 8 formed by a III-V heterostructure.

[0046] More precisely, the heterostructure 8 includes a substrate 8o that includes a p-type semiconductor material, InP for example, a stack 81 of layers forming quantum wells, made of InGaAsP for example, and a layer 82 of an n-type material, for example an InP/InGaAs stack.

[0047] The thickness of the heterostructure 8 may typically be about a few hundred microns. The thickness of the stack of quantum wells 81 may be about 300 nm and the thickness of the layer 82 may be about 200 nm.

[0048] As illustrated in FIG. 7, selective chemical etching of the substrate 80 (selective over the active layers 81 and 82) is carried out, followed by lithography and etching adapted to the III-V material to obtain the gain medium 800 of the laser source. Next eutectic deposits 801, 802, 803, based on gold for example, are deposited to allow metal contacts to be made to the etched layer 820 and to the etched layer 830.

[0049] As illustrated in FIG. 8, the structure is encapsulated by depositing another insulating layer above the stack 7 to form a second insulating region 9 above the structure 800 and the stack 7. Conventional production of contacts 910 is carried out to make contact with the eutectic zones 801, 802 and 803, as well as conventional production of other contacts 903 to connect metal tracks to contact pads situated on the back side.

[0050] After the steps of finishing and cutting the wafer to singulate the integrated circuits, a photonic integrated circuit IC is obtained, as illustrated in FIG. 8. The integrated circuit includes a silicon layer 1 that includes a waveguide GO and at least one other photonic component and a first insulating region 4 arranged above a first side F1 of the silicon layer and encapsulating here several metallization levels M1-M4. The integrated circuit also includes a second insulating region 9 above a second side F2 of the silicon layer and encapsulating the gain medium 800 of the laser source SL and, in this embodiment, an additional means 71 or at least one additional waveguide, and possibly also Bragg mirrors. This laser source is optically coupled to the waveguide GO which is situated in part 10 of the silicon layer 1.

[0051] As a variant, as illustrated in FIG. 9, it may be possible to arrange the additional means 71 of the laser source in the first insulating region 4. The gain medium 800 of the laser source SL is then arranged in the immediate vicinity of the silicon layer 1 and is separated from the second side F2 of the latter by the additional insulating layer 70 (PADOX). In this respect, the additional means 71 are produced prior to the production of the metallization levels M1-M4 of the integrated circuit, again by wafer-scale deposition of a layer of amorphous silicon and etching(s).

[0052] It should also be noted that, whether in the embodiment of FIG. 8 or the embodiment of FIG. 9, the grating coupler 11 turns its relief surface no towards the first insulating region 4 in the direction of the metal mirror 5. The light beam that arrives on the coupler via the silicon layer is subdivided in the coupler 11 into a first beam that crosses the insulating region 9 towards an optical fiber fixed onto the back side FAR of the chip via an optical interface INT for example, and into a second beam that travels towards the metal mirror 5 to be reflected in the direction of the optical fiber. Thus, none of these beams may be perturbed by the nitride layers that are, for example, found in the first insulating region 4. The production of a metal mirror 5 in the first insulating region 4 is generally independent of the integration (or absence of integration) of a hybrid III-V laser source in the IC chip.

[0053] Thus, according to another aspect, a photonic integrated circuit is provided that includes a silicon layer that includes at least one coupler 11, for example a grating coupler, and a first insulating region 4 arranged above a first side F1 of the silicon layer 1 and encapsulating one or more metallization levels. A metal mirror is situated facing the coupler, for example a first metallization layer, and a second insulating layer 9 is situated above a second side F2 of the silicon layer 1, opposite the first side.

[0054] The advantages of such a structure in relation to a prior-art structure, as illustrated in FIG. 10, are now described. In the prior-art structure equipped, for example, with an optical fiber fixed to its front side FAV, when a light beam reaches the coupler 11, it is subdivided into a first beam that crosses the insulating region 4 towards the optical fiber, and into a second beam that moves towards the substrate 3. Thus, there is a loss in the substrate and a perturbation of the first beam by the nitride layers of the first insulating region.

[0055] Thus, according to this other aspect, losses in the substrate and perturbations by the nitride layers as indicated above, are reduced or avoided. It may also be possible, as illustrated in FIG. 9, to incorporate, into the first insulating region 4, a means 150 or a heat-dissipating radiator connected to the silicon layer 1, opposite the gain medium of the laser source. This means or heat-dissipating radiator may be produced by metal tracks and specific vias simultaneously with the production of the metal tracks of the various metallization levels of the interconnect (BEOL) part of the integrated circuit.

[0056] Of course this heat-dissipating radiator can also be provided in the embodiment in FIG. 8. Also, the heat-dissipating radiator may improve the heat dissipation of the integrated circuit.

[0057] As indicated above and illustrated in particular in FIG. 8 or 9, the photonic integrated circuit includes as a photonic component, a modulator 13. As indicated above, although any kind of optical modulator may be used, the modulator illustrated is, for example, a Mach-Zehnder modulator having a structure well-known by the man skilled in the art. Only one phase shifter of the Mach-Zehnder modulator is represented for ease of understanding.

[0058] In integrated circuits of the prior art, such as the one illustrated in FIG. 10, having an SOI substrate including the silicon layer or film 1 arranged above the buried insulating layer (BOX) 2 itself arranged above the carrier substrate 3, the modulator 13 is above the carrier substrate. However such a prior structure has drawbacks.

[0059] As a matter of fact if the carrier substrate is a small resistivity (SR) substrate, some resistive and capacitive (RC) parasitic effects occur between the silicon film and the carrier substrate leading to a speed limitation and an increase of power consumption.

[0060] It may be possible to avoid such drawbacks by using a high resistivity (HR) substrate as the carrier substrate. However using such HR-SOI substrates may be relative costly and may lead to processing issues.

[0061] The fabrication method described above leads, with reference to FIGS. 1-9, to a photonic integrated circuit that includes a modulator 13 having, as illustrated in FIG. 8 or 9, without a carrier substrate above the modulator after the structure has been flipped and the carrier substrate 3 removed, as illustrated in FIG. 3, typically by grinding.

[0062] Thus RC parasitic effects are greatly reduced while HR-SOI substrates are no longer needed. For example, a parasitic capacitor reduction of 50% may be obtained versus a prior art structure based on an SR-SOI substrate, and a parasitic capacitor reduction of 33% may be obtained versus a prior art structure based on an HR-SOI substrate.

[0063] Thus according to another embodiment illustrated in FIG. 8 or 9, a photonic integrated circuit is also proposed, that includes a silicon layer 1 that includes a modulator 13 having a relief surface and another surface opposite the relief surface, a first insulating region 4 arranged above a first side F1 of the silicon layer and encapsulating at least one metallization level M1-M4 coupled to the relief surface of the modulator, a second insulating region 9 arranged above a second side F2 of the silicon layer and above the another surface of the modulator, and no other substrate turned towards the another surface of the modulator.

[0064] As illustrated also in FIG. 8 or 9, a photonic integrated circuit is also proposed that includes a substrate (for example the handle substrate 6), a silicon layer 1 including a modulator 13 having a relief surface turned towards the substrate and another surface opposite said relief surface, a first insulating region 4 arranged between a first side F1 of the silicon layer and the substrate and encapsulating at least one metallization level M1-M4 coupled to the relief surface of the modulator, and a second insulating region 9 arranged above a second side F2 of the silicon layer and above the another surface of the modulator.

[0065] Further at least one metallization level M1-M4 may be advantageously used for forming a shield for shielding the modulator from said handle substrate. Of course the integrated circuit may include such a modulator with or without the other photonic components, such as the laser source.