SEMICONDUCTOR WAFER COMPRISING A MONOCRYSTALLINE GROUP-IIIA NITRIDE LAYER

Abstract

Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride.

Claims

1.-16. (canceled) cm 17. A semiconductor wafer, comprising: a monocrystalline silicon substrate wafer having a top surface, the monocrystalline substrate wafer structured to have a multiplicity of tips on its top surface, each of the tips covered, in the order given, with a group-IIIB silicide layer having a thickness of not less than 5 nm, and a group-IIIB nitride layer, and the group-IIIB nitride layer covered with a monocrystalline group-IIIA nitride layer.

18. The semiconductor wafer of claim 17, wherein a contact area between the group-IIIB nitride layer and the monocrystalline group-IIIA nitride layer is not more than 50% of the group-IIIA nitride layer, in the case of a coalesced film.

19. The semiconductor wafer of claim 17, wherein the tips have a height between 100 nm and 50 μm.

20. The semiconductor wafer of claim 17, wherein the tips have a height between at least 3 μm and 50 μm.

21. The semiconductor wafer of claim 17, wherein the tips have a bottom width of between 1 nm and 10 μm.

22. The semiconductor wafer of claim 17, wherein the tips have a center-to-center distance between 100 nm and 10 μm.

23. The semiconductor wafer of claim 17, wherein the tips have a center-to-center distance between 100 nm and at most 3μm.

24. The semiconductor wafer of claim 17, wherein the group-IIIB nitride layer has a (111) surface orientation.

25. The semiconductor wafer of claim 17, wherein the group-IIIB nitride layer comprises either a single layer of ScN or YN, or a double layer of ScN and YN, or a multiple mixed or graded layer of Y.sub.1−xSc.sub.xN with 0≦x≦1.

26. The semiconductor wafer of claim 17, wherein the group-IIIB nitride layer has a (111) surface orientation and comprises either a single layer of ScN or YN, or a double layer of ScN and YN ,or a multiple mixed or graded layer of Y.sub.1−xSc.sub.xN with 0<x≦1.

27. The semiconductor wafer of claim 17, wherein the group-IIIB silicide layer has a (0001) surface orientation.

28. The semiconductor wafer of claim 17, wherein the group-IIIB silicide layer is a Y.sub.1−zSc.sub.zSi.sub.x with 0≦z≦1.

29. The semiconductor wafer of claim 27, wherein the group-IIIB silicide layer is a Y.sub.1−zSc.sub.zSi.sub.x with 0≦z≦1.

30. The semiconductor wafer of claim 17, wherein the monocrystalline group-IIIA nitride layer is a coalesced film or a structured layer.

31. The semiconductor wafer of claim 17, wherein the monocrystalline group-IIIA nitride layer is structured layer comprising an array of rods, blocks, tips or pyramids.

32. The semiconductor wafer of claim 17, wherein the monocrystalline group-IIIA nitride layer is a monocrystalline In.sub.xAl.sub.zGa.sub.1−(x+z)N layer with 0≦x, z, and (x+z)≦1.

33. The semiconductor wafer of claim 17, wherein the monocrystalline group-IIIA nitride layer has a (0001) surface orientation.

34. The semiconductor wafer of claim 17, the monocrystalline substrate wafer is a Si(111) or Si(001) wafer.

35. In a process for producing light emitting elements, field effect transistors, or microstructure printing, the improvement comprising employing a semiconductor wafer of claim 17 in the process as a substrate.

36. A method for producing a semiconductor wafer of claim 17, comprising the steps of: providing a monocrystalline substrate wafer, structuring the substrate wafer to form tips on its top surface, covering the tips with a group-IIIB silicide layer and then a group-IIIB nitride layer, and covering the group-IIIB nitride layer with a monocrystalline group-IIIA nitride layer.

37. The method of claim 36, wherein the step of covering the tips with a group-IIIB silicide layer and then with a group-IIIB nitride layer comprises forming the group-IIIB silicide layer by a silicidation process.

38. The method according to claim 37, wherein the step of covering the tips with a group-IIIB silicide layer and then with a group-IIIB nitride layer comprises depositing a group-IIIB nitride on top of a group-IIIB silicide by in situ nitridation of a group-IIIB silicide surface, or by molecular beam epitaxy.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 schematically shows preferred steps for producing a silicon wafer having silicon nanotips.

[0013] FIG. 2 schematically shows a preferred step for silicidation of silicon nanotips and different possibilities to deposit ScN as group-IIIB nitride on the silicidated nanotips to generate ScN pads.

[0014] FIG. 3 schematically shows a preferred step for depositing a coalesced film as GaN layer on the ScN pads.

[0015] FIG. 4 schematically shows a preferred step for depositing nanorods as GaN layer on the ScN pads.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0016] The semiconductor wafer comprises a monocrystalline substrate wafer consisting essentially of silicon, preferably a Si(111) or Si(001) wafer. The monocrystalline substrate wafer is structured to have numerous monocrystalline silicon tips on its top surface, the monocrystalline silicon tips being separated from each other. Each monocrystalline silicon tip is covered in the given order with a group-IIIB silicide layer and a group-IIIB nitride layer generating group-IIIB nitride pads or a coalesced group-IIIB nitride film, where group-IIIB stands for IUPAC group 3, Scandium family elements, especially Scandium (Sc) and Yttrium (Y). The group-IIIB silicide layer is a closed layer and preferably consists of Y.sub.1-31 zSc.sub.zSi.sub.x with 0≦z≦1. Preferably, the group-IIIB silicide layer has a thickness which is not less than 5 nm. The group-IIIB nitride layer is preferably either a single layer of ScN or YN, or a double layer of YN and ScN (YN/ScN or ScN/YN), or a multiple mixed (of different stoichiometry) or graded layer of Y.sub.1−xSc.sub.xN with 0≦x≦1. Finally, the monocrystalline group-IIIA nitride layer, especially In.sub.xAl.sub.zGa.sub.1−(x+z)N with 0≦x, z, (x+z)≦1 is grown on the group-IIIB nitride pads or film. The group-IIIA nitride layer can be a coalesced film or a structured layer, e.g. an array of (nano−) rods, blocks, tips or pyramids.

[0017] In this invention, the prior art problems are addressed using nanoheteroepitaxy technique (single-crystal growth of one semiconductor on another) by structuring of the substrate wafer in such a way that “nanotips”, i.e. thin needle-like Si structures of, for example, several 1 nm-10 μm bottom wide and 100 nm-50 μm high structures with a certain center-to-center distance (period) (100 nm-10 μm) to each other are created.

[0018] Then, the topmost part of the nanotips is transformed from Si to group-IIIB silicide, preferably ScSi.sub.x or YSi.sub.x, keeping the epitaxial relationship of subsequent layers, followed by the deposition of epitaxial group-IIIB nitride, preferably ScN, especially ScN(111). Finally, group-IIIA nitride is deposited on top of group-IIIB nitride. It is advisable that in case of a coalesced group-IIIA nitride film on group-IIIB nitride pads, the contact area between the group-IIIB nitride pads and the coalesced group-IIIA nitride film is not more than 50% of the coalesced group-IIIA nitride film.

[0019] According to a preferred embodiment of the invention, the thickness of the group-IIIB silicide layer is not more than 50 nm.

[0020] According to a preferred embodiment of the invention, group-IIIB nitride is deposited on top of group-IIIB silicide by in situ nitridation of the group-IIIB silicide surface, preferably ScSi.sub.x or YSi.sub.x surface, especially a ScSi.sub.xl (0001) or YSi.sub.x(0001) surface, or by MBE technique.

[0021] This invention addresses the issue of mechanical strain due to the possibility of the Si nanotips to absorb part of the strain in an elastic manner. Absorption of the strain due to the elastic deformation of the epilayer depends upon the volume of 3D void network inbetween Si and group-IIIA nitride layer. Optimized structure releases the stress and avoids cracking of group-IIIA nitride layer upon cooling down from the deposition temperature.

[0022] This invention addresses the lattice mismatch by the formation of intermediate layers. Preferably, the group-IIIB silicide topping of the Si nanotips is hexagonal Y.sub.1−zSc.sub.zSi.sub.x(0001) with a lattice mismatch to Si(111) of −4.7%. According to a preferred embodiment group-IIIB nitride on top of the group-IIIB silicide topping is epitaxial ScN(111) with a lattice mismatch to GaN of only −0.1% resulting in the suppression of the formation of extended defects like e.g. misfit and threading dislocations which could be detrimental on the operation of a device made out of the deposited group-IIIA nitride layer. In the conventional method of group-IIIA nitride film deposition on Si, SiN formation at Si and nitride film interfaces may cause an epitaxial relationship problem. However, this invention avoids the formation of SiN.

[0023] C. Nörenberger et al., Surf. Sci. 600, 4126 (2006) “Surface structures of scandium silicides grown on Si(111) studied by STM, AFM and electron diffraction” investigated the formation of ScSi on Si(111) at different temperatures and revealed that if scandium silicide layers are grown at 900-920° C., they consist of the hexagonal ScSi.sub.2 with the (110) and (101) faces parallel to the Si(111) surface. In the introduction of this publication it is stated, that a few monolayers of the hexagonal ScSi.sub.2 have also been investigated as a possible interfacial layer when growing ScN on Si(111), which is a promising buffer layer for the growth of GaN on Si(111).

[0024] The inventive semiconductor wafer can advantageously be used as a substrate for producing light emitting elements (laser diode or LED etc.) and field effect transistors (FETs) for high power and high frequency applications. Light extraction efficiency of light emitting structure and the electrical breakdown voltage of the power transistor structure can be improved by fabricating respective structure on top of the inventive semiconductor wafer rather than on the classical GaN on Silicon approach.

[0025] The inventive semiconductor wafer can advantageously also be used for microstructure printing because well defined patches of GaN can be easily transferred by a separation step from the tips to another substrate.

[0026] Further advantages and embodiments of the invention will become apparent from the description and the appended figures.

[0027] It should be noted that the previously mentioned features and the features to be further described in the following are usable not only in the respectively indicated combination, but also in further combinations or taken alone, without departing from the scope of the present invention.

[0028] In the drawings preferred embodiments for producing a semiconductor wafer according to the invention comprising a monocrystalline substrate wafer consisting essentially of silicon and a monocrystalline GaN layer as group-IIIA nitride layer are shown.

[0029] Within the scope of the invention, a Si nanotips approach (for providing flexible seed area and thus opportunity for antiphase domain (APD) free group-IIIA nitride growth on Si by growth from one critical nucleus only) is combined with an innovative layer stack without using the classical AlN/AlGaN/GaN approach.

[0030] According to the preferred embodiment of the invention shown in the figures and explained in more detail below it is build up on Si nanotips a layer stack of: [0031] 1) ScSi.sub.x as a preferred embodiment of Y.sub.1-31 zSc.sub.zSi.sub.x with 0≦z≦1 in turn as a preferred embodiment of group-IIIB silicide: Epitaxial silicidation (an annealing (sintering) process resulting in the formation of metal-Si alloy (silicide)) of the Si nanotips to avoid GaN reaction with Si. [0032] 2) ScN as a preferred embodiment of Y.sub.1−xSc.sub.xN with 0≦x1 in turn as a preferred embodiment of group-IIIB nitride: Epitaxial ScN growth to have zero lattice mismatch growth template [0033] 3) GaN as a preferred embodiment of In.sub.xAl.sub.zGa.sub.1−(x+z)N with 0≦x, z, (x+z)≦1 in turn as a preferred embodiment of group-IIIA nitride: Functional GaN patches e.g. by ELO
so that the resulting preferred heterostructure is given by Si/ScSi.sub.x/ScN/GaN. It is noted that group-IIIB chemistry behaves similar to Al chemistry which provides a good guideline for stability of compounds discussed here.

[0034] Referring to FIG. 1, in a first step, a monocrystalline substrate wafer 1 is provided, which consists essentially of monocrystalline silicon, preferably of 90% to 100% silicon, more preferably of 98% to 100% silicon. The substrate wafer 1 may comprise the usual dopants or impurities generally known in the field of silicon technology. The substrate wafer 1 for instance has a crystal surface orientation of Si(111). The substrate wafer 1 may have a diameter of 100 mm to 450 mm. The surface of the substrate wafer is preferably polished.

[0035] Preferably, the substrate wafer 1 is annealed at high temperature to obtain a high quality silicon surface. The anneal temperature is between 600 and 1250° C. The annealing may be performed in a vacuum or under a reducing atmosphere, preferably comprising hydrogen, for 30 seconds to 30 minutes, preferably from one to ten minutes.

[0036] In a second step, nanotips 2 are formed on the upper surface of the silicon substrate layer 1. In the prior art, different techniques for forming nanotips are known, e.g. by defining the tips by photo lithography and removing Si by chemical and/or mechanical processes, e.g. etching, especially anisotropic wet etching. A height H, a width at the base W and a period P of the nanotips can be controlled by the lithography and etching process.

[0037] The height H advantageously is in the range of 100 nm-50 μm, the width W at the base of a nanotip advantageously is in the range of several 1 nm-10 μm, and the period P advantageously is in the range of 100 nm-10 μm. The maximum width ratio of the nanotips (width at the base:width at the top) is preferably 1000:1 and the maximum aspect ratio (height:width at the base) 1:1.

[0038] In a third step, a growth mask 3, in the example shown, amorphous SiO.sub.2, is deposited on the silicon substrate wafer 1. Different material, e.g. SiN, can also be used.

[0039] Finally, Si areas on the upper ends of the nanotips are uncovered which form the basis for a subsequent silicidation step. This can be done [0040] a) by a polishing step, e.g. by duration of chemical mechanical planarization (CMP) process, [0041] b) by a (wet) etching step, e.g. with hydrofluoric acid (HF), or [0042] c) by an anisotropic (wet) etching step, e.g. with potassium hydroxide (KOH).

[0043] Having uncovered tips as shown in b) and c) may lead to a deflection of dislocations in the GaN layer and thus provide a better quality. Examples a) and b) result in a planar surface, whereas example c) results in a rough surface with Si tips being recessed in SiO.sub.2 indentations. b) and c) offer the advantage of dislocation reduction through deflection. a) and b) are advantageous as they offer planar growth. c) can be desirable for specific applications due to a potential rough surface or 3D growth.

[0044] In FIG. 2 further steps according to preferred embodiments of the invention are shown. The steps shown are performed on a silicon wafer having silicon nanotips according to example a) of FIG. 1, shown in the middle of the first line of FIG. 2.

[0045] In a first step, a thin scandium (and/or yttrium, in another embodiment not shown) layer 4 is deposited all over the cleaned patterned silicon tip area. Alternatively, a KOH etch might be applied before to achieve <111> facetted Si tips.

[0046] In a second step, higher temperatures are applied to form ScSi.sub.x 5 as a preferred embodiment of Y.sub.1−zSc.sub.zSi.sub.x with 0≦z≦1 as group-IIIB silicide at the top of the Si tips (shown on the left of the first line of FIG. 2). Preferably, the ScSi.sub.x pads 5 have a (0001) orientation. It is to be noted that Ti is neighboring Sc in the periodic system and TiSi.sub.x processes for low resistance contacts are well established in Si microelectronics.

[0047] Since group-IIIB silicides exhibit a small lattice mismatch and a variation in their crystal structures it became possible to grow epitaxial group-IIIB silicides on Si(001) and Si(111) by depositing a thin group-IIIB metal layer and annealing (cf. C. Nörenberger et al., ib.; Baptist et al., Phys. Rev. Left. 64, 311 (1990); Rogero et al., Phys. Rev. B 66, 235421 (2002)). It is shown by AFM, STM and LEED studies that ScSi.sub.x can be formed with a hexagonal (0001) structure with 4.78% lattice mismatch on Si(111). Depending on the annealing temperature (450° C.-920° C.) different ScSi.sub.x surface reconstructions with a terrace width up to 200 nm were achieved. Thus, epitaxial single domain ScSi.sub.x films are formed on sufficiently small Si nanotips. It is to be noted that such a detailed surface science investigation is not known on Si(001), however XRD results indicate an orthorhombic ScSi structure at 500° C. and an hexagonal ScSi1.7 structure at 900° C., which is very similar with the behavior of Sc on Si(111).

[0048] In a further step (shown on the left of the second line), the residual Sc metal is removed from SiO.sub.2 areas by hydrochloride acid (HCl) etching resulting in the ScSi.sub.x pads 5 being still embedded in the SiO.sub.2 (example a)).

[0049] Optionally, a further HF etching step can be applied to completely uncover the ScSi.sub.x pads 5 (example b)) or to even remove the SiO.sub.2 almost completely (example c)) for reducing strain.

[0050] In the following, ScN islands 6 are deposited on the epitaxial ScSi.sub.x passivated surface (shown in line 3) as a preferred embodiment of Y.sub.1−xSc.sub.xN with 0≦x≦1 as group-IIIB nitride, e.g. by MBE or CVD process. Preferably, the ScN islands 6 have a (111) orientation.

[0051] In-situ nitridation of the (0001) ScSi.sub.x surface provides a few (up to 10) nm thick ScN(111) layer. A thin layer is preferred because of pronounced roughening tendency of the material. Nitridation is carried out using either NH.sub.3 gas or one of many plasma sources, including an electron cyclotron resonance (ECR) or a radio-frequency (rf) nitrogen plasma source.

[0052] ScN(111) epitaxy can also be grown on ScSi.sub.x using MBE technique (cf. eg. M. Moram et al., J. Cryst. Growth 308, 302 (2007)). This technique is in particular an option if thicker ScN films are required.

[0053] The morphology (faceting etc.) and size (small islands of a few microns up to a coalesced film) can be controlled by ELO parameters.

[0054] These Si/ScSi.sub.x/ScN pillar structures represent ideal nucleation sites for the low-strain and low-defect growth of group-IIIA nitride structures.

[0055] With nanopatterned Si substrates like Si nanotips on Si wafers, it becomes possible that the lattice mismatch strain between the epitaxial film and the substrate is not only stored in the substrate—as is inevitably the case for planar bulk Si substrates—but distributed between the growing epitaxial film and the nanopatterned Si tips. This so-called compliant effect is beneficial to favor the formation of coherent, only elastically relaxed interfaces between lattice mismatched semiconductors on Si. In other words, the so called critical thickness for the onset of plastic relaxation in the epitaxial film is substantially delayed; even to infinity in the most favorable conditions.

[0056] After formation of ScN, in a final optional step (shown in line 4), SiO.sub.2 can be etched away using HF chemistry from the template to deposit GaN. However, a thin SiO.sub.2 layer (<10 nm thick) can be intentionally left in between and on the side wall of the nanotips to protect further GaN deposition on these that helps to form a 3D void network as shown on the right of line 3.

[0057] Referring now to FIGS. 3 and 4, in a next step GaN is deposited on the ScN islands 6 as a preferred embodiment of In.sub.xAl.sub.zGa.sub.1−(x+z)N with 0≦x, z, (x+z)≦1 as group-IIIA nitride to produce a semiconductor wafer 10 according to a preferred embodiment of the invention. A coalesced GaN film 7 or GaN nanorods 8 (diameter preferably of several nanometers up to 10 μm; height preferably between several hundred nanometers and 10 μm) can be formed on the ScN islands 6 controlled by the depositing process parameters.

[0058] As mentioned above, growth of high quality GaN epilayers on Si is difficult. High density of threading dislocations due to ˜−17% in-plane lattice mismatches and severe wafer bow and even layer cracking due to more than 55% coefficient of thermal expansion (CTE) mismatches between GaN and Si are the main challenges. In addition, Si heavily reacts with impinging Ga and NH.sub.3 at high temperature that degrades the layer quality and wafer bow. AlN seed and AlGaN buffer layers are typically used to overcome these problems. Differently from the classical approach, according to the invention, the growth area of Si is covered with group-IIIB-Si.sub.x followed by group-IIIB-N. In conventional method of group-IIIA nitride film deposition on Si, SiN formation at Si and nitride film interface may cause an epitaxial relationship problem. However, the silicidation process avoids the formation of SiN. Proper design of pitch between nanotips and their height can limit the diffusion of reactive species inside the uncovered area in between nanotips. Basically, narrow pitch (P<3 μm) and a longer size (H>3 μm) of nanotips avoid nuclei formation at the bottom as well as on the sidewall of the structure (cf. eg. M.Ali et al., J. Cryst. Growth 315, 188 (2011)).

[0059] A faster growth of <0001> facet than <10-11> facet of GaN results in the formation of well-known pyramidal structure on patterned substrate (cf. e.g. A. Strittmatter et al., Appl. Phys. Lett. 78, 727 (2001); S. Tanaka et al., Appl. Phys. Lett. 79, 955 (2001)). However, due to growth rate anisotropy, lateral or vertical extension can be controlled by adjusting the group-V-IIIA ratio (NH.sub.3 and MO precursor flows), growth temperature and pressure. Lateral growth can be promoted with increased group-V-IIIA ratio and high growth temperature. A coalesced GaN film 7(FIG. 3) or nanorod structure 8 (FIG. 4) can be formed as a template for further device structure. GaN film or nanorod structures may consist of structures having a combination of group-IIIA elements (Al, Ga and In).

[0060] One concept of the invention to solve the wafer warpage problem in GaN on Si epiwafers and to reduce threading dislocation density in GaN epilayers is using nanoheteroepitaxy where the contact area between Si substrate and group-IIIA layer is less than 100%, preferably not more than 50% of the grown film. Thin structure of group-IIIB-Si.sub.x and group-IIIB-N are formed on the contact region between Si and group-IIIA nitride film to reduce the lattice mismatch whereas 3D void network is embedded in the non-contact region to absorb the strain evolving from thermal expansion coefficient mismatch between Si and nitride film. Size and distribution of growth surfaces for group-IIIA nitride epi can be tuned in a wide range in order to match the requirements for efficient strain management and dislocation reduction. It is possible to grow a coalesced group-IIIA nitride film or nanorod structure by designing the nanotips template structure and growth optimization of group-IIIA nitride.