DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

Abstract

A display panel, a manufacturing method thereof, and a display device are provided. The display panel is divided into a bending area and a non-bending area, and includes a thin film transistor layer corresponding to the non-bending area, an organic filling layer corresponding to the bending area, and a pixel electrode. The pixel electrode in the bending area is connected to a source of the thin film transistor layer in the non-bending area through a metal trace, the organic filling layer includes a plurality of second via holes, and an organic photoresist is filled in the plurality of second via holes.

Claims

1. A display panel, wherein the display panel is divided into a bending area and a non-bending area, and comprises: a substrate layer; a thin film transistor layer disposed on the substrate layer and corresponding to the non-bending area; an organic filling layer disposed on the substrate layer and corresponding to the bending area; a planarization layer disposed on the thin film transistor layer and the organic filling layer; a pixel electrode disposed on the planarization layer and connected to a source of the thin film transistor layer through a first via hole; and a pixel definition layer disposed on the planarization layer and corresponding to a gap of the pixel electrode, wherein the pixel electrode in the bending area is connected to the source of the thin film transistor layer in the non-bending area through a metal trace, the organic filling layer comprises a plurality of second via holes, and an organic photoresist is filled in the plurality of second via holes.

2. The display panel as claimed in claim 1, wherein the second via holes are spaced equally apart from one another.

3. The display panel as claimed in claim 1, wherein distribution densities of the second via holes gradually decrease from a center of the bending area to both sides.

4. The display panel as claimed in claim 1, wherein cross-sectional widths of the second via holes gradually decrease from a center of the bending area to both sides.

5. The display panel as claimed in claim 1, wherein depths of the second via holes range from greater than 0 to less than or equal to 20 microns.

6. The display panel as claimed in claim 5, wherein the depths of the second via holes are the same.

7. The display panel as claimed in claim 5, wherein the depths of the second via holes gradually decrease from a center of the bending area to both sides.

8. The display panel as claimed in claim 1, wherein shapes of the second via holes are selected from a group consisting of a circle, an ellipse, a sector, and a polygon.

9. A manufacturing method of a display panel, wherein the display panel is divided into a bending area and a non-bending area, and the manufacturing method comprises steps of: providing a substrate layer; forming a thin film transistor layer on the substrate layer and corresponding to the non-bending area; forming a plurality of second via holes on the substrate layer and corresponding to the bending area; filling an organic photoresist in the plurality of second via holes to form an organic filling layer; forming a planarization layer on the thin film transistor layer and the organic filling layer; forming a pixel electrode on the planarization layer, wherein the pixel electrode is connected to a source of the thin film transistor layer through a first via hole, and the pixel electrode in the bending area is connected to the source of the thin film transistor layer in the non-bending area through a metal trace; and forming a pixel definition layer on the planarization layer and corresponding to a gap of the pixel electrode.

10. The manufacturing method of the display panel as claimed in claim 9, wherein the second via holes are spaced equally apart from one another.

11. The manufacturing method of the display panel as claimed in claim 9, wherein distribution densities of the second via holes gradually decrease from a center of the bending area to both sides.

12. The manufacturing method of the display panel as claimed in claim 9, wherein cross-sectional widths of the second via holes gradually decrease from a center of the bending area to both sides.

13. The manufacturing method of the display panel as claimed in claim 9, wherein depths of the second via holes are the same.

14. The manufacturing method of the display panel as claimed in claim 9, wherein depths of the second via holes gradually decrease from a center of the bending area to both sides.

15. A display device, comprising a driver chip and a display panel, wherein the display panel is divided into a bending area and a non-bending area, and comprises: a substrate layer; a thin film transistor layer disposed on the substrate layer and corresponding to the non-bending area; an organic filling layer disposed on the substrate layer and corresponding to the bending area; a planarization layer disposed on the thin film transistor layer and the organic filling layer; a pixel electrode disposed on the planarization layer and connected to a source of the thin film transistor layer through a first via hole; and a pixel definition layer disposed on the planarization layer and corresponding to a gap of the pixel electrode, wherein the pixel electrode in the bending area is connected to the source of the thin film transistor layer in the non-bending area through a metal trace, the organic filling layer comprises a plurality of second via holes, and an organic photoresist is filled in the plurality of second via holes.

16. The display device as claimed in claim 15, wherein the second via holes are spaced equally apart from one another.

17. The display device as claimed in claim 15, wherein distribution densities of the second via holes gradually decrease from a center of the bending area to both sides.

18. The display device as claimed in claim 15, wherein cross-sectional widths of the second via holes gradually decrease from a center of the bending area to both sides.

19. The display device as claimed in claim 15, wherein depths of the second via holes are the same.

20. The display device as claimed in claim 15, wherein depths of the second via holes gradually decrease from a center of the bending area to both sides.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0026] FIG. 1 is a schematic diagram of a basic structure of a display panel of an embodiment of the present disclosure.

[0027] FIG. 2a to FIG. 2e are cross-sectional views of second via holes corresponding to a bending area of embodiments of the present disclosure.

[0028] FIG. 3 is a flowchart of a manufacturing method of a display panel of an embodiment of the present disclosure.

EMBODIMENT OF INVENTION

DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution, and the advantages of the present disclosure clearer and specific, further detailed descriptions of the present disclosure are stated here, referencing to the accompanying drawings and some preferred embodiments of the present disclosure. It should be understood that the detailed embodiments of the disclosure described here are used to explain the present disclosure only, instead of limiting the present disclosure.

[0030] FIG. 1 is a schematic diagram of a basic structure of a display panel of an embodiment of the present disclosure. The display panel is divided into a bending area A1 and a non-bending area A2. The display panel includes a substrate layer 101, a thin film transistor layer 102, an organic filling layer 103, a planarization layer 104, a pixel electrode 105, and a pixel definition layer 107. The thin film transistor layer 102 is disposed on the substrate layer 101 and corresponds to the non-bending area A2. The organic filling layer 103 is disposed on the substrate layer 101 and corresponds to the bending area A1. The planarization layer 104 is disposed on the thin film transistor layer 102 and the organic filling layer 103. The pixel electrode 105 is disposed on the planarization layer 104 and is connected to a source 1021 of the thin film transistor layer 102 through a first via hole 106. The pixel definition layer 107 is disposed on the planarization layer 104 and corresponds to a gap of the pixel electrode 105. The pixel electrode 105 in the bending area A1 is connected to the source 1021 of the thin film transistor layer 102 in the non-bending area A2 through a metal trace. The organic filling layer 103 includes a plurality of second via holes 109. The plurality of second via holes 109 are filled with an organic photoresist.

[0031] In one embodiment, the substrate layer 101 includes a first substrate layer 1011, a first buffer layer 1012 disposed on the first substrate layer 1011, a second substrate layer 1013 disposed on the first buffer layer 1012, and a second buffer layer 1014 disposed on the second substrate layer 1013.

[0032] In one embodiment, the thin film transistor layer 102 further includes an active layer 1022, a gate insulating layer 1023 disposed on the active layer 1022, a gate 1024 disposed on the gate insulating layer 1023, a second insulating layer 1025 disposed on the gate 1024, a second metal layer 1026 disposed on the second insulating layer 1025, a dielectric layer 1027 disposed on the second metal layer 1026, and a drain 1028 on the dielectric layer 1027. The source 1021 is connected to one end of the active layer 1022 through a third via hole 110, and a drain 1028 is connected to the other end of the active layer 1022 through a fourth via hole 111.

[0033] In one embodiment, the display panel further includes a spacer 108, and the spacer 108 is disposed on the pixel definition layer 107.

[0034] It should be noted that the display panel of an embodiment of the present disclosure includes at least one bending area A1. In the present disclosure, by disposing the thin film transistor layer 102 in the non-bending area A2, and not disposing the thin film transistor in the bending area A1, an electrical drift of the thin film transistor can be avoided when the thin film transistor is bent, thereby avoiding affecting display performance. Moreover, the pixel electrode 105 in the bending area A1 is connected to the source 1021 of the thin film transistor layer 102 in the non-bending area A2 through the metal trace. That is, the pixel electrode in the bending area A1 can be controlled by the thin film transistor in the non-bending area A2 such that the bending area A1 can also be displayed normally without affecting a resolution of the display panel. Also, in the present disclosure, the plurality of second via holes 109 are disposed under the metal trace and filled with the organic photoresist, so as to reduce a risk of the metal trace breaking due to a bending process and release the stress on each the film layer during bending. The present disclosure only changes the pixel structure in the bending area A1, so a scope of influence is minor, and it will not affect a reliability of the non-bending area A2.

[0035] In one embodiment, the metal trace connecting the pixel electrode 105 in the bending area A1 and the thin film transistor layer 102 in the non-bending area A2 can be the source 1021 (as shown in FIG. 1). Alternatively, it can be replaced by other wire that is more resistant to bending. In this embodiment, the pixel electrode 105 in the bending area A1 and the thin film transistor layer 102 in the non-bending area A2 are connected through the source 1021, and this structure can avoid a display failure caused by a broken scan line. Material of the source trace has strong bending resistance, and a risk of breaking due to the bending process is small. Moreover, the plurality of second via holes 109 are disposed under the source 1021 and filled with the organic photoresist, which can greatly relieve the stress on each film layer during bending.

[0036] It should be noted that, in the display panel of an embodiment of the present disclosure, a portion corresponding to the bending area A1 can be bent from an inside to an outside, or from the outside to the inside. A bending radius ranges from 0 to 20 mm.

[0037] It should be noted that the plurality of second via holes 109 are formed by etching, and a width of an etching area may be greater than a width of the bending area A1, that is, greater than πR, so as to better release the stress generated during bending. R refers to the bending radius of the display panel. The plurality of second via holes 109 are formed by being subjected to at least once dry etching. In some embodiments, the plurality of second via holes 109 can also be filled with other organic substances with strong bending resistance.

[0038] In one embodiment, cross-sectional widths of the second via holes 109 are the same (not shown in the drawings). Alternatively, the cross-sectional widths of the second via holes 109 gradually decrease from a center of the bending area A1 to both sides (as shown in FIG. 1, W1>W2). The bending area A1 of the present disclosure is done by forming via holes and filling them, and the widths of the second via holes 109 are predetermined. The widths of the second via holes 109 are adjusted according to the stress on the bending area A1, which greatly relieves the stress on each film layer during bending and reduces the risk of metal trace breaking.

[0039] In one embodiment, depths of the second via holes 109 range from greater than 0 to less than or equal to 20 microns. The depths of the second via holes 109 can be the same (not shown in the drawings). Alternatively, the depths of the second via holes 109 gradually decrease from the center of the bending area A1 to both sides (as shown in FIG. 1, D1>D2). In this embodiment, the depths of the second via holes 109 are determined, and the depths of the second via holes 109 are adjusted according to the stress of the bending area A1, which greatly relieves the stress on each film layer during bending and reduces the risk of metal trace breaking.

[0040] FIG. 2a to FIG. 2e are cross-sectional views of second via holes corresponding to a bending area of embodiments of the present disclosure. The second via holes 109 can be equally spaced apart from one another (as shown in FIG. 2a). Alternatively, distribution densities of the second via holes 109 gradually decrease from the center of the bending area to both sides (as shown in FIG. 2b). In these embodiments, distances between the second via holes 109 are predetermined. The distances between the second via holes 109 are adjusted according to the stress on the bending area A1, which greatly relieves the stress on each film layer during bending and reduces the risk of metal trace breaking.

[0041] In one embodiment, under a premise that a size of the bending area remains unchanged, the number of the second via holes 109 may be increased. As shown in FIG. 2c, the number of the second via holes 109 is predetermined. The number of the second via holes 109 is adjusted according to the stress on the bending area A1, which greatly relieves the stress on each film layer during bending and reduces the risk of metal trace breaking.

[0042] In one embodiment, shapes of the second via holes 109 are selected from a group consisting of a circle (as shown in FIG. 2a to FIG. 2c), an ellipse (as shown in FIG. 2d), a sector (not shown in the drawings), and a polygon (i.e., a hexagon as shown in FIG. 2e). In this embodiment, the shapes of the second via holes 109 are predetermined. The shapes of the second via holes 109 are adjusted according to the stress on the bending area A1, which greatly relieves the stress on each film layer during bending and reduces the risk of metal trace breaking.

[0043] FIG. 3 is a flowchart of a manufacturing method of a display panel of an embodiment of the present disclosure. The display panel is divided into a bending area and a non-bending area, and the manufacturing method includes the following steps.

[0044] In a step S301, a substrate layer is provided.

[0045] In a step S302, a thin film transistor layer is formed on the substrate layer and corresponds to the non-bending area.

[0046] In a step S303, a plurality of second via holes are formed on the substrate layer and corresponds to the bending area.

[0047] In a step S304, an organic photoresist is filled in the plurality of second via holes to form an organic filling layer.

[0048] In a step S305, a planarization layer is formed on the thin film transistor layer and the organic filling layer.

[0049] In a step S306, a pixel electrode is formed on the planarization layer. The pixel electrode is connected to a source of the thin film transistor layer through a first via hole, and the pixel electrode in the bending area is connected to the source of the thin film transistor layer in the non-bending area through a metal trace.

[0050] In a step S306, a pixel definition layer is formed on the planarization layer and corresponds to a gap of the pixel electrode.

[0051] It should be noted that the step S301 specifically includes the following. A first substrate layer is coated on a glass substrate. A first buffer layer is deposited on the first substrate layer. A second substrate layer is coated on the first buffer layer to form a double polyimide (PI) structure. A second buffer layer is deposited on the second substrate layer.

[0052] It should be noted that the step S302 specifically includes the following. An active layer is formed on the second buffer layer. The active layer is crystallized and patterned to form a TFT channel and a trace. A gate insulating layer and a first metal layer are deposited on the active layer. The first metal layer is patterned to form a gate and a scan line. A second insulating layer and a second metal layer are deposited on the gate. The second metal layer is patterned to form a second electrode of a storage capacitor and a discharge line. A dielectric layer is deposited on the second metal layer. A source and a drain are formed on the dielectric layer. The source is connected to one end of the active layer through a third via hole. The drain is connected to the other end of the active layer through a fourth via hole.

[0053] It should be noted that the, in the present disclosure, by disposing the thin film transistor layer in the non-bending area, and not disposing the thin film transistor in the bending area, an electrical drift of the thin film transistor can be avoided when it is bent, thereby avoiding affecting display performance. Moreover, the pixel electrode in the bending area is connected to the source of the thin film transistor layer in the non-bending area through the metal trace. That is, the pixel electrode in the bending area can be controlled by the thin film transistor in the non-bending area such that the bending area can also be displayed normally without affecting a resolution of the display panel. Also, in the present disclosure, the plurality of second via holes are disposed under the metal trace and filled with the organic photoresist, so as to reduce a risk of the metal trace breaking due to a bending process and release the stress on each the film layer during bending.

[0054] It should be noted that in the step S303, the plurality of second via holes may be spaced equally apart from one another. Alternatively, distribution densities of the plurality of second via holes gradually decrease from a center of the bending area to both sides. Their cross-sectional widths may be the same. Alternatively, the cross-sectional widths gradually decrease from the center of the bending area to both sides. Their depths range from greater than 0 to less than or equal to 20 microns. Their depths may be the same. Alternatively, the depths gradually decrease from the center of the bending area to both sides. Their shapes are selected from a group consisting of a circle, an ellipse, a sector, and a polygon. In the embodiments of the present disclosure, a size and depth of the holes in the bending area are gradually changed. Densities and depths of the holes are adjusted according to the stress of the bending area, which greatly relieves the stress on each film layer during bending, and reduces the risk of metal trace breaking.

[0055] It should be noted that the manufacturing method also includes forming a spacer on the pixel definition layer.

[0056] An embodiment of the present disclosure also provides a display device, including a driver chip and the above-mentioned display panel. The display device of the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet, a TV, a monitor, a notebook, a digital camera, a navigator, and so on.

[0057] In summary, in the display panel of the embodiments of the present disclosure, by disposing a thin film transistor in the non-bending area, the pixel electrode in the bending area is connected to the thin film transistor in the non-bending area through the metal trace. This can prevent a scan line from breaking due to a bending process, and the electrical properties of the thin film transistor will not be greatly shifted during bending. Moreover, the plurality of via holes are disposed under the metal trace in the bending area and filled with the organic photoresist, which can reduce the risk of the metal trace breaking and greatly relieve the stress on each the film layer when it is bent. Accordingly, it solves the technical problems in the prior art, such as a bendable display panel cannot achieve high resolution, a process is complicated, a manufacturing process is difficult, and electrical properties of a thin film transistor will drift with a bending process, thereby affecting display performance.

[0058] It should be understood that, to a person skilled in the art, equivalent substitution or modification may be made according to the technical solutions and invention concept of the present disclosure, and all these modifications or substitutions shall be encompassed in the scope of the claims of the present disclosure.